CN107861898A - A kind of High speed rear panel based on OpenVPX frameworks - Google Patents
A kind of High speed rear panel based on OpenVPX frameworks Download PDFInfo
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- CN107861898A CN107861898A CN201710969435.0A CN201710969435A CN107861898A CN 107861898 A CN107861898 A CN 107861898A CN 201710969435 A CN201710969435 A CN 201710969435A CN 107861898 A CN107861898 A CN 107861898A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
- G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/3003—Monitoring arrangements specially adapted to the computing system or computing system component being monitored
- G06F11/3024—Monitoring arrangements specially adapted to the computing system or computing system component being monitored where the computing system component is a central processing unit [CPU]
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/3055—Monitoring arrangements for monitoring the status of the computing system or of the computing system component, e.g. monitoring if the computing system is on, off, available, not available
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/3058—Monitoring arrangements for monitoring environmental properties or parameters of the computing system or of the computing system component, e.g. monitoring of power, currents, temperature, humidity, position, vibrations
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/409—Mechanical coupling
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F8/00—Arrangements for software engineering
- G06F8/60—Software deployment
- G06F8/65—Updates
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K7/00—Constructional details common to different types of electric apparatus
- H05K7/14—Mounting supporting structure in casing or on frame or rack
- H05K7/1438—Back panels or connecting means therefor; Terminals; Coding means to avoid wrong insertion
- H05K7/1459—Circuit configuration, e.g. routing signals
Abstract
The invention discloses a kind of High speed rear panel based on OpenVPX frameworks, including bus interface circuit and the supporting module using SOC hardware circuit realiration；Bus interface circuit includes 1 and exchanges board slot position, 3 signal transacting board slot positions, 1 collection board slot position, 1 interface conversion board slot position and 1 power supply board slot position.The configuration management for the load board that each groove position is carried is realized by supporting module, synchronizing signal and reset signal including the position offer of reception exchange board slot are simultaneously forwarded to other groove positions, and set I/O pin status to configure the functional status of each groove position in initialization；The High speed rear panel of this OpenVPX frameworks provided by the invention, solve the problems, such as existing 3U VPX bus communication circuits complex designing, flexibility and scalability difference.
Description
Technical field
The invention belongs to high-performance embedded process circuit technical field in real time, and in particular to one kind is based on OpenVPX framves
The High speed rear panel of structure.
Background technology
The major function of high-speed communication interconnection backboard is to realize on backboard the high speed signal interconnection between each module.At present
High-speed communication interconnection backboard often according to real system application carry out circuit design, topological structure and level division unobvious,
Backboard upper module does not have versatility, and the flexibility of complex circuit designs and circuit and expansion are poor.
OpenVPX standards are the high reliability meter provided for fields such as military, Aero-Space, national defence of VITA tissue issues
Calculation machine standard, to solve the problems, such as the compatible interoperation of different vendor's equipment room；The standard is in power supply distribution, system control, reference
Specification is given in terms of clock, separation, standard development, bottom plate, 3U system topologies and 6U system topologies.
OpenVPX also proposed the concept of " plane ", and plane refers to the physics and logical channel of equipment room interconnection；
OpenVPX planes include following 5 planes：
Utility plane：Most basic service is provided for system, such as：Power supply supplies, reference clock, low level
Signal for example systematic reset signal；
Management plane：For hardware resource of the organization and management based on IPMI standard, Management
Plane power supply can be with separating, to realize Management plane to each plate for the main power source of each board power supply in system
Power supply control；
Control plane：Using low latency, Medium-bandwidth, the communication pattern based on packet, by control access
(control traffic) distinguishes with data path (data traffic), it is ensured that the bandwidth of each path, and one is logical
The conflict on road does not interfere with another path；
Data plane：The data path of a set of high bandwidth, low latency is built between plate and on bottom plate；Dataplane can
With single starlike or double star shape, single-hop or multi-hop the MESH network of selection；Physical layer, logical layer, Internet communication protocol (including
Serial RapidIO and 10Gbit Ethernets) it can all be applied to Data plane.
Expansion plane：Master control borad and some tightly coupled process plates or I O board are connected；Expansion
Plane topologys are the mutual exclusion set with the tree of the root of each host node, and as data plane, expansion plane make
Its communication is supported with the passage of low latency, high bandwidth.
It is numerous that High speed rear panel based on existing OpenVPX standard architectures can solve existing processor backboard hardware circuit design
Trivial, the problem of autgmentability is poor, can not be unit level because OpenVPX standards only define JTAG debugging interfaces in plate level still
Unified debugging interface is provided, and there is different controllers, different type, different factories on other boards carried on backboard
Program burn writing software, flashburn tools, the equal disunity of programming interface of family's controller, in software debugging and upgrading, it can only pass through
The upgrading reparation that unit completes corresponding program is dismantled, virtually adds the cost and complexity of maintenance.
The content of the invention
For the disadvantages described above or Improvement requirement of prior art, the invention provides a kind of height based on OpenVPX frameworks
Fast backboard, it is complicated its object is to solve current information processing platform backplane signal, in the scheduling in face of a variety of type load tasks
Poor with resource distribution Time Bandwidth deficiency, Device-General and autgmentability, the problem of complicated, is safeguarded in board software upgrading.
To achieve the above object, according to one aspect of the present invention, there is provided a kind of high speed back of the body based on OpenVPX frameworks
Plate, including bus interface circuit and the supporting module using SOC hardware circuit realiration；Its bus interface circuit includes 1 exchange
Board slot position, 3 signal transacting board slot positions, 1 collection board slot position, 1 interface conversion board slot position and 1 power supply board slot position.
The configuration management of the load board carried to each groove position is realized by supporting module, including receives and exchanges board slot
Position provide synchronizing signal and reset signal simultaneously be forwarded to other groove positions, and initialization when set I/O pin status with
Put the functional status of each groove position.
Preferably, the above-mentioned High speed rear panel based on OpenVPX frameworks, the bus of each groove position of its bus interface circuit are based on
OpenVPX standards, include expanding flaggy, data Layer, key-course, management level and common layer, realize to exchange board slot position as control
The high-rate information transmission at center processed and other groove positions, and the data message interaction between each independent groove position；
Feature is：
Flaggy is being expanded, there is the first GTP interfaces on each signal transacting board slot position, by the first GTP interfaces by 3 signals
Processing board slot position connects, to realize the high speed data transfer between Signal transacting board analysis and board.
Flaggy is being expanded, there is the 2nd GTP interfaces on each signal transacting board slot position and collection board slot position, pass through second
GTP interfaces connect 3 signal transacting board slot positions and collection board slot position, form an annular path.
The collection plate that collection board slot position is carried is mainly used in generating linear FM signal, the signal of collection channel transmission,
And data prediction.Because each signal transacting board slot position can carry the algorithm of different signal-processing board realizations and differ,
The data of processing also can be variant, it is therefore desirable to which the data that signal-processing board is sent to collection plate carry out after-treatment；It can lead to
Cross increases daughter board on motherboard, the signal-processing board being made up of 2 pieces of circuit boards of motherboard and daughter board, and the processor of motherboard is mainly
DSP, for algorithm process, the processor of daughter board is mainly fpga chip, for signal transacting, with one accurate matching institute of construction
The data channel of algorithm and performance requirement is needed, extends the process performance and transmission bandwidth of motherboard, fpga chip processing on daughter board
Data then carry out data interaction by the 2nd GTP interfaces on backboard between each signal transacting board slot position and collection board slot position, real
Distribution, after-treatment and data interaction of the carrier signal on unlike signal processing board slot position after now handling, improves system
Parallel processing capability.
In data Layer, exchanging on board slot position, 3 signal transacting board slot positions and collection board slot position has RapidIO interfaces, and
The RapidIO interfaces exchanged on board slot position pass through in carried power board with the RapidIO interfaces on other groove positions
Serial RapidIO exchange chips are attached, and form the serial RapidIO interference networks of 4X, and the serial RapidIO of 4X include 4 pairs
Differential pair line is sent, differential pair line is received in 4 docking, and each pair RapidIO transmission rates are 3.125Gbps, pass through the serial RapidIO
The high speed transmission of signals not less than 5Gbps can be achieved in data/address bus between each groove position, realizes carried power board and collection
The reliably multi-point interaction of image transmitting and command information between plate, signal-processing board.
In key-course, exchange have on board slot position, 3 signal transacting board slot positions and collection board slot position Ethernet interface and
The Ethernet interface of Ethernet interface and other groove positions on exchange board slot position passes through the Ethernet on carried power board and connect
Mouth control chip is attached, and is formed the multi-node communication networks based on industry ethernet, is transmitted by industry ethernet
Position machine is sent to the transmission order for exchanging board slot position, programming file command, and the shape for exchanging groove position and returning is sent to host computer
State information；And programming file is transferred to by specified slot by above-mentioned industry ethernet interface according to the status information by host computer
Position；Realize that the control information on backboard between each groove position and external interface interacts.
The interface chip that is connected on industry ethernet supports serial gigabit Ethernet, support MII GMII RGMII SGMII
The I/O mouth mold formulas of interface, the I/O port numbers for the SGMII interfaces that the present invention uses are few, are easy to PCB layout, and data-signal
Occur in the form of differential pair, advantageously ensure that signal integrity.
In management level, exchanging on board slot position, 3 signal transacting board slot positions and collection board slot position has PMBUS interfaces, each groove
It is connected between position by PMBUS buses, the load board carried by the PMBUS buses offer on power board to each groove position
Management；Including the self-test to each groove position board, BIT tests, program upgrading, power management, health control, reset management, clock
Management and/or pair when；The management signal issued by power board is by exchanging the PMBUS interfaces of board slot position via under PMBUS buses
Each groove position is dealt into, the feedback signal of the board of each groove position carrying is returned to by the PMBUS interfaces of each groove position via PMBUS buses
Board slot position is exchanged, and then is sent to carried exchange board.
In common layer, including system clock bus, reset signal bus and power bus；By what is loaded suitable for groove position
The electric signal of board processor power-up is connected to the SOC of supporting module by PMBUS EBIs, to realize that board powers up
Management；Electric signal size needed for other each board grooves is converted on backboard by the electric signal for providing power supply board slot position
Each load board power-up, to realize that the power supply electric signal respectively loaded on backboard inputs.
Preferably, the above-mentioned High speed rear panel based on OpenVPX frameworks, its supporting module include reset unit, I/O pin-likes
State setting unit and signal synchronization unit；
Wherein, the initial reset signal that reset unit is used to transmit reception exchange board slot position generates other groove position plates and resetted
Signal is simultaneously sent to corresponding groove position；
I/O pin status setting unit is used to be located at different address according to what the power board that exchange board slot position is carried issued
On each groove position each groove position board of I/O pin status information initializings I/O pin status, carried with to set each groove position
The functional status of board；
Signal synchronization unit is used to receive the initial differential synchronizing signal of power board transmission and output difference is synchronously believed respectively
Number daughter board carried to other groove positions.
Preferably, the above-mentioned High speed rear panel based on OpenVPX frameworks, its interface conversion board slot position receive various external signals
Input, the convectional signals that electrical signal format is converted to other groove positions on backboard by the interface on the interface conversion board slot position are determined
Adopted form；
Conventional RS422, LVDS, 1553B electric signal is defined on the interface conversion board slot position, can directly and power board
RS422, LVDS, 1553B electric signal interface on groove position is attached, and extends workable signaling interface on backboard.
Preferably, the above-mentioned High speed rear panel based on OpenVPX frameworks, jtag interface is respectively provided with each groove position, to realize
The plate level debugging for the board that each groove position is carried, and be connected in the SOC of supporting module and built using these jtag interfaces
Vertical JTAG link, the unified interface of complete machine level is introduced by the JTAG mouths on interface conversion board slot position, dismounting can not be had in complete machine
In the case of in single board chip software code carry out maintenance upgrade operation.
In general, by the contemplated above technical scheme of the present invention compared with prior art, it can obtain down and show
Beneficial effect：
(1) High speed rear panel provided by the invention based on OpenVPX frameworks, as a result of interface conversion board slot position, greatly
Accessible signal type is extended greatly, can be accessed all kinds of external signals according to system requirements, is then sent to exchange
Signal transacting is carried out on board slot position, during applied in different systems, reduces the signal on backboard and redefines work, therefore solve
The problem of existing 3U VPX bus communication circuits complex designing, flexibility and scalability difference of having determined；
(2) High speed rear panel provided by the invention based on OpenVPX frameworks, the supporting module realized as a result of SOC,
The intelligence power-up and health monitoring to the processor chips on the board of each groove position can be realized, is supported each needed for processor chips
Kind of level signal, can Acquisition Processor die temperature information, power-up state；JTAG chains can be realized, there is provided the plate of complete machine level
Card debugging interface, therefore the monitoring management and software upgrading of each board processor chips for being carried on backboard can be realized
Safeguard, reduce the complexity of power-supply wiring and board state monitoring, reduce the complexity of complete machine software upgrading maintenance, enhancing
Flexibility, add the range of choice of each groove position upper plate Card processor chip；
In general, the present invention supporting module that increase soc is realized, is established by optimizing backboard hardware interface design
JTAG chains, in the system-level upgrading renewal for providing each control chip in unified interface completion system so that follow-up soft of product
Part maintenance upgrade becomes extremely convenient, substantially increases maintainability, the ease for use of product；Solves the current information processing platform back of the body
Partitioned signal is complicated, when in face of the scheduling and resource distribution of a variety of type load tasks, the bandwidth deficiency that is faced, real-time compared with
Difference, Device-General and autgmentability are poor, and the problem of complicated is safeguarded in board software upgrading.
Brief description of the drawings
Fig. 1 is the topological structure signal of one embodiment of the High speed rear panel provided by the invention based on OpenVPX frameworks
Figure；
Fig. 2 is the exchange board slot position signal distribution schematic diagram in embodiment；
Fig. 3 is the signal transacting board slot position signal distribution schematic diagram in embodiment；
Fig. 4 is the mixed communication board slot position signal distribution schematic diagram in embodiment；
Fig. 5 is the interface conversion board slot position signal distribution schematic diagram in embodiment；
Fig. 6 is the supporting module signal distribution schematic diagram in embodiment；
Fig. 7 is the drive software state flow chart in embodiment.
Embodiment
In order to make the purpose , technical scheme and advantage of the present invention be clearer, it is right below in conjunction with drawings and Examples
The present invention is further elaborated.It should be appreciated that the specific embodiments described herein are merely illustrative of the present invention, and
It is not used in the restriction present invention.As long as in addition, technical characteristic involved in each embodiment of invention described below
Conflict can is not formed each other to be mutually combined.
The High speed rear panel based on OpenVPX frameworks that embodiment provides, its topological structure is as shown in figure 1, be with power board
Based on groove position, to gather board slot position, signal transacting board slot position as the master-slave mode topological structure from composition；
Bus between each groove position is divided by function including expanding flaggy, data Layer, key-course, management level and common layer
Connection bus, realize to exchange high-rate information transmission of the groove position as control centre and other groove positions, and to pass through GTP interfaces real
The now data message interaction between each individual loads groove position.
Feature is：Flaggy is being expanded, there is GTP interfaces on each signal transacting board slot position, is being believed 3 by GTP interfaces
Number processing board slot position connects, to realize the high speed data transfer between Signal transacting board analysis and board；In the present embodiment, it is
The high speed data transfer on signal-processing board between FPGA is realized, GTP interfaces use the VIRTEX FPGA systems of xlinx companies
Arrange supporting rocketIO GTP.
Flaggy is being expanded, there is GTP interfaces on each signal transacting board slot position and collection board slot position, by GTP interfaces by 3
Individual signal transacting board slot position and collection board slot position connect, and form an annular path.What collection board slot position was carried adopts
Collection plate is mainly used in generating linear FM signal, the signal of collection channel transmission, and data prediction.Due to each signal transacting
Board slot position can carry the algorithm that different signal-processing boards is realized and differ, and the data of processing also can be variant, it is therefore desirable to
The data that signal-processing board is sent to collection plate carry out after-treatment；Can be by increasing daughter board on motherboard, by motherboard and son
The signal-processing board that 2 pieces of circuit boards of plate are formed, the processor of motherboard is mainly DSP, for algorithm process, the processor master of daughter board
To be fpga chip, for signal transacting, with the data channel of algorithm and performance requirement, extension needed for one accurate matching of construction
The process performance and transmission bandwidth of motherboard, the data of fpga chip processing are then by the 2nd GTP interfaces on backboard each on daughter board
Data interaction is carried out between signal transacting board slot position and collection board slot position, the FM signal after realization processing is in unlike signal processing
Distribution, after-treatment and data interaction on board slot position, improve the parallel processing capability of system.
SLOT0 is exchanges board slot position, and SLOT1,2,4 are general signal processing module groove position, SLOT3 is mixed communication board slot
Position, SLOT5 is interface conversion board slot position, and SLOT6 is power supply board slot position；
Clock is defined on SLOT0 P0 connectors, reset, synchronizing signal terminal, PMBUS are output to SLOT1~4；SLOT1
The P1 connectors that 4x SRIO are connected to SLOT0 are defined on~4 P1 connectors；The P2 connectors of SLOT1~4 define 4x
SGMII interfaces are connected to SLOT0 P2 connectors；The P2 connectors of SLOT1~4 define the interconnection of 2x GTP ring-types；SLOT0 has
1 group of 1553B bus, 1 group of PHY industry ethernet, 2 groups of RS422 buses and 1 group of CamerLink bus are connected to SLOT5；SLOT6
By the P0 connectors of SLOT0~5 power supply is provided for SLOT0~5.
Fig. 2 is the signal distribution schematic diagram for exchanging board slot position terminal in embodiment；Slot0 is as carrying power board business
The groove position of unit, the J0 connectors of slot0 grooves position are the signaling interface of common layer；When the board carried inserts corresponding groove position
When, the J0 connectors on backboard groove position are connected with the card connector P0 of inserted board, the J1 connectors on backboard groove position with
The card connector P1 of inserted board is connected, the card connector P2 phases of the J2 connectors on backboard groove position and inserted board
Even.
J0 connectors on backboard groove position include backboard main power source input terminal, baseband board address number input terminal GA
[4：0], baseband board address number check bit input terminal GAP, 100MHz System Clock Reference input terminal, systematic unity triggering
Input terminal (SYNC synchronizing signals), system power-on reset input terminal (SYSRESET reset signals), it is defeated that signal is managed between plate
Enter terminal ((I2C) SM [3：0]) and the related TRST, TMS of debugging, TDI, TDO, tck signal input terminal.
The J1 connectors of slot0 grooves position are the signaling interface of data Layer, and wafer1-wafer12 is defined as RapidIO data
EBI, respectively 4X RapidIO patterns, 8 differential signals on remaining wafer13-wafer16 can carry out from
Definition, it can also be used as and be used for single-ended signal.Specifically, have reserved unnecessary electric signal interface on this interface, and these connect
Mouth had both supported differential signal or had supported single-ended signal, needed to be defined with specific reference to board on groove position；According on slot0 grooves position
Board demand, if necessary to additional differential signal, can be added above, it is not necessary to which differential signal can also be directly as
Single-ended signal.
The J2 interfaces of slot0 grooves position are the signaling interface of key-course, and it is total that wafer5-wafer7 is defined as serial Ethernet
Line interface, respectively 4X SGMII patterns；Remaining differential signal may be defined as the signal input for board debugging, such as
RS422, LVDS, RS232,1553B signal.In embodiment, defined on interface conversion board slot position conventional RS422, LVDS,
1553B electric signals, it can directly be attached, extend with RS422, LVDS, 1553B electric signal interface exchanged on board slot position
Workable signaling interface on backboard.There are a large amount of remaining signaling interfaces to be not used on board, and these electric signal interface branch
Various main flow communication signal interfaces, such as RS422, LVDS, 1553B are held, if transmitting this kind of signal on the board that groove position is carried,
It can then draw and be connected on the remaining interface of J2 interfaces on P2 connectors.
Fig. 3 is the signal distribution schematic diagram of the signal transacting board slot position terminal in embodiment；Slot1 grooves position, slot2 grooves
Position, groove position of the slot4 grooves position as carrying signal process plate business unit, this 3 business unit have interchangeable feature, because
The terminal of this this 3 groove position is defined using unified definition mode；
Single-ended signal J0 terminals are defined as the signaling interface of common layer, keep unified with slot0 signal definition, J1 terminals
Wafer1-wafer4 be signally attached to as RapidIO data bus interfaces, wafer16 as the SGMII of Ethernet interface
The groove position of power board 0, the single-ended signal on wafer1-wafer7 are defined as RS232 AccessPort signals；The wafer5- of J2 terminals
Wafer8 can form the GTP interfaces of Loop communication, respectively 2XGTP patterns, for receiving as expansion interface between board
The 2XGTP signals come from daughter board FPGA；Remaining terminal retains as spare interface, may be configured as differential signal and may be alternatively provided as list
End signal；GTP interfaces are then by GTP interfaces on backboard in each signal transacting for the data for handling fpga chip on daughter board
Data interaction is carried out between board slot position and collection board slot position, the FM signal after realization processing is on unlike signal processing board slot position
Distribution, after-treatment and data interaction, improve the parallel processing capability of system.
The signal of mixed communication board slot position slot3 in embodiment distributes schematic diagram as shown in figure 4, the J0 of slot3 grooves position
Terminal is defined as the signaling interface of common layer, keeps unified with the signal definition on slot0, the wafer1-wafer4 of J1 terminals
As RapidIO data bus interfaces, wafer16 is signally attached to the groove position of power board 0 as the SGMII of Ethernet interface；J2
The wafer5-wafer8 of terminal can form the GTP interfaces of Loop communication, respectively 2XGTP as expansion interface between board
Pattern, for receiving the 2XGTP signals come from daughter board FPGA.The wafer9-wafer16 of J2 terminals is defined as LVDS difference letter
Number.
The terminal definition of interface conversion board slot position slot5 in embodiment is as shown in figure 5, J0 terminals are defined as backboard input
Master battery signal and debugging interface signal, the wafer10-wafer16 of J1 terminals is as external interface input signal.Because
In OpenVPX standards, it is differential signal not have strict definition to groove position connector terminals, but at the connector end of board
Sub-definite difference form and single-ended format, therefore, remaining interface for example J0 on slot5 J1 the signaling interface such as J2 in platform
It is middle to retain as spare interface, it can define other interface signals when external interface changes.
Control circuit is powered by power module on backboard, and operating voltage is 5V ± 0.15V, and electric current is not more than 1A.Backboard connects
Connect device mainly by the 1410186-1J0VPX sockets of Tyco companies, 1410140-1J1VPX sockets, 1410142-1J2VPX sockets,
1469491 leads and 6450869-4 power module VPX sockets are formed.Relative to traditional pin type connector, this VPX
The silicon wafer slice structure of high-speed-differential connector have be completely embedded, the small advantage such as low with the bit error rate of insertion loss, each difference
Contact and 10GB/s may be up to the data bandwidth of support, and silicon wafer all carries ESD ground planes and contact layer, prevents the operation phase
Between influenceed by accidental discharge.
The High speed rear panel based on OpenVPX frameworks that embodiment provides, its supporting module are divided by function including resetting
Unit, I/O pin status setting unit and signal synchronization unit；Realized using SOC, Fig. 6 is the branch hold mode in embodiment
Block signal distributes schematic diagram.In embodiment, SOC using Microsemi A2F500M3G-1FGG400.Backboard bottom drives
Dynamic running software is main to complete Clock management interface, synchronizing signal interface, JTAG switching interfaces, reseting interface in SOC
Function.It is illustrated in figure 7 the flow chart that backboard bottom layer driving software is configured.
Wherein, reset unit inputs initial reset signal by power board, then export respectively through SOC reset signal to
Other four daughter boards；During running software, reset signal initialization is carried out first, the initial reset signal vpx_ that power board is exported
Sysreset_L0 is assigned to each daughter board reset signal respectively；
I/O pin status setting unit sets the functional status of each daughter board by initializing I/O pin status；Software
During operation, the initialization of I/O pins, it is low level 0 to set each daughter board I/O pins；
Signal synchronization module inputs initial differential synchronizing signal by power board, then same through SOC difference output difference
Step signal gives other four daughter boards.During running software, synchronizing signal initialization, synchronous difference of the sync_in functions power board
Signal vpx_L0_sync_n, vpx_L0_sync_p are converted into signal sync_in, while sync functions are input signal sync_
In is separately converted to the synchronous difference signal of each daughter board.
The above-mentioned High speed rear panel based on OpenVPX that embodiment provides, topological structure and level division are obvious, the spirit of circuit
Activity and expansion are good, effectively realize the cooperative high speed interconnection of multipath serial bus interface, including gigabit Ethernet connects
Mouthful, RapidIO interfaces, PMBUS EBIs, PMBUS100KHz, Ethernet transmission rate 1000Mbps, GTP transmission rate are not
Less than 2.5GHz, HyperLInk transmission rates are not less than 3.125GHz, and PCIE transmission rates are not less than 3.125GHz, and SRIO is passed
Defeated speed is not less than 3.125GHz, and data rate is not less than 5Gbps.The chip selected in hardware circuit of the present invention, can be with having
Identical function, other chips of equivalent specifications are alternative.
As it will be easily appreciated by one skilled in the art that the foregoing is merely illustrative of the preferred embodiments of the present invention, not to
The limitation present invention, all any modification, equivalent and improvement made within the spirit and principles of the invention etc., all should be included
Within protection scope of the present invention.
Claims (9)
1. a kind of High speed rear panel based on OpenVPX frameworks, it is characterised in that including bus interface circuit and using SOC hardware
The supporting module of circuit realiration；
The bus interface circuit includes 1 and exchanges board slot position, 3 signal transacting board slot positions, 1 collection board slot position, 1 interface
Change board slot position and 1 power supply board slot position；
The configuration management of the load board carried to each groove position is realized by the supporting module, including receives and exchanges board slot
Position provide synchronizing signal and reset signal simultaneously be forwarded to other groove positions, and initialization when set I/O pin status with
Put the functional status of each groove position.
2. High speed rear panel as claimed in claim 1, it is characterised in that the bus of each groove position of bus interface circuit is based on
OpenVPX standards, include expanding flaggy, data Layer, key-course, management level and common layer, realize to exchange board slot position as control
The high-rate information transmission at center processed and other groove positions, and the data message interaction between each independent groove position；
Flaggy is being expanded, there is the first GTP interfaces on each signal transacting board slot position, by the first GTP interfaces by 3 signal transactings
Board slot position connects, to realize the high speed data transfer between Signal transacting board analysis and board；
Flaggy is being expanded, there is the 2nd GTP interfaces on each signal transacting board slot position and collection board slot position, connect by the 2nd GTP
Mouth connects 3 signal transacting board slot positions and collection board slot position, an annular path is formed, to cause carried letter
On number process plate daughter board the data of fpga chip processing by the 2nd GTP interfaces in each signal transacting board slot position and collection plate
Data interaction is carried out between groove position, realizes that the carrier signal after carried signal-processing board processing handles board slot in unlike signal
Distribution, after-treatment and data interaction on position, improve the parallel processing capability of system.
3. High speed rear panel as claimed in claim 2, it is characterised in that
In data Layer, exchanging on board slot position, 3 signal transacting board slot positions and collection board slot position has RapidIO interfaces, and exchanges
RapidIO interfaces on board slot position pass through the Serial on carried power board with the RapidIO interfaces on other groove positions
RapidI/O exchange chips are attached, and form RapidIO internet, realize using the power board carried be main control module and
The multi-point interaction of reliable image transmitting and command information between the board carried on other groove positions.
4. High speed rear panel as claimed in claim 2 or claim 3, it is characterised in that
In key-course, exchanging on board slot position, 3 signal transacting board slot positions and collection board slot position has Ethernet interface, and exchanges
The Ethernet interface of Ethernet interface and other groove positions on board slot position passes through the Ethernet interface control on carried power board
Coremaking piece is attached, and forms the multi-node communication networks based on industry ethernet, and host computer is transmitted by industry ethernet
The transmission order for exchanging board slot position, programming file command are sent to, and is sent to host computer and exchanges the state letter that groove position returns
Breath；And programming file is transferred to by specified slot position by the industry ethernet interface according to the status information by host computer；It is real
Control information on existing backboard between each groove position and external interface interacts.
5. High speed rear panel as claimed in claim 2 or claim 3, it is characterised in that
In management level, exchanging has PMBUS interfaces on board slot position, 3 signal transacting board slot positions and collection board slot position, each groove position it
Between be connected by PMBUS buses, the management of the board carried to each groove position is provided by PMBUS buses on power board, by
The management signal that power board issues is issued to each groove position, each groove position by exchanging the PMBUS interfaces of board slot position via PMBUS buses
The feedback signal of the board of carrying is returned to via PMBUS buses by the PMBUS interfaces of each groove position and exchanges board slot position, Jin Erfa
It is sent to carried exchange board.
6. High speed rear panel as claimed in claim 2 or claim 3, it is characterised in that
In common layer, including system clock bus, reset signal bus and power bus；The board that will be loaded suitable for groove position
The electric signal of processor power-up is connected to the SOC of supporting module by PMBUS EBIs, to realize board power-up pipe
Reason.
7. High speed rear panel as claimed in claim 1 or 2, it is characterised in that the supporting module include reset unit arranged side by side,
I/O pin status setting unit and signal synchronization unit；
The initial reset signal that the reset unit is used to receive the transmission of exchange board slot position generates other groove position plate reset signals
And it is sent to corresponding groove position；
The I/O pin status setting unit is used to be located at different address according to what the power board that exchange board slot position is carried issued
On each groove position each groove position board of I/O pin status information initializings I/O pin status, carried with to set each groove position
The functional status of board；
The signal synchronization unit is used to receive the initial differential synchronizing signal of power board transmission and output difference is synchronously believed respectively
Number daughter board carried to other groove positions.
8. High speed rear panel as claimed in claim 1 or 2, it is characterised in that the interface conversion board slot position receives various outsides
Signal is inputted, and electrical signal format is converted to the signal lattice of other groove positions on backboard by the interface on the interface conversion board slot position
Formula；
RS422, LVDS, 1553B electric signal are defined on the interface conversion board slot position, can be directly with exchanging on board slot position
RS422, LVDS, 1553B electric signal interface are attached, and extend workable signaling interface on backboard.
9. High speed rear panel as claimed in claim 1 or 2, it is characterised in that jtag interface is respectively provided with each groove position, it is each to realize
The plate level debugging for the board that groove position is carried, and be connected to using these jtag interfaces in supporting module and establish JTAG link,
The unified interface of complete machine level is introduced by the JTAG mouths on interface conversion board slot position, can be in the case where complete machine have to dismounting to list
Software code in board chip carries out maintenance upgrade.
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| CN201710969435.0A CN107861898A (en) | 2017-10-18 | 2017-10-18 | A kind of High speed rear panel based on OpenVPX frameworks |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201710969435.0A CN107861898A (en) | 2017-10-18 | 2017-10-18 | A kind of High speed rear panel based on OpenVPX frameworks |
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| CN107861898A true CN107861898A (en) | 2018-03-30 |
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| CN201710969435.0A Pending CN107861898A (en) | 2017-10-18 | 2017-10-18 | A kind of High speed rear panel based on OpenVPX frameworks |
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| CN113098820A (en) * | 2021-04-02 | 2021-07-09 | 中科院计算技术研究所南京移动通信与计算创新研究院 | Multi-carrier signal processing device and method based on VPX architecture |
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| CN113612742A (en) * | 2021-07-23 | 2021-11-05 | 中国人民解放军军事科学院国防科技创新研究院 | Multi-mode search and rescue signal processing device based on VPX framework |
| CN113612742B (en) * | 2021-07-23 | 2023-04-18 | 中国人民解放军军事科学院国防科技创新研究院 | Multi-mode search and rescue signal processing device based on VPX framework |
| CN115412155A (en) * | 2022-08-19 | 2022-11-29 | 西安微电子技术研究所 | Motherboard of satellite-borne large-bandwidth elastic heterogeneous resource data processing system |
| CN115412155B (en) * | 2022-08-19 | 2023-11-03 | 西安微电子技术研究所 | Motherboard of satellite-borne large-bandwidth elastic heterogeneous resource data processing system |
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Application publication date: 20180330 |