CN108270877B - Distributed network node data sharing system - Google Patents
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- CN108270877B CN108270877B CN201810394736.XA CN201810394736A CN108270877B CN 108270877 B CN108270877 B CN 108270877B CN 201810394736 A CN201810394736 A CN 201810394736A CN 108270877 B CN108270877 B CN 108270877B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L67/00—Network arrangements or protocols for supporting network services or applications
- H04L67/01—Protocols
- H04L67/10—Protocols in which an application is distributed across nodes in the network
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L67/00—Network arrangements or protocols for supporting network services or applications
- H04L67/01—Protocols
- H04L67/10—Protocols in which an application is distributed across nodes in the network
Abstract
The application provides a distributed network node data sharing system, which is composed of a plurality of signal processing modules and a high-speed data link switching module, wherein the signal processing modules are used for processing and storing currently received network node data and accessing the network node data stored in other signal processing modules through the high-speed data link switching module. The distributed network node data sharing system can distribute a plurality of network node data to a plurality of signal processing modules for processing through the modularized arrangement, and share the data among the signal processing modules through the high-speed data link switching module, and when the signal processing modules in the distributed network node data sharing system are expanded, the data access of the signal processing modules establishing the sharing link based on the high-speed data link switching module is not influenced. The aim that the parallel processing of data is not influenced when the system is expanded is achieved.
Description
Technical Field
The invention relates to the technical field of data processing, in particular to a distributed network node data sharing system.
Background
Radars are electronic devices that detect objects using electromagnetic waves. The radar emits electromagnetic waves to irradiate a target and receives the echo of the target, so that information such as the distance from the target to an electromagnetic wave emission point, the distance change rate (radial speed), the azimuth and the altitude is obtained.
And aiming at the processing of radar real-time signals, a parallel processing algorithm is mostly adopted. At present, there are two main processing methods, one is a parallel processing method based on a pipeline, and the other is a processing method based on data parallel.
The core idea of the parallel processing method based on the pipeline is as follows: dividing the processing algorithm into a plurality of subtasks according to the data flow direction, mapping each subtask to a corresponding processing node, and enabling the data flow to flow in a serial and unidirectional mode in the plurality of subtasks. The method needs a separate hardware matrix transpose processing board, and requires high coupling degree between the system and the hardware, and the universality and the expandability are poor due to different programs of a plurality of processing nodes.
The data parallel-based processing method mainly comprises parallel processing of shared storage. In the process of parallel processing by adopting shared storage, because the communication of the nodes uses the shared storage, a plurality of nodes share the bus, and when the data of the system nodes is more, the memory access bandwidth becomes the bottleneck of the system, which is not beneficial to the system expansion.
As can be seen from the above, the parallel data processing methods in the prior art all have the problem of being not favorable for system expansion.
Disclosure of Invention
In view of this, the embodiments of the present invention provide a distributed network node data sharing system, so as to solve the problem that the existing parallel processing methods for radar real-time signals are not conducive to system expansion.
In order to achieve the above purpose, the embodiments of the present invention provide the following technical solutions:
a distributed network node data sharing system, comprising: a plurality of signal processing modules and a high-speed data link switching module;
the signal processing module is used for processing and storing the currently received network node data, and accessing the network node data stored in other signal processing modules through the high-speed data link switching module;
the high-speed data link switching module is used for data transmission among a plurality of signal processing modules which process the network node data in parallel.
Optionally, the signal processing module includes a plurality of signal processors;
the signal processors are connected through hyperlink Hyper Link interfaces and used for processing and storing currently received network node data;
and data exchange access is carried out among the plurality of signal processors through the Hyper Link interface.
Optionally, the signal processing module includes a plurality of signal processors;
the signal processors are connected through a high-speed network switching 4X SRIO interface, and are used for processing and storing currently received network node data;
and data exchange access is carried out among the plurality of signal processors through the 4X SRIO interface.
Optionally, the signal processing module is a multi-core digital signal processing DSP board, and the multi-core DSP board includes 4 DSP processors, 1 field programmable gate array intermediate layer board FMC slot, 4 gigabit ethernet interfaces, 1 4X PCIe interface, 6 high-speed network switch 4X SRIO interfaces, 4 serial ports, and a general IO interface;
each DSP processor is connected with the memory module through a DDR3 interface, connected with the memory through an EMIF interface and connected with the expansion memory through an SPI interface;
4 pieces of DSP processors carry out data interaction through the high-speed data link exchange module through the 4X SRIO interfaces;
the FMC slot is provided with 1 FMC interface, 1 DDR3 interface, 1 4X SRIO interface, 1 4X PCIe interface and 2 4X GTX interfaces;
connecting 4 pieces of DSP processors with the FMC slot through a PCIe exchange piece and a 4X PCIe interface on the FMC slot, and expanding an 8X PCIe interface to be connected to a P1 connector of a bus VPX;
connecting 4 pieces of DSP processors with the FMC slot through SRIO switch pieces and 4X SRIO interfaces on the FMC slot, and extending 6 4X SRIO interfaces to be connected to the P1 connector and the P2 connector of the VPX;
and 4 DSP processors carry out program loading through the FMC slot.
Optionally, a hyperlink Hyper Link interface is further arranged on the DSP processor;
and 4 DSP processors positioned on the same signal processing module carry out data interaction through the Hyper Link interface.
Optionally, each of the DSP processors on different signal processing modules performs data transmission through the first 4X SRIO interface.
Optionally, if the distributed network node divides the complex number point matrix data into m × n matrices according to the distance dimension and the azimuth dimension, after receiving the distributed network node data, equally allocating each distance line of the matrices to memories of m DSP processors, and equally allocating each direction line of the matrices to memories of n DSP processors, where m and n are positive integers, and a value of m or n is 2.
Optionally, the multi-core digital signal processing DSP board is a multi-core digital signal processing DSP board based on a VPX 6U standard structure.
Optionally, the high-speed data link switching module includes: SRIO exchange chip board and Ethernet exchange chip board;
the SRIO switching chip board is provided with a high-speed switching network formed by 5 SRIO switching chips, wherein each SRIO switching chip supports 12 4X SRIO interfaces, the two SRIO switching chips are connected through the 4X SRIO interfaces, and 19 total 4X SRIO interfaces of the 5 SRIO switching chips are output outwards through a VPX connector;
the Ethernet switching chip board is provided with 1 Ethernet switching chip, and the Ethernet switching chip is provided with a port 1Gbe, a port 10Gbe, a gigabit Ethernet interface, an Ethernet management interface and an SERDES interface connected with the VPX.
Optionally, the high-speed data link switching module is a high-speed data switching board based on a 6U OpenVPX standard structure.
The distributed network node data sharing system provided by the embodiment of the application is composed of a plurality of signal processing modules and a high-speed data link switching module, wherein the signal processing modules are used for processing and storing currently received network node data and accessing the network node data stored in other signal processing modules through the high-speed data link switching module; the high-speed data link exchange module is used for data transmission among a plurality of signal processing modules which process the network node data in parallel. The distributed network node data sharing system can distribute a plurality of network node data to a plurality of signal processing modules for processing through the modularized arrangement, and share the data among the signal processing modules through the high-speed data link switching module, and when the signal processing modules in the distributed network node data sharing system are expanded, the data access of the signal processing modules establishing the sharing link based on the high-speed data link switching module is not influenced. The aim that the parallel processing of data is not influenced when the system is expanded is achieved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a distributed network node data sharing system according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of another distributed network node data sharing system according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of a high-speed data exchange module according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of another distributed network node data sharing system according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In this application, relational terms such as "first" and "second," and the like, may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
As can be seen from the background art, in the existing data parallel processing method based on the processing of the radar signal, since the plurality of processing nodes share the memory and the central line, the memory access bandwidth becomes a system bottleneck when the data of the system nodes is excessive, which is not beneficial to system expansion. Therefore, the embodiment of the application discloses a distributed network node data sharing system. The data are distributed to each signal processing module for processing by adopting a modularized design, and data sharing among the signal processing modules is carried out by the high-speed data link switching module. The specific implementation principle of the distributed network node data sharing system is described in detail by the following embodiments.
Fig. 1 is a schematic structural diagram of a distributed network node data sharing system disclosed in the embodiment of the present invention. The distributed network node data sharing system 100 includes: a plurality of signal processing modules 101 and a high speed data link switching module 102.
The plurality of signal processing modules 101 are arranged in a distributed manner. Each signal processing module 101 is configured to process and store currently received network node data.
The network node data sharing among the plurality of signal processing modules 101 is realized by the high-speed data link switching module 102.
The high-speed data link switching module 102 is used for data transmission among a plurality of signal processing modules 101 which process the data of the network node in parallel.
Optionally, the high-speed data link switching module 102 is further configured to transmit a system configuration file of the distributed network node data sharing system.
That is, each signal processing module 101 is configured to access network node data stored in other signal processing modules through the high-speed data link switching module 102.
In the embodiment of the invention, the distributed network node data sharing system distributes network node data to a plurality of signal processing modules for parallel processing, and realizes data sharing among the signal processing modules through a high-speed data link switching module. The method can improve the efficiency of data processing, shorten the time of data processing and meet the requirement of high real-time performance of data and signal processing. Meanwhile, when the distributed network node data sharing system is expanded, the data access of the signal processing module establishing the sharing link based on the high-speed data link exchange module is not influenced.
Optionally, the signal processing module 101 includes a plurality of signal processors, and the plurality of signal processors are connected through a Hyper Link (Hyper Link) interface. The signal processor is used for processing and storing the currently received network node data. And data exchange among the plurality of signal processors is carried out through a Hyper Link interface.
Optionally, the signal processing module 101 includes a plurality of signal processors, the signal processors are connected through a high-speed network switch 4X SRIO interface, and the signal processors are configured to process and store currently received network node data. And data exchange among the plurality of signal processors is carried out through the 4X SRIO interface.
That is, for multiple signal processors within one signal processing module. The data stored between the signal processors can be shared at high speed through a Hyper Link interface or a 4X SRIO interface. The data sharing method and the data sharing device can realize data sharing of a plurality of signal processors, save the storage capacity of the signal processors, reduce the hardware cost of the distributed network node data sharing system, and improve the data processing rate through the Hyper Link interface or the 4X SRIO interface.
In order to more clearly illustrate the specific structure and implementation process of the distributed network node data sharing system disclosed in the embodiment of the present invention, the present invention is described in detail below with specific application examples.
The distributed network node data sharing system includes a plurality of signal processing modules and a high-speed data link switching module.
Fig. 2 is a schematic structural diagram of a signal processing module according to an embodiment of the present invention.
The Signal Processing module is a multi-core Digital Signal Processing (DSP) Signal Processing board based on a VPX 6U standard structure. Optionally, the model of the multi-core DSP signal processing board is VPX 6678Q.
The multi-core DSP signal processing board comprises: 4 DSP processors, 1 field programmable gate array intermediate level integrated circuit board (FPGA Mezzanine Card, FMC) slot, 4 gigabit Ethernet ports, 1 4X PCIe interface, 6 4X SRIO interfaces, 4 serial ports and general IO interfaces. The interfaces described above all meet the VITA46 and VITA65 specifications.
The DSP processor is a DSP processor with eight embedded C66X kernels, the highest dominant frequency is 1.25GHz, the DSP is externally connected with a DDR3SDRAM, the bit width is 64bit, the clock is 666.7MHz, and the capacity is 2 GB.
Optionally, the model of the DSP processor is TMS320C 6678.
As shown in fig. 2, each DSP processor is correspondingly provided with a 4X SRIO interface, a 4X PCIe interface, a serial port, a general IO interface, a DDR3 interface, an EMIF interface, an SPI interface, a UART interface, an I2C interface, and the like. See fig. 2 for specific interfaces.
Optionally, each DSP processor is further provided with a gigabit ethernet interface.
Each DSP processor is connected with a DDR3SDRAM of the memory module through the DDR3 interface, is connected with a memory through an EMIF interface, and is connected with an expansion memory through an SPI interface.
And 4 DSP processors carry out data interaction through a high-speed data link switching module through a 4X SRIO interface.
The FMC slot is provided with an FMC interface, a DDR3 interface, a 4X SRIO interface, a 4X PCIe interface and a 4X GTX interface.
On the multi-core DSP signal processing board, 4 pieces of DSP processors are connected with the FMC slot through a PCIe exchange piece and a 4X PCIe interface on the FMC slot, and an 8X PCIe interface is expanded to be connected to a P1 connector of a bus VPX.
On the multi-core DSP signal processing board, 4 pieces of DSP processors are connected with an FMC slot through SRIO exchange pieces and 4X SRIO interfaces on the FMC slot, and 6 4X SRIO interfaces are expanded to be connected to a P1 connector and a P2 connector of VPX.
On the multi-core DSP signal processing board, the 4 DSP processors carry out program loading through FMC slots.
In a specific implementation, the model of the FPGA in the FMC slot is XC7K325T or XC7K 410T.
The FPGA of the XC7K325T or XC7K410T supports Master SPI loading or loading of an upper computer.
Optionally, each DSP processor is further provided with a Hyper Link interface, and the 4 DSP processors perform data interaction and sharing through the Hyper Link interface.
Optionally, each DSP processor may also be directly interconnected through an SRIO interface. Each DSP processor can access data which is distributed and stored in the plug-in DDR of the plurality of DSP processors through the SRIO interface.
The following examples are given. As shown in fig. 3, two DSP processors in a board are called "Neighbor", a Hyper Link interface is used to implement data sharing transmission, and the DSP processors between different boards are called "Buddy". And shared transmission of data is realized by using a 4x SRIO interface. When the distributed multi-section data sharing design is carried out, the complex dot matrix data are divided into m × n small matrixes according to the distance dimension and the direction dimension, after the system data are received, each distance line of the matrixes is evenly divided into m DDR, and each square line is evenly divided into n DDR. When either m or n is 2,
that is, if the distributed network node divides the complex point matrix data into m × n matrices according to the distance dimension and the azimuth dimension, after receiving the distributed network node data, equally allocating each distance line of the matrices to memories of m DSP processors, and equally allocating each direction line of the matrices to memories of n DSP processors, where m and n are positive integers, and a value of m or n is 2.
According to the scheme, any two DSP processors are directly interconnected through the SRIO interface, so that each DSP processor can access data which are distributed and stored in the multi-DSP plug-in DDR through the SRIO interface, the Hyperlink interface can access data between adjacent DSPs, and the system does not influence the bandwidth of data access between the DSP processors in the system along with the expansion of the number of the board cards.
It should be noted that, each DSP processor for different signal processing may perform data transmission and sharing through the 4X SRIO interface.
It should be noted that fig. 2 also discloses an SRIO Switch chip board and an Ethernet Switch chip (Ethernet Switch) board
Fig. 4 is a schematic structural diagram of a high-speed data exchange module according to an embodiment of the present invention.
The high speed data link switching module includes: SRIO Switch chip board and non-managed Ethernet Switch board. Specifically, the high-speed data link switching module is a high-speed data switching board based on a 6U OpenVPX standard structure. The SRIO Switch chip board and the unmanaged Ethernet Switch board meet the standard 6U OpenVPX.
The design standard of the high-speed data link switching Module is suitable for defining Open VPX standard Slot attribute (Slot Profile) and Module attribute (Module Profile).
The high-speed data link exchange module can adopt an air cooling or cold guiding heat dissipation mode and is applied to the temperature environment of minus 40 ℃ to plus 70 ℃.
The SRIO switching chip board is provided with a high-speed switching network formed by 5 SRIO switching chips, 19 4X SRIP interfaces connected to the backboard through a VPX connector, and 20 gigabit Ethernet interfaces (Ethernet 1G Serdes Ports) connected to the backboard through the VPX connector. The front panel of the SRIO Switch board includes 3 RJ45 interfaces connected to the Ethernet Switch board. 1 management port connected to the Ethernet Switch board. 1 RJ45 interface is connected to ZYNQ-7000 FPGA. 2 RS-232 interfaces are respectively connected with Ethernet Switch and ZYNQ-7000 FPGA.
The Ethernet Switch board is provided with 1 Ethernet Switch chip, and the Ethernet Switch chip is provided with a port 1Gbe, a port 10Gbe, a gigabit Ethernet interface, an Ethernet management interface and a SERDES interface connected with the VPX.
Each SRIO switching chip supports 12 4X SRIO interfaces, and the highest line rate is 6.25 Gbaud. Each SRIO switch chip may be directly interconnected by 2 4X SRIO. Each SRIO switching chip outputs 19 4 SRIOs to the outside through VPX connectors (P2-P6).
The Ethernet Switch chip adopts 24 1GbE ports of Microsmi (Vitesse) and 4 VSC7460 chips of 10GbE, outputs 3 gigabit Ethernet and 1 management Ethernet interface through the front panel, and outputs 20 SERDES interfaces through P1 on the VPX connector.
It should be noted that, the SRIO Switch chip board and the non-management Ethernet Switch board are managed by using the FPGA, and the SRIO Switch chip and the Ethernet Switch chip are maintained. Specifically, the FPGA is ZYNQ-7000 series FPGA, a dual-core ARM A9 processor is integrated in the chip, the highest main frequency supports 1GHz, the CPS1848 and the VSC7460 can be configured, and monitoring of board card power supply voltage, current, temperature and working state can be realized.
In summary, in the distributed network node data sharing system provided in the embodiments of the present invention, the distributed network node data sharing system can distribute a plurality of network node data to a plurality of signal processing modules for processing through the modularized arrangement, and share the data among the signal processing modules through the high-speed data link switching module, and when the signal processing modules in the distributed network node data sharing system are expanded, the data access of the signal processing modules establishing a shared link based on the high-speed data link switching module is not affected. The aim that the parallel processing of data is not influenced when the system is expanded is achieved.
The embodiments in the present specification are described in a progressive manner, and the same and similar parts among the embodiments are referred to each other, and each embodiment focuses on the differences from the other embodiments. In particular, the system or system embodiments are substantially similar to the method embodiments and therefore are described in a relatively simple manner, and reference may be made to some of the descriptions of the method embodiments for related points. The above-described system and system embodiments are only illustrative, wherein the units described as separate parts may or may not be physically separate, and the parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of the present embodiment. One of ordinary skill in the art can understand and implement it without inventive effort.
Those of skill would further appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both, and that the various illustrative components and steps have been described above generally in terms of their functionality in order to clearly illustrate this interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (9)
1. A distributed network node data sharing system, comprising: a plurality of signal processing modules and a high-speed data link switching module;
the signal processing module is used for processing and storing the currently received network node data, and accessing the network node data stored in other signal processing modules through the high-speed data link switching module;
the high-speed data link switching module is used for data transmission among a plurality of signal processing modules which process the network node data in parallel;
the signal processing module is a multi-core Digital Signal Processing (DSP) board, and the multi-core DSP board comprises 4 DSP processors, 1 Field Programmable Gate Array (FPGA) middle layer board card FMC slot, 4 gigabit Ethernet interfaces, 1 4X peripheral component interconnect express (PCIe) interface, 6 high-speed network switching (4X SRIO) interfaces, 4 serial ports and a general IO interface;
each DSP processor is connected with the memory module through a DDR3 interface, connected with the memory through an EMIF interface and connected with the expansion memory through an SPI interface;
4 pieces of DSP processors carry out data interaction through the high-speed data link exchange module through the 4X SRIO interfaces;
the FMC slot is provided with 1 FMC interface, 1 DDR3 interface, 1 4X SRIO interface, 1 4X PCIe interface and 2 4X GTX interfaces;
connecting 4 pieces of DSP processors with the FMC slot through a PCIe exchange piece and a 4X PCIe interface on the FMC slot, and expanding an 8X PCIe interface to be connected to a P1 connector of a bus VPX;
connecting 4 pieces of DSP processors with the FMC slot through SRIO switch pieces and 4X SRIO interfaces on the FMC slot, and extending 6 4X SRIO interfaces to be connected to the P1 connector and the P2 connector of the VPX;
and 4 DSP processors carry out program loading through the FMC slot.
2. The system of claim 1, wherein the signal processing module comprises a plurality of signal processors;
the signal processors are connected through hyperlink Hyper Link interfaces and used for processing and storing currently received network node data;
and data exchange access is carried out among the plurality of signal processors through the Hyper Link interface.
3. The system of claim 1, wherein the signal processing module comprises a plurality of signal processors;
the signal processors are connected through a high-speed network switching 4X SRIO interface, and are used for processing and storing currently received network node data;
and data exchange access is carried out among the plurality of signal processors through the 4X SRIO interface.
4. The system according to claim 1, wherein a Hyper Link interface is further provided on the DSP processor;
and 4 DSP processors positioned on the same signal processing module carry out data interaction through the Hyper Link interface.
5. The system of claim 1, wherein each of the DSP processors on different ones of the signal processing modules performs data transfer via the 4X SRIO interface.
6. The system of claim 1, wherein if the distributed network node divides the complex number point matrix data into m x n matrices according to distance and orientation dimensions, after receiving the distributed network node data, equally allocating each distance line of the matrix to memories of m DSP processors, equally allocating each orientation line of the matrix to memories of n DSP processors, m and n being positive integers, and m or n taking a value of 2.
7. The system of claim 1, wherein the multi-core digital signal processing DSP board is a multi-core digital signal processing DSP board based on a VPX 6U standard architecture.
8. The system according to any of claims 1-5, wherein the high speed data link switching module comprises: SRIO exchange chip board and Ethernet exchange chip board;
the SRIO switching chip board is provided with a high-speed switching network formed by 5 SRIO switching chips, wherein each SRIO switching chip supports 12 4X SRIO interfaces, the two SRIO switching chips are connected through the 4X SRIO interfaces, and 19 total 4X SRIO interfaces of the 5 SRIO switching chips are output outwards through a VPX connector;
the Ethernet switching chip board is provided with 1 Ethernet switching chip, and the Ethernet switching chip is provided with a port 1Gbe, a port 10Gbe, a gigabit Ethernet interface, an Ethernet management interface and an SERDES interface connected with the VPX.
9. The system according to any of claims 1-5, wherein the high-speed data link switching module is a 6U OpenVPX standard architecture-based high-speed data switch board.
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