CN103631527A - DSP array achieving method based on two-level exchanging architecture - Google Patents
DSP array achieving method based on two-level exchanging architecture Download PDFInfo
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Abstract
The invention relates to a DSP array achieving method based on two-level exchanging architecture. To be specific, N high-performance DSPs are connected in a tight coupling mode through two-level exchanging and interconnection to form a DSP array; interconnection of all DSPs in each bottom plate unit is achieved by first-level interconnection through a RapidIO exchanging interface, and M bottom plate units are connected by second-level interconnection through an Infiniband exchanging interface; in the first-level interconnection, blade servers serve as bottom plates of the bottom plate units, and each bottom plate carries P DSP chips; IB interfaces, connected with the outside, of the bottom plate units are built by the blade servers through an FPGA and a connector, exchanging and interconnection between each DSP chip and the FPGA are achieved through an SRIO technology, and then the FPGA is connected with the IB interfaces through the connector; in the second-level interconnection, the IB interfaces of all the bottom plate units are connected together through Infiniband exchanging chips. Due to the adoption of the method, higher digital processing ability can be achieved, and system effectiveness can be effectively improved.
Description
(1), technical field: the present invention relates to a kind of dsp processor array implementation method, particularly relate to a kind of dsp processor array implementation method based on two-stage architecture for exchanging.
(2), background technology: digital signal processing (DSP) chip is a kind of microprocessor that is particularly suitable for carrying out digital signal processing computing, and it is mainly used to realize real-time various digital signal processing algorithms.Along with the development of large scale integrated circuit technology, dsp chip has obtained the development of advancing by leaps and bounds, and the application of dsp chip is more and more extensive, and becomes gradually the determinative that electronic product updates.
RapidIO framework is a kind of high-speed serial interconnect technology based on packet switch, for the interconnection between chip and in base plate.Its design is compatible mutually with most popular network processing unit, host-processor and network digital signal processor.It has met the demand of high performance embedded system industry to inner system interconnection, comprises reliability, high bandwidth and Bus Speed faster.RapidIO framework is desirable interconnection technique in the group system that forms of reciprocity flush bonding processor and DSP, FPGA and ASIC.
InfiniBand can be used for the interconnection between base plate or between server, it adopts high speed serialization link and extendible High-speed Switching Fabrics based on packet switch to substitute shared bus structure, and high bandwidth, low delay, extendible I/O interconnection can be provided in relatively short distance.InfiniBand both can process storage I/O, network I/O, also can treatment progress between communication (IPC).It can carry out disk array, SANs, LANs, server and cluster server interconnected, also can connect external network (such as WAN, VPN, internet).
The current high-performance server overwhelming majority is the high-performance CPU processor based on X86, and along with the burst of current digital signal processing operand increases, the advantage of dsp chip is more and more significant in actual applications.Adopt extensive dsp processor array will improve operational performance and the efficiency of whole system.
(3), summary of the invention:
The technical problem to be solved in the present invention is: overcome the defect of prior art, a kind of dsp processor array implementation method based on two-stage architecture for exchanging is provided, the method can provide higher digital processing ability, has effectively improved system effectiveness.
Technical scheme of the present invention:
A kind of dsp processor array implementation method based on two-stage architecture for exchanging, be specially: adopt the mode of two-stage exchanging interconnection that N High Performance DSP processor carried out to tight coupling connection, form dsp processor array, realize many times of processing poweies of monolithic dsp processor, greatly promoted the processing power of high-speed digital signal; Wherein, the intercommunicated RapidIO Fabric Interface of crossing of one-level is realized the interconnection between each dsp processor in each bottom board unit, and the intercommunicated Infiniband Fabric Interface of crossing of secondary is realized M the connection between bottom board unit; N, M are more than or equal to 1 natural number;
In one-level interconnection, adopt blade server as the base plate of bottom board unit, each base plate carrying P sheet dsp processor chip, P is more than or equal to 1 natural number; Inner in each bottom board unit, each dsp processor chip chamber interconnects by SRIO exchange of skills, SRIO technology realizes by SRIO exchange chip, by SRIO technology, any one dsp processor chip can be accessed the resource of other dsp processor chips, has realized the device resource on network and has shared; Blade server sets up with connector the IB interface that bottom board unit is externally connected by FPGA, each dsp processor chip and FPGA interconnect by SRIO exchange of skills, FPGA connects IB interface by connector again, IB interface is bottom board unit and the outside passage that carries out data high-speed exchange, and the speed of exchanges data is 40Gb/s; Blade server sets up by Ethernet chip and converter the Ethernet interface that bottom board unit is externally connected, each dsp processor chip is connected with each minute interface of Ethernet chip respectively, total interface of Ethernet chip is connected with Ethernet interface by converter, and FPGA manages Ethernet chip by MDIO interface; Each bottom board unit provides 10/100/1000M Ethernet interface to safeguard for system management; Each dsp processor chip is also connected with storer; Each bottom board unit is equipped with Clock management module and power management module, clock frequency in Clock management module major control bottom board unit between each functional module, make the clock synchronous of each functional module, power management module provides driving power to each functional module in bottom board unit; Blade server carries out inner management by microprocessor, microprocessor is connected with dsp processor chip by HPI interface, data transmission between each dsp processor chip adopts packet system, when carrying out high-performance calculation, the intermediate result that relates to calculating, without between dsp processor chip and microprocessor, carry out data interaction between each dsp processor chip, has reduced the communication overhead of whole bottom board unit.
In secondary interconnection, Infiniband Fabric Interface adopts Infiniband exchange chip to realize, and the IB interface of each bottom board unit links together by Infiniband exchange chip.
Storer contains DDR2 internal memory, FLASH and SRAM, and in each bottom board unit, each dsp processor chip is by DDR2 Memory Controller Hub and a DDR2 Memory linkage, and each dsp processor chip is connected with a SRAM with a FLASH by EMIF mouth; By SRIO technology, the storer connecting on each dsp processor chip can be shared by other dsp processor chip.
In DDR2, save as the DDR2 internal memory of 4G, the FLASH that FLASH is 4MB, the SRAM that SRAM is 8MB.
In each bottom board unit, be also provided with JTAG debugging interface and USB interface, for assembly loading procedure, debugging, test.
Clock management module is connected with Ethernet chip with dsp processor chip, SRIO exchange chip, storer, connector; Power management module provides driving power to dsp processor chip, SRIO exchange chip, storer, connector, FPGA, converter and Ethernet chip.
Blade server is the standard A TCA blade server of 1U;
SRIO exchange chip adopts TSI 578 exchange chips of Tundra company, and TSI 578 exchange chips provide 8 4X SRIO ports and 16 1X SRIO ports, and each port can be configured to 1.25Gb/S, 2.5Gb/S or 3.125 Gb/S; TSI 578 exchange chips adopt 0.13 micrometre CMOS technology, 27mm * 27mm 675 ball FCBGA encapsulation technology packings, TSI 578 exchange chips need to be used 1.2V and 3.3V power supply, be adapted at using at industry and business environment temperature, the SerDes strengthening greatly reduces power consumption, and TSI 578 exchange chips are be applicable to ATCA blade server with MicroTCA blade server backboard or process the ideal platform being connected; The processing power of each bottom board unit is 115,200MIPS, and each chip chamber interconnection speed can reach 40Gb/s.
The TMS320TCI6474 1200 multi-core DSP processors of dsp processor chip WeiTI company, the core of built-in 3 C64x of TMS320TCI6474 1200 multi-core DSP processor, can realize performance extensibility by parallel processing, allowing a plurality of kernels on single chips, to process many threads, is one of ideal solution of numerous multinuclear devices;
Microprocessor adopts MPC 860 microprocessors of motorola inc.
FPGA is Virtex5 LX50T FPGA, and connector is Mallox ConnectX MT25408A0-FCCR-QIS bridging chip.
Ethernet chip adopts the single port 10/100/1000M phy interface chip 88E1111 of Marvell company.
P is 4.
Beneficial effect of the present invention:
1, the present invention adopts the mode of two-stage exchanging interconnection that N High Performance DSP processor carried out to tight coupling connection, form dsp processor array, wherein, the intercommunicated RapidIO Fabric Interface of crossing of one-level is realized the interconnection between each dsp processor in each bottom board unit, and the intercommunicated Infiniband Fabric Interface of crossing of secondary is realized M the connection between bottom board unit; Dsp processor is owing to having taked hard-wired multiplicaton addition unit, be particularly suitable for the calculating scene of high speed, big data quantity, in the increasing dedicated task such as Radar Signal Processing, image processing, communication base station, the data operation quantity data transfer bandwidth large and that require relating to is high, although general CPU processor also can be processed these tasks, its Energy Efficiency Ratio will be far below dsp processor; During the present invention forms dsp processor, large-scale many dsp processors array, higher digital processing ability can be provided, effectively improve system effectiveness, overcome the defect that can not meet large data processing demand completely that the combination of existing single dsp processor or a few dsp processor has.
(4), accompanying drawing explanation:
Fig. 1 is the structural representation of one-level interconnection;
Fig. 2 is the structural representation of secondary interconnection;
Fig. 3 is the DDR2 Memory linkage schematic diagram of bottom board unit;
Fig. 4 is the external interface connection diagram of bottom board unit.
(5), embodiment:
Referring to Fig. 1～Fig. 4, in figure, dsp processor array implementation method based on two-stage architecture for exchanging is specially: adopt the mode of two-stage exchanging interconnection that N High Performance DSP processor carried out to tight coupling connection, form dsp processor array, realize many times of processing poweies of monolithic dsp processor, greatly promoted the processing power of high-speed digital signal; Wherein, the intercommunicated RapidIO Fabric Interface of crossing of one-level is realized the interconnection between each dsp processor in each bottom board unit, and the intercommunicated Infiniband Fabric Interface of crossing of secondary is realized M the connection between bottom board unit; N, M are more than or equal to 1 natural number;
In one-level interconnection, adopt blade server as the base plate of bottom board unit, 4 dsp processor chips of each base plate carrying; Inner in each bottom board unit, each dsp processor chip chamber interconnects by SRIO exchange of skills, SRIO technology realizes by SRIO exchange chip, by SRIO technology, any one dsp processor chip can be accessed the resource of other dsp processor chips, has realized the device resource on network and has shared; Blade server sets up with connector the IB interface that bottom board unit is externally connected by FPGA, each dsp processor chip and FPGA interconnect by SRIO exchange of skills, FPGA connects IB interface by connector again, IB interface is bottom board unit and the outside passage that carries out data high-speed exchange, and the speed of exchanges data is 40Gb/s; Blade server sets up by Ethernet chip and converter the Ethernet interface that bottom board unit is externally connected, each dsp processor chip is connected with each minute interface of Ethernet chip respectively, total interface of Ethernet chip is connected with Ethernet interface by converter, and FPGA manages Ethernet chip by MDIO interface; Each bottom board unit provides 10/100/1000M Ethernet interface to safeguard for system management; Each dsp processor chip is also connected with storer; Each bottom board unit is equipped with Clock management module and power management module, clock frequency in Clock management module major control bottom board unit between each functional module, make the clock synchronous of each functional module, power management module provides driving power to each functional module in bottom board unit; Blade server carries out inner management by microprocessor, microprocessor is connected with dsp processor chip by HPI interface, data transmission between each dsp processor chip adopts packet system, when carrying out high-performance calculation, the intermediate result that relates to calculating, without between dsp processor chip and microprocessor, carry out data interaction between each dsp processor chip, has reduced the communication overhead of whole bottom board unit.
In secondary interconnection, Infiniband Fabric Interface adopts Infiniband exchange chip to realize, and the IB interface of each bottom board unit links together by Infiniband exchange chip.
Storer contains DDR2 internal memory, FLASH and SRAM, and in each bottom board unit, each dsp processor chip is by DDR2 Memory Controller Hub and a DDR2 Memory linkage, and each dsp processor chip is connected with a SRAM with a FLASH by EMIF mouth; By SRIO technology, the storer connecting on each dsp processor chip can be shared by other dsp processor chip.
In DDR2, save as the DDR2 internal memory of 4G, the FLASH that FLASH is 4MB, the SRAM that SRAM is 8MB.
In each bottom board unit, be also provided with JTAG debugging interface and USB interface, for assembly loading procedure, debugging, test.
Clock management module is connected with Ethernet chip with dsp processor chip, SRIO exchange chip, storer, connector; Power management module provides driving power to dsp processor chip, SRIO exchange chip, storer, connector, FPGA, converter and Ethernet chip.
Blade server is the standard A TCA blade server of 1U;
SRIO exchange chip adopts TSI 578 exchange chips of Tundra company, and TSI 578 exchange chips provide 8 4X SRIO ports and 16 1X SRIO ports, and each port can be configured to 1.25Gb/S, 2.5Gb/S or 3.125 Gb/S; TSI 578 exchange chips adopt 0.13 micrometre CMOS technology, 27mm * 27mm 675 ball FCBGA encapsulation technology packings, TSI 578 exchange chips need to be used 1.2V and 3.3V power supply, be adapted at using at industry and business environment temperature, the SerDes strengthening greatly reduces power consumption, and TSI 578 exchange chips are be applicable to ATCA blade server with MicroTCA blade server backboard or process the ideal platform being connected; The processing power of each bottom board unit is 115,200MIPS, and each chip chamber interconnection speed can reach 40Gb/s.
The TMS320TCI6474 1200 multi-core DSP processors of dsp processor chip WeiTI company, the core of built-in 3 C64x of TMS320TCI6474 1200 multi-core DSP processor, can realize performance extensibility by parallel processing, allowing a plurality of kernels on single chips, to process many threads, is one of ideal solution of numerous multinuclear devices;
Microprocessor adopts MPC 860 microprocessors of motorola inc.
FPGA is Virtex5 LX50T FPGA, and connector is Mallox ConnectX MT25408A0-FCCR-QIS bridging chip.
Ethernet chip adopts the single port 10/100/1000M phy interface chip 88E1111 of Marvell company.
Claims (9)
1. the dsp processor array implementation method based on two-stage architecture for exchanging, is characterized in that: adopt the mode of two-stage exchanging interconnection that N High Performance DSP processor carried out to tight coupling connection, form dsp processor array; Wherein, the intercommunicated RapidIO Fabric Interface of crossing of one-level is realized the interconnection between each dsp processor in each bottom board unit, and the intercommunicated Infiniband Fabric Interface of crossing of secondary is realized M the connection between bottom board unit; N, M are more than or equal to 1 natural number;
In one-level interconnection, adopt blade server as the base plate of bottom board unit, each base plate carrying P sheet dsp processor chip, P is more than or equal to 1 natural number; Inner in each bottom board unit, each dsp processor chip chamber interconnects by SRIO exchange of skills, and SRIO technology realizes by SRIO exchange chip, and by SRIO technology, any one dsp processor chip can be accessed the resource of other dsp processor chips; Blade server sets up with connector the IB interface that bottom board unit is externally connected by FPGA, each dsp processor chip and FPGA interconnect by SRIO exchange of skills, FPGA connects IB interface by connector again, and IB interface is bottom board unit and the outside passage that carries out data high-speed exchange; Blade server sets up by Ethernet chip and converter the Ethernet interface that bottom board unit is externally connected, each dsp processor chip is connected with each minute interface of Ethernet chip respectively, total interface of Ethernet chip is connected with Ethernet interface by converter, and FPGA manages Ethernet chip by MDIO interface; Each dsp processor chip is also connected with storer; Each bottom board unit is equipped with Clock management module and power management module, clock frequency in Clock management module major control bottom board unit between each functional module, make the clock synchronous of each functional module, power management module provides driving power to each functional module in bottom board unit; Blade server carries out inner management by microprocessor, and microprocessor is connected with dsp processor chip by HPI interface, and the data transmission between each dsp processor chip adopts packet system;
In secondary interconnection, Infiniband Fabric Interface adopts Infiniband exchange chip to realize, and the IB interface of each bottom board unit links together by Infiniband exchange chip.
2. the dsp processor array implementation method based on two-stage architecture for exchanging according to claim 1, it is characterized in that: described storer contains DDR2 internal memory, FLASH and SRAM, in each bottom board unit, each dsp processor chip is by DDR2 Memory Controller Hub and a DDR2 Memory linkage, and each dsp processor chip is connected with a SRAM with a FLASH by EMIF mouth; By SRIO technology, the storer connecting on each dsp processor chip can be shared by other dsp processor chip.
3. the dsp processor array implementation method based on two-stage architecture for exchanging according to claim 2, is characterized in that: in described DDR2, save as the DDR2 internal memory of 4G, the FLASH that FLASH is 4MB, the SRAM that SRAM is 8MB.
4. the dsp processor array implementation method based on two-stage architecture for exchanging according to claim 1, is characterized in that: in described each bottom board unit, be also provided with JTAG debugging interface and USB interface.
5. the dsp processor array implementation method based on two-stage architecture for exchanging according to claim 1, is characterized in that: described Clock management module is connected with Ethernet chip with dsp processor chip, SRIO exchange chip, storer, connector; Power management module provides driving power to dsp processor chip, SRIO exchange chip, storer, connector, FPGA, converter and Ethernet chip.
6. the dsp processor array implementation method based on two-stage architecture for exchanging according to claim 1, is characterized in that: the standard A TCA blade server that described blade server is 1U; Described SRIO exchange chip adopts TSI 578 exchange chips of Tundra company, the TMS320TCI6474 1200 multi-core DSP processors of described dsp processor chip WeiTI company; Described microprocessor adopts MPC 860 microprocessors of motorola inc.
7. the dsp processor array implementation method based on two-stage architecture for exchanging according to claim 1, is characterized in that: described FPGA is Virtex5 LX50T FPGA, and connector is Mallox ConnectX MT25408A0-FCCR-QIS bridging chip.
8. the dsp processor array implementation method based on two-stage architecture for exchanging according to claim 1, is characterized in that: described Ethernet chip adopts the single port 10/100/1000M phy interface chip 88E1111 of Marvell company.
9. the dsp processor array implementation method based on two-stage architecture for exchanging according to claim 1, is characterized in that: described P is 4.
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Application publication date: 20140312 |