CN108270877A - Distributed network node data-sharing systems - Google Patents
Distributed network node data-sharing systems Download PDFInfo
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- CN108270877A CN108270877A CN201810394736.XA CN201810394736A CN108270877A CN 108270877 A CN108270877 A CN 108270877A CN 201810394736 A CN201810394736 A CN 201810394736A CN 108270877 A CN108270877 A CN 108270877A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L67/00—Network arrangements or protocols for supporting network services or applications
- H04L67/01—Protocols
- H04L67/10—Protocols in which an application is distributed across nodes in the network
- H04L67/1095—Replication or mirroring of data, e.g. scheduling or transport for data synchronisation between network nodes
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L67/00—Network arrangements or protocols for supporting network services or applications
- H04L67/01—Protocols
- H04L67/10—Protocols in which an application is distributed across nodes in the network
Abstract
The application provides a kind of distributed network node data-sharing systems, the system is made of multiple signal processing modules and high speed data link Switching Module, the signal processing module, for being handled the network node data being currently received and being stored and access the network node data stored in other signal processing modules by the high speed data link Switching Module.Multiple network node datas can be distributed on multiple signal processing modules and handled by modular setting distributed network node data-sharing systems, and pass through the data sharing between high speed data link Switching Module progress signal processing module, and in the signal processing module in extending the distributed network node data-sharing systems, the data access of the signal processing module of shared link is established based on high speed data link Switching Module to be affected.Realize that extending in system is the purpose for not influencing parallel data processing.
Description
Technical field
The present invention relates to technical field of data processing, and in particular to a kind of distributed network node data-sharing systems.
Background technology
Radar is the electronic equipment using electromagnetic wave detection target.Radar emission electromagnetic wave is irradiated and receives to target
Its echo, the information such as distance, range rate (radial velocity), orientation, height thus to obtain target to electromagnetic emission point.
Processing for radar live signal uses parallel processing algorithm more.At present, there are mainly two types of processing methods, a kind of
For the method for parallel processing based on assembly line, another kind is the processing method based on data parallel.
Its core concept of method for parallel processing based on assembly line is：Processing Algorithm is divided into according to data flow direction multiple
Each subtask is mapped to corresponding processing node, data flow serial one-way flow in multiple subtasks by subtask.The party
Method needs individual hardware matrix transposition processing board, and requires system high with the hardware degree of coupling, and due to multiple processing node journeys
Sequence is different, causes Universal and scalability poor.
Processing method based on data parallel mainly includes the parallel processing of shared storage.Using the parallel place of shared storage
During reason, since the communication of node is using shared memory, multiple nodes sharing buses are interior when system node data are more
Access bandwidth is deposited as system bottleneck, is unfavorable for system extension.
It can be seen from the above, there are problems that being unfavorable for system extension in the prior art for parallel data processing method.
Invention content
In view of this, the embodiment of the present invention provides a kind of distributed network node data-sharing systems, to solve existing needle
There are problems that being unfavorable for system extension to the method for parallel processing of radar live signal.
To achieve the above object, the embodiment of the present invention provides following technical solution：
A kind of distributed network node data-sharing systems, including：Multiple signal processing modules and high speed data link are handed over
Change the mold block；
The signal processing module for handling the network node data being currently received, and stores, Yi Jitong
It crosses the high speed data link Switching Module and accesses the network node data stored in other described signal processing modules；
The high speed data link Switching Module, at the signal for network node data described in multiple parallel processings
Manage the data transmission between module.
Optionally, the signal processing module includes multiple signal processors；
Multiple signal processors are connected by hyperlink Hyper Link interfaces, and the signal processor is used for working as
Before the network node data that receives handled, and store；
Data exchanging visit is carried out by the Hyper Link interfaces between multiple signal processors.
Optionally, the signal processing module includes multiple signal processors；
Multiple signal processors exchange 4X SRIO interfaces by express network and connect, and the signal processor is used for
The network node data being currently received is handled, and is stored；
Data exchanging visit is carried out by the 4X SRIO interfaces between multiple signal processors.
Optionally, the signal processing module is multinuclear Digital Signal Processing dsp board, and the multi-core DSP plate includes 4
Dsp processor, 1 field programmable gate array middle layer board FMC slots, 4 gigabit ethernet interfaces, 1 4X PCIe connect
Mouth, 6 express networks exchange 4X SRIO interfaces, 4 serial ports and general I/O interface；
The every dsp processor is connected by DDR3 interfaces with memory modules, is connected by EMIF interfaces with memory,
It is connected by SPI interface with extended menory；
Between 4 dsp processors by the 4X SRIO interfaces via the high speed data link Switching Module into
Row data interaction；
1 FMC interface, 1 DDR3 interface, 1 4X SRIO interface, 1 4X PCIe is provided on the FMC slots to connect
Mouth and 2 4X GTX interfaces；
By the 4X PCIe interfaces on PCIe changing plates and the FMC slots, by 4 dsp processors with it is described
FMC slots connect, and extend the P1 connectors that a 8X PCIe interface is connected to bus VPX；
By the 4X SRIO interfaces on SRIO changing plates and the FMC slots, by 4 dsp processors with it is described
FMC slots connect, and extend 6 4X SRIO interfaces and be connected to the P1 connectors of the VPX and P2 connectors；
4 dsp processors are loaded by the FMC slots into line program.
Optionally, hyperlink Hyper Link interfaces are additionally provided on the dsp processor；
It is connect between 4 dsp processors on the same signal processing module by the Hyper Link
Mouth carries out data interaction.
Optionally, the every dsp processor on the different signal processing modules is connect by the first 4X SRIO
Mouth carries out data transmission.
Optionally, if complex points matrix data is divided into m × n by distributed network node according to apart from peacekeeping azimuth dimension
Every range line of the matrix then after the distributed network node data are received, is evenly distributed to m institute by matrix
In the memory for stating dsp processor, every rhumb line of the matrix is evenly distributed in the n dsp processors
In depositing, m and n are positive integer, and the value of m or n is 2.
Optionally, the multinuclear Digital Signal Processing dsp board is at the multinuclear digital signal based on VPX 6U normal structures
Manage dsp board.
Optionally, the high speed data link Switching Module includes：SRIO exchange chips plate and Ethernet switching chip plate；
The High-speed Switching Fabrics that 5 SRIO exchange chips are formed are provided on the SRIO exchange chips plate,
Wherein, the every SRIO exchange chips support 12 4X SRIO interfaces, by described between SRIO exchange chips described in two panels
4X SRIO interfaces connect, 5 SRIO exchange chips to share 19 4X SRIO interfaces externally defeated by VPX connectors
Go out；
1 Ethernet switching chip is provided on the Ethernet switching chip plate, the Ethernet switching chip has
The SERDES interfaces that 1Gbe ports, 10Gbe ports, gigabit ethernet interface, ethernet management interface and the VPX are connected.
Optionally, the high speed data link Switching Module is exchanged for the high-speed data based on 6U OpenVPX normal structures
Plate.
Based on a kind of above-mentioned distributed network node data-sharing systems provided by the embodiments of the present application, the system is by multiple
Signal processing module and high speed data link Switching Module are formed, the signal processing module, for the network being currently received
Node data is handled, and is stored and accessed other signal processing moulds by the high speed data link Switching Module
The network node data stored in block；The high speed data link Switching Module, for number of network node described in multiple parallel processings
According to the signal processing module between data transmission.It is total to by modular setting distributed network node data
Multiple network node datas can be distributed on multiple signal processing modules and handle, and pass through high-speed data chain by the system of enjoying
Road Switching Module carries out the data sharing between signal processing module, and is extending the distributed network node data-sharing systems
In signal processing module when, the data that the signal processing module of shared link is established based on high speed data link Switching Module are visited
Asking will not be affected.Realize that extending in system is the purpose for not influencing parallel data processing.
Description of the drawings
In order to illustrate more clearly about the embodiment of the present invention or technical scheme of the prior art, to embodiment or will show below
There is attached drawing needed in technology description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
The embodiment of invention, for those of ordinary skill in the art, without creative efforts, can also basis
The attached drawing of offer obtains other attached drawings.
Fig. 1 is a kind of structure diagram of distributed network node data-sharing systems provided in an embodiment of the present invention；
Fig. 2 is the structure diagram of another distributed network node data-sharing systems provided in an embodiment of the present invention；
Fig. 3 is a kind of structure diagram of high-speed data Switching Module provided in an embodiment of the present invention；
Fig. 4 is the structure diagram of another distributed network node data-sharing systems provided in an embodiment of the present invention.
Specific embodiment
Below in conjunction with the attached drawing in the embodiment of the present invention, the technical solution in the embodiment of the present invention is carried out clear, complete
Site preparation describes, it is clear that described embodiment is only part of the embodiment of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, those of ordinary skill in the art are obtained every other without making creative work
Embodiment shall fall within the protection scope of the present invention.
In this application, the relational terms of such as " first " and " second " or the like are used merely to an entity or behaviour
Make with another entity or operate distinguish, without necessarily requiring or implying between these entities or operation there are it is any this
Kind practical relationship or sequence.Moreover, term " comprising ", "comprising" or its any other variant are intended to nonexcludability
Include so that process, method, article or equipment including a series of elements not only include those elements, but also
Including other elements that are not explicitly listed or further include for this process, method, article or equipment it is intrinsic will
Element.In the absence of more restrictions, the element limited by sentence "including a ...", it is not excluded that wanted including described
Also there are other identical elements in the process of element, method, article or equipment.
By background technology it is found that the existing data parallel processing method being based on when handling thunder method signal, due to multiple
Nodes sharing memory and center line are handled, internal storage access broadband becomes system bottleneck when system node overabundance of data, is unfavorable for
System extends.Therefore, the embodiment of the present application discloses a kind of distributed network node data-sharing systems.It is set using modular
Meter, will be handled in data distribution to each signal processing module, and is passed through high speed data link Switching Module and carried out signal
Data sharing between processing module during the extending in system signal processing module, is built based on high speed data link Switching Module
The data access of the signal processing module of vertical shared link will not be affected.The distributed network node data-sharing systems
Specific implementation principle be described in detail by following embodiment.
As shown in Figure 1, show for a kind of structure of distributed network node data-sharing systems disclosed by the embodiments of the present invention
It is intended to.The distributed network node data-sharing systems 100 include：Multiple signal processing modules 101 and high speed data link are handed over
Change the mold block 102.
Multiple distributed settings of signal processing module 101.Each signal processing module 101, for being currently received
Network node data is handled, and is stored.
Network node data between multiple signal processing modules 101 is shared, and passes through high speed data link Switching Module 102
It realizes.
The high speed data link Switching Module 102, for the signal processing mould of multiple parallel processing network node datas
Data transmission between block 101.
Optionally, high speed data link Switching Module 102 is additionally operable to transmit the distributed network node data-sharing systems
System configuration file.
That is, each signal processing module 101, other are accessed for passing through high speed data link Switching Module 102
The network node data stored in signal processing module.
In embodiments of the present invention, network node data is distributed to multiple letters by distributed network node data-sharing systems
Parallel processing is carried out in number processing module, and passes through high speed data link Switching Module and realizes between each signal processing module
Data sharing.The efficiency of data processing can not only be improved, shorten the time of data processing, meet data, signal processing height
Requirement of real-time.Meanwhile when the distributed network node data-sharing systems carry out system extension, based on high speed data link
The data access that Switching Module establishes the signal processing module of shared link will not be affected.
Optionally, which includes multiple signal processors, and multiple signal processors pass through hyperlink
(Hyper Link) interface is connected.The signal processor is used to handle the network node data being currently received, and deposit
Storage.Data exchanging visit is carried out by Hyper Link interfaces between multiple signal processors.
Optionally, which includes multiple signal processors, and multiple signal processors pass through express network
The connection of 4X SRIO interfaces is exchanged, the signal processor is used to handle the network node data being currently received, and deposit
Storage.Data exchanging visit is carried out by the 4X SRIO interfaces between multiple signal processors.
That is, for multiple signal processors in a signal processing module.It is stored between signal processor
Data can be realized by Hyper Link interfaces or 4X SRIO interfaces it is shared at a high speed.It can not only realize multiple signals
The memory capacity of signal processor is saved in the data sharing of processor, reduces the hard of distributed network node data-sharing systems
Part cost can also improve data processing rate by Hyper Link interfaces or 4X SRIO interfaces.
Concrete structure for clearer explanation distributed network node data-sharing systems disclosed by the embodiments of the present invention
And implementation procedure, present invention below are described in detail with concrete application example.
The distributed network node data-sharing systems include multiple signal processing modules and high speed data link interchange mode
Block.
As shown in Fig. 2, for a kind of structure diagram of signal processing module disclosed by the embodiments of the present invention.
The signal processing module is multinuclear Digital Signal Processing (the Digital Signal based on VPX 6U normal structures
Processing, DSP) signal-processing board.Optionally, the model VPX6678Q of the multi-core DSP signal-processing board.
The multi-core DSP signal-processing board includes：4 dsp processors, 1 field programmable gate array middle layer board
(FPGA Mezzanine Card, FMC) slot, 4 gigabit Ethernet mouths, 1 4X PCIe interface, 6 4X SRIO interfaces, 4
A serial ports and general I/O interface.Above-mentioned interface is satisfied by VITA46 and VITA65 specifications.
The dsp processor is the dsp processor for embedding eight C66X kernels, and highest dominant frequency is 1.25GHz, and the DSP is external
Memory modules DDR3SDRAM, bit wide 64bit, clock 666.7MHz, capacity 2GB.
Optionally, the model TMS320C6678 of the dsp processor.
As shown in Fig. 2, 4X SRIO interfaces, 4X PCIe interfaces, serial ports, general are correspondingly arranged on each dsp processor
I/O interface, DDR3 interfaces, EMIF interfaces, SPI interface, UART interface and I2C interface etc..Physical interface is seen referring in attached drawing 2
Specific label.
Optionally, also it is correspondingly arranged on gigabit ethernet interface on each dsp processor.
Every dsp processor is connected by the DDR3 interfaces with memory modules DDR3SDRAM, by EMIF interfaces with depositing
Reservoir is connected, and is connected by SPI interface with extended menory.
Data interaction is carried out via high speed data link Switching Module by 4X SRIO interfaces between 4 dsp processors.
FMC interfaces, DDR3 interfaces, 4X SRIO interfaces, 4X PCIe interfaces and 4X GTX is provided on the FMC slots to connect
Mouthful.
On the multi-core DSP signal-processing board, by the 4X PCIe interfaces on PCIe changing plates and FMC slots, by 4
Dsp processor is connect with the FMC slots, and extends the P1 connectors that a 8X PCIe interface is connected to bus VPX.
On the multi-core DSP signal-processing board, by the 4X SRIO interfaces on SRIO changing plates and FMC slots, by 4
Dsp processor is connect with FMC slots, and is extended 6 4X SRIO interfaces and be connected to the P1 connectors of VPX and P2 connectors.
On the multi-core DSP signal-processing board, which is loaded by FMC slots into line program.
In the concrete realization, the model XC7K325T or XC7K410T of the FPGA in the FMC slots.
The FPGA of the XC7K325T or XC7K410T supports Master SPI loadings or the loading of host computer.
Optionally, hyperlink Hyper Link interfaces are additionally provided on every dsp processor, are led between 4 dsp processors
The Hyper Link interfaces are crossed to carry out data interaction and share.
Optionally, every dsp processor can also directly pass through SRIO interface inter-links.Every dsp processor can pass through
The SRIO interfaces access the data that distribution is stored in the plug-in DDR of multi-DSP processor.
Citing illustrates below.As shown in figure 3, the two panels dsp processor in veneer is referred to as " Neighbor ", use
Hyper Link interfaces realize that data sharing is transmitted, and the dsp processor between different boards is referred to as " Buddy ".Use 4x SRIO
Interface realizes the shared transmission of data.When distributed more piece data sharing designs, complex points matrix data is tieed up according to distance
It is divided into m*n minor matrix with azimuth dimension, system data is assigned to every range line of matrix in m DDR after receiving, every side
Bit line is uniformly assigned in n DDR.When as m or n, any one is 2,
That is, if complex points matrix data is divided into m × n by distributed network node according to apart from peacekeeping azimuth dimension
Every range line of the matrix then after the distributed network node data are received, is evenly distributed to m by a matrix
In the memory of the dsp processor, every rhumb line of the matrix is evenly distributed to a dsp processors of n
In memory, m and n are positive integer, and the value of m or n is 2.
Said program, arbitrary two panels dsp processor is directly by SRIO interface inter-links, so every dsp processor can be with
The data for being distributed and being stored in the plug-in DDR of multi-DSP are accessed by SRIO interfaces, Hyperlink interfaces can access adjacent DSP
Between data, and the system with board quantity extension without data access between dsp processor in influence system bandwidth.
It should be noted that it can be carried out for every dsp processor in unlike signal processing by 4X SRIO interfaces
Data transmission and shared.
It should be noted that SRIO exchange chips plate and Ethernet switching chip (Ethernet are also disclosed that in Fig. 2
Switch) plate
As shown in figure 4, for a kind of structure diagram of high-speed data Switching Module provided in an embodiment of the present invention.
The high speed data link Switching Module includes：The Ethernet Switch of SRIO exchange chips plate and non-management type
Plate.Specifically, the high speed data link Switching Module is the high-speed data power board based on 6U OpenVPX normal structures.It should
The Ethernet Switch plates of SRIO exchange chips plate and non-management type meet standard 6U OpenVPX.
The design standard of the high speed data link Switching Module is applicable in Open VPX specification slots attributes (Slot Profile)
And module attribute (Module Profile) definition.
Air-cooled or conduction cooling radiating mode can be used in the high speed data link Switching Module, is taken the photograph applied to -40 degrees Celsius~+70
In the temperature environment of family name's degree.
The High-speed Switching Fabrics that 5 SRIO exchange chips are formed are provided on the SRIO exchange chip plates, 19 logical
The 4X SRIP interfaces that VPX connectors are connected to backboard are crossed, 20 gigabit Ethernets that backboard is connected to by VPX connectors connect
Mouth (Ethernet 1G Serdes Ports).It is then connected on the front panel of the SRIO power boards comprising 3 RJ45 interfaces
Ethernet Switch plates.1 management mouth for being connected to Ethernet Switch plates.1 RJ45 interface is connected to ZYNQ-
7000FPGA.2 RS-232 interfaces connect Ethernet Switch and ZYNQ-7000FPGA respectively.
1 Ethernet Switch chip, the Ethernet switching chip are provided on the Ethernet Switch plates
It is connect with 1Gbe ports, 10Gbe ports, gigabit ethernet interface, ethernet management interface with the VPX SERDES being connected
Mouthful.
Wherein, the every SRIO exchange chip supports 12 4X SRIO interfaces, and highest line rate is 6.25Gbaud.Often
Piece SRIO exchange chips can be interconnected directly by 2 4X SRIO.Each SRIO exchange chips by VPX connectors (P2~
P6 19 4X SRIO) are externally exported.
Ethernet Switch chips use 24 1GbE ports of Microsemi (Vitesse), 4 10GbE chips
VSC7460 exports 3 gigabit Ethernets and 1 management ethernet interface by front panel, defeated by the P1 on VPX connectors
Go out 20 road SERDES interfaces.
It should be noted that the Ethernet of above-mentioned SRIO exchange chips plate and non-management type is managed using FPGA
Switch plates and safeguard SRIO exchange chips and Ethernet Switch chips.Specifically, the FPGA is ZYNQ-7000
Series FPGA, the chip interior are integrated with double-core ARM A9 processors, and highest dominant frequency supports 1GHz, can realize to CPS1848,
VSC7460 is configured, and can also realize the monitoring of board supply voltage, electric current, temperature and working condition.
In conclusion a kind of distributed network node data-sharing systems provided in an embodiment of the present invention, pass through modularization
Setting multiple network node datas are distributed at multiple signals by the distributed network node data-sharing systems
It is handled in reason module, and passes through the data sharing between high speed data link Switching Module progress signal processing module, and
In the signal processing module in extending the distributed network node data-sharing systems, based on high speed data link Switching Module
Establishing the data access of the signal processing module of shared link will not be affected.Realize that extending in system is not influence data
The purpose of parallel processing.
Each embodiment in this specification is described by the way of progressive, identical similar portion between each embodiment
Point just to refer each other, and the highlights of each of the examples are difference from other examples.Especially for system or
For system embodiment, since it is substantially similar to embodiment of the method, so describing fairly simple, related part is referring to method
The part explanation of embodiment.System and system embodiment described above is only schematical, wherein the conduct
The unit that separating component illustrates may or may not be it is physically separate, the component shown as unit can be or
Person may not be physical unit, you can be located at a place or can also be distributed in multiple network element.It can root
Factually border needs to select some or all of module therein realize the purpose of this embodiment scheme.Ordinary skill
Personnel are without creative efforts, you can to understand and implement.
Professional further appreciates that, with reference to each exemplary unit of the embodiments described herein description
And algorithm steps, can be realized with the combination of electronic hardware, computer software or the two, in order to clearly demonstrate hardware and
The interchangeability of software generally describes each exemplary composition and step according to function in the above description.These
Function is performed actually with hardware or software mode, specific application and design constraint depending on technical solution.Profession
Technical staff can realize described function to each specific application using distinct methods, but this realization should not
Think beyond the scope of this invention.
The foregoing description of the disclosed embodiments enables professional and technical personnel in the field to realize or use the present invention.
A variety of modifications of these embodiments will be apparent for those skilled in the art, it is as defined herein
General Principle can be realized in other embodiments without departing from the spirit or scope of the present invention.Therefore, it is of the invention
The embodiments shown herein is not intended to be limited to, and is to fit to and the principles and novel features disclosed herein phase one
The most wide range caused.
Claims (10)
1. a kind of distributed network node data-sharing systems, which is characterized in that including：Multiple signal processing modules and high speed number
According to link switching module；
The signal processing module for handling the network node data being currently received, and stores and passes through institute
It states high speed data link Switching Module and accesses the network node data stored in other described signal processing modules；
The high speed data link Switching Module, for the signal processing mould of network node data described in multiple parallel processings
Data transmission between block.
2. system according to claim 1, which is characterized in that the signal processing module includes multiple signal processors；
Multiple signal processors are connected by hyperlink Hyper Link interfaces, and the signal processor is used for currently connecing
The network node data received is handled, and is stored；
Data exchanging visit is carried out by the Hyper Link interfaces between multiple signal processors.
3. system according to claim 1, which is characterized in that the signal processing module includes multiple signal processors；
Multiple signal processors exchange 4X SRIO interfaces by express network and connect, and the signal processor is used for working as
Before the network node data that receives handled, and store；
Data exchanging visit is carried out by the 4X SRIO interfaces between multiple signal processors.
4. system according to claim 1, which is characterized in that the signal processing module is multinuclear Digital Signal Processing
Dsp board, the multi-core DSP plate include 4 dsp processors, 1 field programmable gate array middle layer board FMC slot, 4
Gigabit ethernet interface, 1 4X PCIe interface, 6 express networks exchange 4X SRIO interfaces, 4 serial ports and general I/O interface；
The every dsp processor is connected by DDR3 interfaces with memory modules, is connected by EMIF interfaces with memory, passed through
SPI interface is connected with extended menory；
Between 4 dsp processors by the 4X SRIO interfaces via the high speed data link Switching Module into line number
According to interaction；
Be provided on the FMC slots 1 FMC interface, 1 DDR3 interface, 1 4X SRIO interface, 1 4X PCIe interface and
2 4X GTX interfaces；
By the 4X PCIe interfaces on PCIe changing plates and the FMC slots, 4 dsp processors are inserted with the FMC
Slot connects, and extends the P1 connectors that a 8X PCIe interface is connected to bus VPX；
By the 4X SRIO interfaces on SRIO changing plates and the FMC slots, 4 dsp processors are inserted with the FMC
Slot connects, and extends 6 4X SRIO interfaces and be connected to the P1 connectors of the VPX and P2 connectors；
4 dsp processors are loaded by the FMC slots into line program.
5. system according to claim 4, which is characterized in that hyperlink Hyper is additionally provided on the dsp processor
Link interfaces；
Between 4 dsp processors on the same signal processing module by the Hyper Link interfaces into
Row data interaction.
6. system according to claim 4, which is characterized in that the every DSP on the different signal processing modules
Processor is carried out data transmission by the first 4X SRIO interfaces.
7. system according to claim 4, which is characterized in that if distributed network node by complex points matrix data according to
M × n matrix is divided into apart from peacekeeping azimuth dimension, then after the distributed network node data are received, by the matrix
Every range line be evenly distributed in the memory of m dsp processors, by every rhumb line mean allocation of the matrix
Into the memory of the n dsp processors, m and n are positive integer, and the value of m or n is 2.
8. system according to claim 4, which is characterized in that the multinuclear Digital Signal Processing dsp board is based on VPX
The multinuclear Digital Signal Processing dsp board of 6U normal structures.
9. according to the system described in any one of claim 1-6, which is characterized in that the high speed data link Switching Module packet
It includes：SRIO exchange chips plate and Ethernet switching chip plate；
The High-speed Switching Fabrics that 5 SRIO exchange chips are formed are provided on the SRIO exchange chips plate, wherein,
The every SRIO exchange chip supports 12 4X SRIO interfaces, passes through the 4X between SRIO exchange chips described in two panels
SRIO interfaces connect, and the 19 4X SRIO interfaces that share of 5 SRIO exchange chips are externally exported by VPX connectors；
1 Ethernet switching chip is provided on the Ethernet switching chip plate, the Ethernet switching chip has 1Gbe
The SERDES interfaces that port, 10Gbe ports, gigabit ethernet interface, ethernet management interface and the VPX are connected.
10. according to the system described in any one of claim 1-6, which is characterized in that the high speed data link Switching Module
For the high-speed data power board based on 6U OpenVPX normal structures.
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| CN109254728A (en) * | 2018-08-21 | 2019-01-22 | 广东九联科技股份有限公司 | Storage optimization method and system for multi-master chip fusion product |
| CN109672634A (en) * | 2018-12-03 | 2019-04-23 | 天津津航计算技术研究所 | The clog-free SRIO network topology structure in 18 tunnels and method based on exchange chip |
| CN112800001A (en) * | 2021-04-13 | 2021-05-14 | 北京乐研科技有限公司 | High-performance Internet of things hardware platform and method based on ARM platform architecture |
| CN114885196A (en) * | 2022-05-07 | 2022-08-09 | 苏州朗捷通智能科技有限公司 | Booth is apart from LED display screen distributed control system |
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