CN109672634A - The clog-free SRIO network topology structure in 18 tunnels and method based on exchange chip - Google Patents
The clog-free SRIO network topology structure in 18 tunnels and method based on exchange chip Download PDFInfo
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- CN109672634A CN109672634A CN201811465709.3A CN201811465709A CN109672634A CN 109672634 A CN109672634 A CN 109672634A CN 201811465709 A CN201811465709 A CN 201811465709A CN 109672634 A CN109672634 A CN 109672634A
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- cps1848
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- srio
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/15—Interconnection of switching modules
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/02—Details
- H04L12/12—Arrangements for remote connection or disconnection of substations or of equipment thereof
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/50—Reducing energy consumption in communication networks in wire-line communication networks, e.g. low power modes or reduced link rate
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Abstract
The clog-free SRIO network topology structure in 18 tunnels that the present invention relates to a kind of based on exchange chip and method, belong to technical field of data storage.The present invention realizes the clog-free SRIO network topology structure in 18 tunnels using the SRIO exchange chip of minimum the piece number, any two circuit node in 18 tunnels can realize that the high-speed data of SRIO 4x is exchanged by secondary topological structure, system power dissipation is reduced, the wiring difficulty of high-speed differential signal is reduced.
Description
Technical field
The invention belongs to technical field of data storage, and in particular to a kind of clog-free SRIO net in 18 tunnels based on exchange chip
Network topological structure and method.
Background technique
The CPS1848 exchange chip of current Integrated Device Technology, Inc. at most realizes the exchanging interconnection of 12 road 4x modes now, realizes complete double
The clog-free exchange network of work.But in order to meet the clog-free SRIO switching network of the full duplex of 18 road high-speed data switching requirements
Network, monolithic CPS1848 exchange chip have been unable to satisfy requirement.
Summary of the invention
(1) technical problems to be solved
The technical problem to be solved by the present invention is how to design using minimum the piece number SRIO exchange chip realize 18 tunnels without
Block SRIO network topology structure.
(2) technical solution
The clog-free SRIO network in 18 tunnels that in order to solve the above-mentioned technical problems, the present invention provides a kind of based on exchange chip
Topological structure, by 3 CPS1848 exchange chips, that is, CPS1848 chip A, CPS1848 chip B and CPS1848 chip C cascade
At every CPS1848 exchange chip itself is used to provide the exchange of 12 road SRIO 4x high-speed datas, and CPS1848 chip A has 3 tunnels
The 3 road SRIO 4x of SRIO 4x and CPS1848 chip B are interconnected one to one, 3 tunnels of another 3 road SRIO 4x and CPS1848 chip C
SRIO 4x is interconnected one to one, the another 3 road SRIO 4x mono- of the another 3 road SRIO 4x and CPS1848 chip C of CPS1848 chip B
It is interconnected to one, respectively remaining 6 road SRIO 4x is mentioned CPS1848 chip A, CPS1848 chip B and CPS1848 chip C jointly
For the clog-free full duplex switching node in 18 tunnels.
The present invention also provides the working method of the clog-free SRIO network topology structure in 18 tunnels described in one kind, definition
Access between CPS1848 chip A and CPS1848 chip B be access 1., between CPS1848 chip A and CPS1848 chip C
Access be access 2., access between CPS1848 chip B and CPS1848 chip C be access 3., CPS1848 chip A and 18 tunnels
Access between clog-free full duplex switching node be access 4., the clog-free full duplex switching node of CPS1848 chip B and 18 tunnels
Between access be access 5., access between the clog-free full duplex switching node of CPS1848 chip C and 18 tunnels be access 6.,
Then the course of work of the clog-free SRIO network topology structure in 18 tunnel includes:
If the exchange between 18 road SRIO network nodes do not need in CPS1848 chip A, CPS1848 chip B and
Data exchange is carried out between CPS1848 chip C, then 4. corresponding 6 road SRIO network node passes through in CPS1848 chip A access
Exchange is completed in inside, and 5. corresponding 6 road SRIO network node completes exchange to access inside CPS1848 chip B, 6. access corresponds to
6 road SRIO network nodes completed inside CPS1848 chip C exchange.
Preferably, the course of work of the clog-free SRIO network topology structure in 18 tunnel further include: if SRIO network section
Point needs to carry out 12 circuit-switched datas between CPS1848 chip A and CPS1848 chip B to exchange, then access 4. corresponding 6 road SRIO net
Network node data is transmitted to CPS1848 chip A, then 1. and (access 2., access 3.) is transmitted to CPS1848 chip B by access,
Finally it is transmitted to access 5. corresponding 6 road SRIO node.Remaining 6 road SRIO network node is by access 6. in CPS1848 chip C
Complete exchange in inside.
Preferably, SRIO network node carries out what 12 circuit-switched datas exchanged between CPS1848 chip A and CPS1848 chip C
Process carries out the process class that 12 circuit-switched datas exchange with SRIO network node between CPS1848 chip A and CPS1848 chip B
Seemingly.
Preferably, 12 circuit-switched datas are carried out between CPS1848 chip B and CPS1848 chip C exchange process and SRIO network
The process that node carries out 12 circuit-switched data exchanges between CPS1848 chip A and CPS1848 chip B is similar.
Preferably, if SRIO network node is between CPS1848 chip A, CPS1848 chip B and CPS1848 chip C
Carrying out data exchange, then 4. 1. corresponding 3 road SRIO network node data is transmitted to CPS1848 chip B by access to access, then
It is transmitted to access 5. corresponding 3 road SRIO node；4. 2. remaining corresponding 3 road SRIO network node data are passed access by access
CPS1848 chip C is transported to, then is transmitted to access 6. corresponding 3 road SRIO node；Access 5. remaining corresponding 3 road SRIO network
3. node data is transmitted to CPS1848 chip C by access, then be transmitted to access 6. remaining corresponding 3 road SRIO node.
(3) beneficial effect
The present invention realizes the clog-free SRIO network topology structure in 18 tunnels using the SRIO exchange chip of minimum the piece number, and 18 tunnels are appointed
Two circuit nodes of anticipating can realize that the high-speed data of SRIO 4x exchanges, and reduces system power dissipation, reduces high speed by secondary topological structure
The wiring difficulty of differential signal.
Detailed description of the invention
Fig. 1 is the clog-free SRIO network topology structure figure in a kind of 18 tunnel provided by the invention.
Specific embodiment
To keep the purpose of the present invention, content and advantage clearer, with reference to the accompanying drawings and examples, to of the invention
Specific embodiment is described in further detail.
The clog-free SRIO network topology structure in 18 tunnels based on exchange chip that the present invention designs is exchanged by 3 CPS1848
Chip cascade is constituted, as shown in Figure 1.Every CPS1848 exchange chip itself is used to provide the friendship of 12 road SRIO 4x high-speed datas
It changes.CPS1848 chip B and CPS1848 chip C respectively has 3 road SRIO 4x and other two panels exchange chips to interconnect, i.e. CPS1848 core
Piece A has the 3 road SRIO 4x of 3 road SRIO 4x and CPS1848 chip B to interconnect one to one, another 3 road SRIO 4x and CPS1848 core
The 3 road SRIO 4x of piece C are interconnected one to one, another 3 tunnel of the another 3 road SRIO 4x and CPS1848 chip C of CPS1848 chip B
SRIO 4x is interconnected one to one, the respective remaining 6 road SRIO of CPS1848 chip A, CPS1848 chip B and CPS1848 chip C
4x provides 18 tunnels clog-free full duplex switching node jointly.
Define CPS1848 chip A and CPS1848 chip B between access be access 1., CPS1848 chip A with
Access between CPS1848 chip C be access 2., the access between CPS1848 chip B and CPS1848 chip C be access 3.,
Access between the clog-free full duplex switching node of CPS1848 chip A and 18 tunnels be access 4., CPS1848 chip B and 18 tunnels without
Block full duplex switching node between access be access 5., the clog-free full duplex switching node of CPS1848 chip C and 18 tunnels it
Between access be access 6..Then present invention work implementation process is as follows:
(1) if the exchange between 18 road SRIO network nodes do not need in CPS1848 chip A, CPS1848 chip B and
Data exchange is carried out between CPS1848 chip C, then 4. corresponding 6 road SRIO network node passes through in CPS1848 chip A access
Exchange is completed in inside, and 5. corresponding 6 road SRIO network node completes exchange to access inside CPS1848 chip B, 6. access corresponds to
6 road SRIO network nodes completed inside CPS1848 chip C exchange.
(2) if SRIO network node needs to carry out 12 circuit-switched data friendships between CPS1848 chip A and CPS1848 chip B
Change, then 4. corresponding 6 road SRIO network node data is transmitted to CPS1848 chip A to access, then by access 1. and (access 2.,
Access is 3.) it is transmitted to CPS1848 chip B, finally it is transmitted to access 5. corresponding 6 road SRIO node.Remaining 6 road SRIO network section
6. point completes exchange by access inside CPS1848 chip C.
(3) if SRIO network node carried out between CPS1848 chip A and CPS1848 chip C 12 circuit-switched datas exchange or
Person carries out 12 circuit-switched datas between CPS1848 chip B and CPS1848 chip C and exchanges process and step (2) similarly.
(4) if SRIO network node carries out between CPS1848 chip A, CPS1848 chip B and CPS1848 chip C
Data exchange, then 4. 1. corresponding 3 road SRIO network node data is transmitted to CPS1848 chip B by access to access, then transmits
To access 5. corresponding 3 road SRIO node；4. 2. remaining corresponding 3 road SRIO network node data are transmitted to access by access
CPS1848 chip C, then it is transmitted to access 6. corresponding 3 road SRIO node；Access 5. remaining corresponding 3 road SRIO network node
3. data are transmitted to CPS1848 chip C by access, then be transmitted to access 6. remaining corresponding 3 road SRIO node.
Remarkable advantage of the present invention are as follows: by design, opened up using the least exchange chip composition clog-free SRIO network in 18 tunnels
Structure is flutterred, Project Realization is simple, and it is at low cost, it is suitble to promote and apply.
The above is only a preferred embodiment of the present invention, it is noted that for the ordinary skill people of the art
For member, without departing from the technical principles of the invention, several improvement and deformations can also be made, these improvement and deformations
Also it should be regarded as protection scope of the present invention.
Claims (6)
1. a kind of clog-free SRIO network topology structure in 18 tunnels based on exchange chip, which is characterized in that handed over by 3 CPS1848
It changes i.e. CPS1848 chip A, CPS1848 chip B and CPS1848 chip C of chip to cascade, every CPS1848 exchange chip sheet
Body has 3 tunnels of 3 road SRIO 4x and CPS1848 chip B for providing the exchange of 12 road SRIO 4x high-speed datas, CPS1848 chip A
SRIO 4x is interconnected one to one, and the 3 road SRIO 4x of another 3 road SRIO 4x and CPS1848 chip C are interconnected one to one,
The another 3 road SRIO 4x of the another 3 road SRIO 4x and CPS1848 chip C of CPS1848 chip B is interconnected one to one, CPS1848 core
Respectively remaining 6 road SRIO 4x provides 18 tunnels clog-free full duplex friendship to piece A, CPS1848 chip B and CPS1848 chip C jointly
Change node.
2. a kind of working method of the clog-free SRIO network topology structure in 18 tunnel as described in claim 1, which is characterized in that fixed
Access between adopted CPS1848 chip A and CPS1848 chip B be access 1., between CPS1848 chip A and CPS1848 chip C
Access be access 2., access between CPS1848 chip B and CPS1848 chip C be access 3., CPS1848 chip A and 18
4. for access, CPS1848 chip B exchanges section with the clog-free full duplex in 18 tunnels to access between the clog-free full duplex switching node in road
5. for access, the access between the clog-free full duplex switching node of CPS1848 chip C and 18 tunnels is access to access between point
6. then the course of work of the clog-free SRIO network topology structure in 18 tunnel includes:
If the exchange between 18 road SRIO network nodes is not needed in CPS1848 chip A, CPS1848 chip B and CPS1848
Data exchange is carried out between chip C, then access 4. corresponding 6 road SRIO network node by being completed inside CPS1848 chip A
Exchange, access 5. completes to exchange inside CPS1848 chip B by corresponding 6 road SRIO network node, access 6. corresponding 6 tunnel
SRIO network node completes exchange inside CPS1848 chip C.
3. method according to claim 2, which is characterized in that the clog-free SRIO network topology structure in 18 tunnel it is worked
Journey further include: if SRIO network node needs to carry out 12 circuit-switched datas between CPS1848 chip A and CPS1848 chip B to exchange,
Then 4. corresponding 6 road SRIO network node data is transmitted to CPS1848 chip A to access, then by access 1. and (access 2., it is logical
Road is 3.) it is transmitted to CPS1848 chip B, finally it is transmitted to access 5. corresponding 6 road SRIO node.Remaining 6 road SRIO network node
Exchange is 6. completed inside CPS1848 chip C by access.
4. method according to claim 2, which is characterized in that SRIO network node is in CPS1848 chip A and CPS1848 core
The process that 12 circuit-switched data exchanges are carried out between piece C, with SRIO network node between CPS1848 chip A and CPS1848 chip B
The process for carrying out 12 circuit-switched data exchanges is similar.
Exist 5. carrying out 12 circuit-switched datas between CPS1848 chip B and CPS1848 chip C and exchanging process with SRIO network node
The process that 12 circuit-switched data exchanges are carried out between CPS1848 chip A and CPS1848 chip B is similar.
6. method according to claim 2, which is characterized in that if SRIO network node is in CPS1848 chip A, CPS1848
Data exchange is carried out between chip B and CPS1848 chip C, then 4. corresponding 3 road SRIO network node data passes through access to access
1. being transmitted to CPS1848 chip B, then it is transmitted to access 5. corresponding 3 road SRIO node；Access 4. remaining corresponding 3 road SRIO
2. network node data is transmitted to CPS1848 chip C by access, then be transmitted to access 6. corresponding 3 road SRIO node；Access
5. 3. remaining corresponding 3 road SRIO network node data are transmitted to CPS1848 chip C by access, then to be transmitted to access 6. right
3 road SRIO node of remaining answered.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201811465709.3A CN109672634B (en) | 2018-12-03 | 2018-12-03 | 18-path non-blocking SRIO network topology device and method based on switching chip |
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| CN201811465709.3A CN109672634B (en) | 2018-12-03 | 2018-12-03 | 18-path non-blocking SRIO network topology device and method based on switching chip |
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| CN109672634A true CN109672634A (en) | 2019-04-23 |
| CN109672634B CN109672634B (en) | 2020-11-06 |
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