CN104333519B - Strictly non-blocking switch network - Google Patents
Strictly non-blocking switch network Download PDFInfo
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- CN104333519B CN104333519B CN201410661871.8A CN201410661871A CN104333519B CN 104333519 B CN104333519 B CN 104333519B CN 201410661871 A CN201410661871 A CN 201410661871A CN 104333519 B CN104333519 B CN 104333519B
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Abstract
The invention relates to a data switch network in the communication field and specifically relates to a strictly non-blocking switch network. According to the switch network, 6 N*N (N must be the multiple of 4) switch chips are adopted to realize the strictly non-blocking switch network having the cross scale of 2N*2N. Each N*N switch chip is provided with N input channels and N output channels; the 6 N*N switch chips are matched to set up a 2N*2N switch network structure, and therefore, the strictly non-blocking switch network with 2N input channels and 2N output channels can be realized. The strictly non-blocking switch network has the beneficial effects that the switch architecture is simplified, the number and difficulty of cascade wiring are reduced, the hardware cost is reduced and the route selecting flexibility during switching is improved.
Description
Technical field
The present invention relates to the data switching networks in the communications field, and in particular to a kind of switching network for realizing strictly non-blocking
Network.
Background technology
With developing rapidly for communication technology, people gradually step up to the demand of data exchange.Traditional switching technology, such as
CrossBar is exchanged and Clos networks, although meet certain application demand, ensure that exchange is strictly non-blocking or wide
Justice is choke free, but also has some shortcomings, such as：Switching fabric is huge, and cascade cabling is complicated, and hardware cost is excessively high.
The content of the invention
Present invention aim to solve above-mentioned problems of the prior art, a kind of structure is especially provided and is simplified,
The exchange network of cascade cabling cleverly strictly non-blocking.
The present invention is adopted the technical scheme that：A kind of exchange network for realizing strictly non-blocking, it is characterised in that：The exchange
Network is 2Nx2N exchange networks, and the exchange chip of the multiple for being necessary for 4 by 6 NxN and N builds, and each NxN exchanges core
Piece be designed with it is N number of enter passage and it is N number of go out passage, a NxN exchange chips therein, the 2nd NxN exchange chips, the 3rd NxN hand over
Change chip and the 4th NxN exchange chips be respectively equipped with N/2 of exchange network external connection enter passage and with exchange network in
The N/2 of portion's connection enter passage and be connected with exchange network inside it is N number of go out passage；5th NxN exchange chips and the 6th NxN
Exchange chip be respectively equipped with exchange network inside be connected it is N number of enter passage and with exchange network external connection it is N number of go out it is logical
Road；The wherein N/4 of a NxN exchange chips and the 2nd NxN exchange chips enters passage and N/4 goes out passage respectively with the 3rd
N/4 of NxN exchange chips and the 4th NxN exchange chips goes out passage and N/4 enters passage and be connected；First NxN exchange chips and
The N/2 of the 2nd NxN exchange chips goes out passage and enters passage with two groups of N/2 of the 5th NxN exchange chips respectively to be connected；3rd
N/2 of NxN exchange chips and the 4th NxN exchange chips goes out passage and enters with two groups of N/2 of the 6th NxN exchange chips respectively
Passage is connected.
The present invention adopts 6 NxN（N is necessary for 4 multiple）Exchange chip, realize a crossover scale for 2Nx2N
Strictly non-blocking exchange network.Each NxN exchange chip enters to go out with N number of passage for N number of passage, and 6 NxN exchange chips coordinate,
Construct the 2Nx2N switch network architectures shown in Fig. 1, you can realize that 2N passage enters the strictly non-blocking exchange that 2N passage goes out
Network.
The invention has the advantages that：Architecture for exchanging has been simplified, the quantity and difficulty of cascade cabling, drop has been reduced
Low hardware cost, selects the motility of route when improve exchange.
Description of the drawings
Fig. 1 is 2Nx2N exchange network schematic diagrams；
Fig. 2 is 32x32 exchange network schematic diagrams；
Fig. 3 is 32x32 exchange network detailed structure views；
Fig. 4 is 8x8 exchange network schematic diagrams；
Fig. 5 is 4x4 exchange network schematic diagrams（a）；
Fig. 6 is 4x4 exchange network schematic diagrams（b）；
Fig. 7 is 4x4 exchange network detailed structure views；
Fig. 8 is 32x32 optical communication equipment front views；
Fig. 9 is 32x32 optical communication equipment side views；
Figure 10 is 32x32 optical communication equipment communication schemes；
Figure 11 is 32x32 clos exchange network schematic diagrams.
Specific embodiment
With reference to embodiments the invention will be further described with accompanying drawing：
With reference to Fig. 1, the exchange network of the strictly non-blocking of the present invention is 2Nx2N exchange networks, by 6 NxN and N is necessary
Exchange chip for 4 multiple builds, each NxN exchange chip be designed with it is N number of enter passage and it is N number of go out passage, it is therein
First NxN exchange chips 1, the 2nd NxN exchange chips 2, the 3rd NxN exchange chips 3 and the 4th NxN exchange chips 4 are respectively equipped with
N/2 for entering passage with N/2 of exchange network external connection and being connected with exchange network inside enters passage and and switching network
Network inside connection it is N number of go out passage；5th NxN exchange chips 5 and the 6th NxN exchange chips 6 be respectively equipped with exchange network
Portion connection it is N number of enter passage and with exchange network external connection it is N number of go out passage；A wherein NxN exchange chips 1 and second
The N/4 of NxN exchange chips 2 enter passage and N/4 go out passage respectively with the 3rd NxN exchange chips 3 and the 4th NxN exchange chips
N/4 of 4 goes out passage and N/4 enters passage and be connected；N/2 of first NxN exchange chips 1 and the 2nd NxN exchange chips 2 goes out logical
Road enters passage and is connected with two groups of N/2 of the 5th NxN exchange chips 5 respectively；3rd NxN exchange chips 3 and the 4th NxN exchange core
The N/2 of piece 4 goes out passage and enters passage with two groups of N/2 of the 6th NxN exchange chips 6 respectively to be connected.
Embodiment：Below by taking N=16 as an example, it is described in detail.
With reference to Fig. 2, using 6 3316 exchange chips, the strictly non-blocking switching network that a crossover scale is 32x32 is realized
Network.Wherein 3316 exchange chips enter to go out with 16 passages for 16 passages, can realize the switching fabric of 16x16.6 3316 exchange cores
Piece coordinates, and constructs the switching fabric shown in Fig. 2, you can realize that 32 passages enter the strictly non-blocking exchange network that 32 passages go out.
32x32 exchange network general descriptions are as follows：
The 32x32 exchange networks of the present embodiment are formed by 6 VSC3316 exchange chips interconnections.Wherein, 32 enter passage point
It is not distributed on four VSC3316 exchange chips that numbering is 1,2,3,4, it is 5,6 that 32 go out passage to be respectively distributed to number
On two VSC3316 exchange chips.It is clear for description, be by the path marking that enters that 32 are connected with exchange network outside below
IN1 ~ IN32,32 path markings that go out being connected with exchange network outside are OUT1 ~ OUT32, the such as Fig. 3 of the exchange network after labelling
It is shown.
With reference to Fig. 3,32x32 exchange networks are built by 6 VSC3316 exchange chips, each VSC3316 exchange chip
Be designed with 16 and enter passage and 16 go out passage, a VSC3316 exchange chips 1 therein, the 2nd VSC3316 exchange chips 2,
3rd VSC3316 exchange chips 3 and the 4th VSC3316 exchange chips 4 be respectively equipped with enter with 8 of exchange network external connection it is logical
Road, labelling is respectively IN1 ~ IN8, IN9 ~ IN16, IN17 ~ IN24 and IN25 ~ IN32；Further respectively have with inside exchange network
8 of connection enter passage and go out passage with 16 be connected inside exchange network；5th VSC3316 exchange chips 5 and the 6th
VSC3316 exchange chips 6 are respectively equipped with and go out passage with 16 of exchange network external connection, labelling be respectively OUT1 ~ OUT16 and
OUT17 ~ OUT32, is additionally provided with 16 be connected with exchange network inside and enters passage；A wherein VSC3316 exchange chips 1 and
4 of two VSC3316 exchange chips 2 enter passage and 4 go out passage respectively with the 3rd VSC3316 exchange chips 3 and the 4th
4 of VSC3316 exchange chips 4 go out passage and 4 enter passage and are connected；First VSC3316 exchange chips 1 and the 2nd VSC3316
8 of exchange chip 2 go out passage and enter passage with two groups 8 of the 5th VSC3316 exchange chips 5 respectively to be connected；3rd VSC3316
8 of the VSC3316 exchange chips 4 of exchange chip 3 and the 4th go out passage respectively with two group 8 of the 6th VSC3316 exchange chips 6
It is individual enter passage be connected.
32x32 exchange network strictly non-blockings are proved：The definition of strictly non-blocking clear and definite first, for a kind of switching network
Network, strictly non-blocking refers to no matter which kind of routing policy adopted there is no any blocked state.And what the present invention was previously mentioned
Strictly non-blocking, only limit unicast.Unicast is referred to, in a kind of exchange network, any input all the way at most only exchanges to defeated all the way
Go out.
Prove that the 32x32 exchange networks shown in Fig. 3 are strictly non-blockings, mentality of designing is as follows：
1. the construction featuress of the network are dissected, and the network model is disassembled, 32x32 exchange networks are split as
Four 8x8 switch network architectures, the switch network architecture figure of 8x8 is shown in Fig. 4.If it is strict nothing to demonstrate the 8x8 exchange networks
Obstruction, then the 32x32 exchange networks of four 8x8 exchange networks compositions are also strictly non-blocking, because four 8x8 are exchanged
The each leisure of network is exchanged, and is independent of each other.
2. to prove that the 8x8 exchange networks shown in Fig. 4 are strictly non-blockings, first 8x8 exchange networks can be torn open
Solution, disassembles into two 4x4 exchange networks as shown in Figure 5 and Figure 6.If it is strict without hindrance to demonstrate two 4x4 exchange networks
Plug, then the 8x8 that two 4x4 exchange networks are constituted is also strictly non-blocking, because each leisure of two 4x4 is exchanged, mutually
Do not affect.
3. therefore, to prove that 32x32 exchanges exchange network is strictly non-blocking, as long as proving shown in Fig. 5 and Fig. 6
Two 4x4 exchange networks are strictly non-blockings.
Two 4x4 exchange networks shown in analysis Fig. 5 and Fig. 6, it can be seen that the 4x4 exchange networks flip horizontal 180 of Fig. 5
Degree, you can obtain the 4x4 exchange networks shown in Fig. 6.As long as therefore proving out that the 4x4 exchange networks shown in Fig. 5 are strict without hindrance
Plug, then the 4x4 exchange networks shown in Fig. 6 are equally strictly non-blockings.
To prove network shown in Fig. 5, the exchange network shown in Fig. 5 is marked in detail, detailed structure view such as Fig. 7 institutes
Show.
With reference to Fig. 7, labelling IN1, IN2, IN3, IN4 are respectively the VSC3316 exchange chips of numbering 1,2,3,4 and enter to hold
Mouthful；Labelling OUT1, OUT2, OUT3, OUT4 are respectively the exit port of the VSC3316 exchange chips of numbering 5,6.
Four inbound ports of the above are listed successively to two exit ports, and all possible link is as follows：
During full intersection, the possibility combination of four inbound ports to two exit ports is as follows：
| IN1--> 5 | IN2--> 6 | IN3--> 5 | IN4--> 6 |
| IN1--> 5 | IN2--> 6 | IN3--> 6 | IN4--> 5 |
| IN1--> 5 | IN2--> 5 | IN3--> 6 | IN4--> 6 |
| IN1--> 6 | IN2--> 5 | IN3--> 6 | IN4--> 5 |
| IN1--> 6 | IN2--> 5 | IN3--> 5 | IN4--> 6 |
| IN1--> 6 | IN2--> 6 | IN3--> 5 | IN4--> 5 |
With the first combination IN1-->5, IN2-->6, IN3-->5, IN4-->As a example by 6, optional link is listed below：
IN1-->5 optional links are：1-5 or 1-4-2-5；
IN2-->6 optional links are：2-3-6 or 2-3-1-4-6；
IN3-->5 optional links are：3-1-5 or 3-1-4-2-5；
IN4-->6 optional links are：4-6 or 4-2-3-6.
During routing, note it is following some：
A. the principle of SPF is followed.
B. because 4x4 exchange networks self structure is limited, the link being connected between two VSC3316 exchange chips only has one.
C. no matter which first routing in four inbound ports, routing after which, only four inbound port all routing successes,
Just it is counted as work(.
The routing order for assuming four inbound ports is IN1-->5, IN2-->6, IN3-->5, IN4-->6, foundation above a,
3 points described in b, c, final link is：
IN1-->5 select links be：1-5；
IN2-->6 select links be：2-3-6；
IN3-->5 select links be：3-1-5；
IN4-->6 select links be：4-6.
In the same manner, other routing orders of four inbound ports, also can routing success.Therefore the combination（IN1-->5, IN2--
>6, IN3-->5, IN4-->6）Can routing success.In the same manner, it is other it is several combination also can routing success, therefore, Fig. 7 and Fig. 5
Shown 4x4 exchange networks are strictly non-blockings.
Because the 4x4 exchange networks shown in Fig. 6 are the results of the 4x4 exchange network flip horizontal 180 degrees shown in Fig. 5, and
And the 4x4 exchange networks shown in Fig. 5 are strictly non-blockings, so the 4x4 exchange networks shown in Fig. 6 are also strictly non-blocking
's.Two 4x4 exchange networks shown in Fig. 5 and Fig. 6 combine, you can the 8x8 exchange networks shown in Fig. 4 are obtained, due to two
Individual 4x4 exchange networks strictly non-blocking, therefore the 8x8 exchange networks shown in Fig. 4 are also strictly non-blocking.Shown in four Fig. 4
8x8 exchange networks combine, you can obtain the 32x32 exchange networks shown in Fig. 3, due to four 8x8 strictly non-blockings, because
This, the 32x32 exchange networks shown in Fig. 3 are also strictly non-blocking.
32x32 exchange network application cases：
According to the 32x32 exchange networks, the present invention has customized a set of optical communication equipment, and specific design is as follows：
Equipment form is the 19 inch standard cabinets of high 2U, and inside is made up of four pieces of boards：One piece of main control card 7, one block of electricity
8, one piece of source card, 9, one piece of service card service card 10.Crucial processing component on main control card is an ARM9 chip and a FPGA
Chip, the crucial processing component on every piece of service card is respectively an ARM7 chip.There are three 3316 exchanges on every piece of service card
Chip, totally six 3316 exchange chips constitute the exchange network of 32x32 as shown in Figure 2 for two pieces of service cards, wherein numbering is 1,2,5
Three 3316 exchange chips on one piece of service card, numbering be 3,4,6 three 3316 exchange chips in another piece of service card
On.The external interface of equipment is the network interface on main control card, and computer controls the equipment by network interface.Equipment front view such as Fig. 8 institutes
Show, equipment side view is as shown in Figure 9.
Computer carries out Control on Communication by the ARM9 chips on network interface and main control card, the ARM9 chips and FPGA on main control card
Chip carries out Control on Communication by SPI, and the fpga chip on main control card is entered with the ARM7 chips on two pieces of service cards by serial ports
Row Control on Communication, the ARM7 chips on every piece of service card are all to control respective three 3316 exchange chips by IIC to be handed over
Change.Detailed communication is as shown in Figure 10.
When to swap, flow process is as follows：First exchange data is generated by computer end, main control card is sent to by network interface
On ARM9 chips, then ARM9 chips carry out route computing, calculate the concrete link data to be switched, by SPI send
To the fpga chip on main control card, then fpga chip is sent to two pieces of business by the concrete link data that serial ports will switch
ARM7 chips on card, the ARM7 chips on last every piece of service card control corresponding 3316 exchange chip and are handed over by IIC
Change, to realize final exchange.
32x32 exchange network application effects：
Traditional three-level CLOS network is a L3 Switching network, and ground floor is made up of r nxm, referred to as input layer；The
Two layers are made up of m rxr, referred to as intermediate layer；Third layer is made up of r mxn, referred to as output layer.Each input layer crosspoint
One and only one link and each intermediate layer crosspoint between is connected, and each intermediate layer crosspoint and each output layer are handed over
Change one and only one link between unit to be connected, but input layer crosspoint and output layer crosspoint are not linked.Work as m
During >=2n-1, three layers of CLOS networks are strictly non-blocking network.
A set of optical communication equipment that 32x32 exchange networks according to the present embodiment are customized has highlighted in actual applications the friendship
The superiority of switching network.With the 32x32 strictly non-blocking exchange networks detailed construction of traditional clos networkings as schemed
Shown in 11, the 32x32 optic communication switching equipment of a set of said function are made with the clos networks.The final index pair of two kinds of equipment
Than situation such as following table：
| With the equipment of the 32x32 exchange networks customization of the present invention | The equipment customized with traditional clos 32x32 exchange networks |
| Consume 6 VSC3316 exchange chips | Consume 12 VSC3316 exchange chips |
| Cascade cabling sum is 64 | Cascade cabling sum is 128 |
| The VSC3316 exchange chips passed through required for exchanging every time Number flexibly, when shortest path is exchanged, it is only necessary to from entering end Mouth is directly sent to exit port. | Any once exchange all has to pass through 3 VSC3316 exchange cores Piece, even if during whole link idles, exchange also must pass through first Three VSC3316 exchange chips. |
The contrast more than finds, using the equipment of the 32x32 exchange networks customization of the present invention, it is only necessary to 6 3316 exchanges
Chip, hardware cost is reduced；Cascade cabling only needs 64, reduces the quantity and difficulty of cabling；And select road when exchanging
By motility improve.
Claims (1)
1. a kind of exchange network for realizing strictly non-blocking, it is characterised in that：The exchange network is 2Nx2N exchange networks, by 6
The exchange chip of the multiple that individual NxN and N are necessary for 4 builds, each NxN exchange chip be designed with it is N number of enter passage and N number of
Go out passage, a NxN exchange chips therein（1）, the 2nd NxN exchange chips（2）, the 3rd NxN exchange chips（3）With the 4th
NxN exchange chips（4）It is respectively equipped with the N/ for entering passage with N/2 of exchange network external connection and being connected with exchange network inside
2 enter passage and with exchange network inside be connected it is N number of go out passage；5th NxN exchange chips（5）Core is exchanged with the 6th NxN
Piece（6）Be respectively equipped with exchange network inside be connected it is N number of enter passage and with exchange network external connection it is N number of go out passage；
A wherein NxN exchange chips（1）With the 2nd NxN exchange chips（2）N/4 enter passage and N/4 goes out passage respectively with the
Three NxN exchange chips（3）With the 4th NxN exchange chips（4）N/4 go out passage and N/4 enters passage and be connected；First NxN is handed over
Change chip（1）With the 2nd NxN exchange chips（2）N/2 go out passage respectively with the 5th NxN exchange chips（5）Two groups of N/2
Enter passage to be connected；3rd NxN exchange chips（3）With the 4th NxN exchange chips（4）N/2 go out passage respectively with the 6th NxN
Exchange chip（6）Two groups of N/2 enter passage and be connected.
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Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105357153A (en) * | 2015-11-27 | 2016-02-24 | 天津光电通信技术有限公司 | Non-blocking switching network architecture based on MESH structure |
| CN107733816B (en) * | 2017-11-29 | 2021-05-25 | 天津光电通信技术有限公司 | Novel strict non-blocking switching network |
| CN108183872B (en) * | 2017-12-27 | 2020-12-22 | 中科曙光信息产业成都有限公司 | Switch system and construction method thereof |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002325087A (en) * | 2001-04-25 | 2002-11-08 | Nec Corp | Unblocked switch system, its switching method and program |
| CN101106732A (en) * | 2007-06-01 | 2008-01-16 | 中国电子科技集团公司第五十四研究所 | Large-capacity and high-performance overlapped switching method |
| CN103763165A (en) * | 2013-11-26 | 2014-04-30 | 苏州爱思索电子科技有限公司 | Crossbar bus structure suitable for cascade connection |
| CN204291038U (en) * | 2014-11-19 | 2015-04-22 | 天津光电通信技术有限公司 | The switching network of strictly non-blocking |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6819675B2 (en) * | 2000-12-28 | 2004-11-16 | International Business Machines Corporation | Self-route multi-memory expandable packet switch with overflow processing means |
| WO2007087275A2 (en) * | 2006-01-23 | 2007-08-02 | Allied Telesis, Inc. | Method and system for improving traffic distribution across a communication network |
-
2014
- 2014-11-19 CN CN201410661871.8A patent/CN104333519B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002325087A (en) * | 2001-04-25 | 2002-11-08 | Nec Corp | Unblocked switch system, its switching method and program |
| CN101106732A (en) * | 2007-06-01 | 2008-01-16 | 中国电子科技集团公司第五十四研究所 | Large-capacity and high-performance overlapped switching method |
| CN103763165A (en) * | 2013-11-26 | 2014-04-30 | 苏州爱思索电子科技有限公司 | Crossbar bus structure suitable for cascade connection |
| CN204291038U (en) * | 2014-11-19 | 2015-04-22 | 天津光电通信技术有限公司 | The switching network of strictly non-blocking |
Non-Patent Citations (2)
| Title |
|---|
| "严格无阻塞多播三级Clos 网的优化";刘燕君等;《小型微型计算机系统》;20120331;第33卷(第3期);第452-456页 * |
| Clos 型大规模ATM 交换网络;刘亚社等;《电子学报》;19991001;第27卷(第10期);第15-19页 * |
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