CN208969660U - A kind of SRIO exchange board of OpenVPX structure - Google Patents
A kind of SRIO exchange board of OpenVPX structure Download PDFInfo
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- CN208969660U CN208969660U CN201821842534.9U CN201821842534U CN208969660U CN 208969660 U CN208969660 U CN 208969660U CN 201821842534 U CN201821842534 U CN 201821842534U CN 208969660 U CN208969660 U CN 208969660U
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Abstract
The utility model provides a kind of SRIO exchange board of OpenVPX structure, belongs to high speed exchange board field, and the utility model is broadly divided into four modules, i.e. CPU management module, SMC module, SRIO Switching Module and 1G Ethernet Switching Module；Wherein, SMC module, SRIO Switching Module, 1G Ethernet Switching Module are connected with CPU management module respectively, and SMC module is connected with 1G Ethernet Switching Module.The board meets OpenVPX standard, is suitable for highly reliable, the high speed exchange of high performance signal process field.The board externally provides the SRIO exchange and 20 road 1G Ethernet exchange of 20 tunnel, 4 X 5G.
Description
Technical field
The utility model relates to exchange board field at a high speed, specifically a kind of SRIO power board of OpenVPX structure
Card.
Background technique
It is very high to the requirement for calculating power in the field of signal processing that high density calculates, generally using multiple computing units
Architecture design, multiple computing units just need the crosspoint of low delay, high speed.SRIO communication obviously meets low delay, height
The requirement of speed, using SRIO as the communication bus between unit is to select well.SRIO as high speed, low delay plate between
Bus protocol has excellent characteristics in terms of high performance distributed computing machine, high performance signal.
Summary of the invention
The purpose of this utility model seeks to provide a kind of SRIO exchange board of OpenVPX structure based on the above issues,
The board meets OpenVPX standard, is suitable for highly reliable, the high speed exchange of high performance signal process field.
Technical solution adopted in the utility model is:
Board is broadly divided into four functional modules, CPU management module, SMC module, SRIO Switching Module, 1G
Ethernet Switching Module.
Wherein SRIO Switching Module and 1G Ethernet Switching Module are functional module and the master that board externally provides
It services.
Make introductions all round SRIO Switching Module and 1G Ethernet Switching Module below.
SRIO Switching Module externally provides 20 road X4 5Gpbs full speed nonblocking switchings, using single SRIO exchange chip without
Method meets this demand, and single IDT CPS1848 at most may be implemented 12 road X4 5Gpbs full speed nonblocking switchings, in this scheme
The mode for having used 5 IDT CPS1848 chips to interconnect, wherein 4 road X4 5Gpbs are externally provided per a piece of CPS1848, it is remaining
8 tunnels be all used for interconnected.1G Ethernet Switching Module at most can be with using this exchange of BCM56334 IC, this IC
24 road 1G Serdes communication links are externally provided, therefore design requirement can be met using a piece of BCM56334.
SMC management module uses AST2400 as host CPU, this CPU aim at board health control and cabinet health control and
Design, provides I2C interface and NCSI interface very rich.
IPMI shelf management agreement is supported on software.Health control of the SMC as entire machine, can by I2C or
Person Ethernet obtains the health status information of other boards, provides unified management, configuration interface to user.
CPU management module is responsible for the initialization and configuration work of entire board service logic.SRIO Switching Module needs are matched
Routing iinformation is set, by CPU management module by I2C bus to each CPS1848 separate configurations routing iinformation.1G Ethernet
Switching Module needs to carry out BCM56334 exchange chip initial configuration, and CPUCPU management module uses the high speed of PCIE X1
Communication interface is configured and is supervised to exchange chip.
The CPU of the minimum system of CPU management module uses P3041 as host CPU, and memory uses the memory of DDR3,
NorFlash is stored as starting Flash, the firmware of starting into this NorFlash.
The utility model mainly has the feature that
1: meeting OpenVPX standard, be suitable for highly reliable, the high speed exchange of high performance signal process field.
2: supporting the SRIO exchange of external 20 tunnel, 4 X 5G.
3: meeting Slot Profiles SLT6-SWH-16U20F-10.4.2 specification.
4: supporting SMC management function.
5: SRIO being supported the functions such as to enumerate, route.
Detailed description of the invention
Attached drawing 1 is the entire block diagram of the utility model；
Attached drawing 2 is CPS1848 interconnected topological diagram.
Specific embodiment
The utility model is described in detail below with reference to the accompanying drawing.
A kind of SRIO of OpenVPX structure of the utility model exchanges board, which externally provides 20 tunnel, 4 X 5G's
SRIO exchange.The exchange board meets Slot Profiles SLT6-SWH-16U20F-10.4.2 specification, and SMC is supported to manage function
Can, the functions such as support SRIO is enumerated, routed.
As shown in Figure 1, board is broadly divided into four functional modules, CPU management module, SMC module, SRIO Switching Module,
1G Ethernet Switching Module.
The hard core control CPU of the board is P3041, and groundwork is that configuration management 1G exchanges IC BCM56334, and SRIO is whole
A network is enumerated, the management work of the SRIO such as routing setting.
SMC this part major function is to obtain, manage the state of entire cabinet, including radiator fan controls, core I C temperature
Degree, remote on-off etc. function.
SRIO Switching Module and 1G Ethernet Switching Module are functional module and the main clothes that board externally provides
Business.
SRIO exchange chip is the CPS1848 of IDT, and the maximum 12 road 5G X4 SRIO that externally provide of each CPS1848 connect
Mouthful, it is therefore desirable to multi-disc interconnection exchanges to provide 20 road SRIO 5G X4.Selection is the mode of 5 CPS1848 interconnection, each
CPS1848 externally exports 4 tunnels, and remaining 8 tunnel is completely used for internal system interconnection, to realize full line speed, nonblocking switching.Specifically
Interconnecting relation is as shown in Figure 2.
1G Ethernet Switching Module at most can externally provide 24 tunnels using this exchange of BCM56334 IC, this IC
1G Serdes communication link, therefore design requirement can be met using a piece of BCM56334.SMC management module uses
As host CPU, this CPU aims at board health control and cabinet health control and designs AST2400, provides very rich
I2C interface and NCSI interface.IPMI shelf management agreement is supported on software.Health control of the SMC as entire machine, can be with
The health status information that other boards are obtained by I2C or Ethernet provides unified management, configuration interface to user.
CPU management module is responsible for the initialization and configuration work of entire board service logic.SRIO Switching Module needs to configure routing letter
Breath, by CPU management module by I2C bus to each CPS1848 separate configurations routing iinformation.1G Ethernet Switching Module
Need to BCM56334 exchange chip carry out initial configuration, CPU using PCIE X1 high speed communication interface to exchange chip into
Row configuration and supervision.The CPU of the minimum system of CPU management module uses P3041 as host CPU, and memory uses the memory of DDR3,
NorFlash is stored as starting Flash, the firmware of starting into this NorFlash.
The board is broadly divided into four layers from logic function, and first layer mainly realizes the functions such as power supply, reset.The second layer is
Management level, management level major function are the health status of management exchange board.The core I C used is AST2400, and what is used is logical
News agreement is IPMB.The physical interconnection interface externally provided has I2C and 1 G Ethernet, I2C to be mainly used for complete machine initialization
When according to each board of application demand switching on and shutting down, according to slot number be each computing unit for being connected to crosspoint point after booting
Device ID with SRIO.
After the BMC starting of each board, use 1G Ethernet as link layer transfer IPMB agreement, also namely what is often called
IPBI over Ethernet.Third layer is control layer, is mainly used for the configuration work of each board service layer and obtains shape
State work.
The physical link that this layer provides is also 1G Ethernet, and the 1G Ethernet interface of management level and control layer is
It is common, use NCSI technology.This SRIO exchange board externally provides 20 road 1G Ethernet, and the exchange IC used is
Interface between BCM56334 and CPU is PCIE.Data Layer externally provides 20 road 5G X primarily to high-speed data exchange
4 SRIO interfaces.
It except for the technical features described in the specification, is the known technology of those skilled in the art.
Claims (7)
1. a kind of SRIO of OpenVPX structure exchanges board, which is characterized in that be broadly divided into four modules, i.e. CPU manages mould
Block, SMC module, SRIO Switching Module and 1G Ethernet Switching Module；
Wherein, SMC module, SRIO Switching Module, 1G Ethernet Switching Module are connected with CPU management module respectively, SMC
Module is connected with 1G Ethernet Switching Module.
2. the SRIO of OpenVPX structure according to claim 1 exchanges board, which is characterized in that
SRIO Switching Module externally provides 20 road X4 5Gpbs full speed nonblocking switchings, mutual using 5 IDT CPS1848 chips
The mode of connection, each IDT CPS1848 realize 12 road X4 5Gpbs full speed nonblocking switchings, wherein external per a piece of CPS1848
4 road X4 5Gpbs are provided, remaining 8 tunnel is all used for interconnected.
3. the SRIO of OpenVPX structure according to claim 1 exchanges board, which is characterized in that
1G Ethernet Switching Module exchanges IC using BCM56334.
4. the SRIO of OpenVPX structure according to claim 1 exchanges board, which is characterized in that
SMC management module uses AST2400 as host CPU.
5. the SRIO of OpenVPX structure according to claim 1 exchanges board, which is characterized in that
The CPU of the minimum system of CPU management module uses P3041 as host CPU, and memory uses the memory of DDR3, NorFlash
As starting Flash, the firmware of starting is stored into this NorFlash.
6. the SRIO of OpenVPX structure according to claim 2 exchanges board, which is characterized in that
SRIO Switching Module needs to configure routing iinformation, is independently matched by I2C bus to each CPS1848 by CPU management module
Set routing iinformation.
7. the SRIO of OpenVPX structure according to claim 3 exchanges board, which is characterized in that
1G Ethernet Switching Module needs to carry out BCM56334 exchange chip initial configuration, and CPU management module uses
The high speed communication interface of PCIE X1 is configured and is supervised to exchange chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821842534.9U CN208969660U (en) | 2018-11-09 | 2018-11-09 | A kind of SRIO exchange board of OpenVPX structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821842534.9U CN208969660U (en) | 2018-11-09 | 2018-11-09 | A kind of SRIO exchange board of OpenVPX structure |
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| Publication Number | Publication Date |
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| CN208969660U true CN208969660U (en) | 2019-06-11 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110955619A (en) * | 2019-11-22 | 2020-04-03 | 武汉船舶通信研究所（中国船舶重工集团公司第七二二研究所） | Combined complete machine system based on standard bus architecture and construction method |
-
2018
- 2018-11-09 CN CN201821842534.9U patent/CN208969660U/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110955619A (en) * | 2019-11-22 | 2020-04-03 | 武汉船舶通信研究所（中国船舶重工集团公司第七二二研究所） | Combined complete machine system based on standard bus architecture and construction method |
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| TR01 | Transfer of patent right |
Effective date of registration: 20211101 Address after: 250100 building S02, No. 1036, Langchao Road, high tech Zone, Jinan City, Shandong Province Patentee after: Shandong Inspur Scientific Research Institute Co.,Ltd. Address before: 250100 First Floor of R&D Building 2877 Kehang Road, Sun Village Town, Jinan High-tech Zone, Shandong Province Patentee before: JINAN INSPUR HIGH-TECH TECHNOLOGY DEVELOPMENT Co.,Ltd. |