CN109445855A - A kind of bridge-set integrated for multi-path low speed peripheral hardware - Google Patents
A kind of bridge-set integrated for multi-path low speed peripheral hardware Download PDFInfo
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- CN109445855A CN109445855A CN201811276109.2A CN201811276109A CN109445855A CN 109445855 A CN109445855 A CN 109445855A CN 201811276109 A CN201811276109 A CN 201811276109A CN 109445855 A CN109445855 A CN 109445855A
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- 230000001360 synchronised effect Effects 0.000 claims description 30
- 230000002457 bidirectional effect Effects 0.000 claims description 7
- 230000010354 integration Effects 0.000 claims description 7
- 238000012545 processing Methods 0.000 claims description 6
- 238000005070 sampling Methods 0.000 claims description 3
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
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Abstract
The invention belongs to digital circuit Front-end Design technical fields, and in particular to a kind of applied to the bridge-set integrated for multi-path low speed peripheral hardware for enclosing extension low-speed peripheral outside the processor.Present invention can assure that carrying out reliable and stable data transmitting from higher speed processor external expansion interface to low-speed peripheral.Compared with the scheme for using discrete device to build, the present invention can greatly reduction circuit plate suqare, achieve the purpose that reduce cost, while also providing convenience for logic debugging and use.The present invention can easily provide user in application process and extend setting, facilitate and increase or reduce logic according to actual use situation using stock number, have good adaptability.In addition, the expansible peripheral unit in the present invention can also cascade use, two-level address mapping relations are constructed, the design less for address space also has stronger adaptability.In the case where bandwidth and FPGA resource allow, it is possible to provide realize cross clock domain synchronization process between a processor Peripheral Interface and any multi-path low speed peripheral apparatus.
Description
Technical Field
The invention belongs to the technical field of digital circuit front end design, and particularly relates to a bridging device for multi-path low-speed peripheral integration, which is applied to low-speed peripheral equipment expanded on the periphery of a processor.
Background
In the field of industrial control, low-speed communication interfaces such as serial ports and CAN are common command and data transmission ways. In a whole machine system, it is common that a plurality of serial ports and a CAN are integrated on a host node or a relay node. These control systems are typically used in the embedded domain, mounted in the chassis using line cards. The ply-yarn drill size is less, when using traditional serial ports control chip and CAN interface control chip to realize, CAN appear the not enough condition of integrated circuit board area. By integrating a single FPGA chip with proper capacity at the periphery of the processor and integrating multi-path serial port logic, CAN control logic and bridging logic into the FPGA chip, the area of the serial port and the CAN line card CAN be greatly reduced.
Usually, the clock frequencies between the external expansion interface of the processor and the external low-speed device are different, and the speed of the external expansion interface of the processor is generally higher than that of the external device interface and is about 2-3 times of the logic working speed of the external device interface. At this time, a clock domain crossing condition exists between the multi-path serial port logic and the external low-speed device, and if a proper bridging structure cannot be used, the occupation of logic resources is large, or a function error is caused by synchronization failure.
Disclosure of Invention
Technical problem to be solved
The invention provides a bridging device for multi-path low-speed peripheral integration, which aims to solve the problem of synchronizing the clock domain crossing behavior between multi-path serial port logic and external low-speed equipment.
(II) technical scheme
In order to solve the above technical problem, the present invention provides a bridging device for multi-channel low-speed peripheral integration, which includes a synchronous bridging unit and an expandable peripheral interface unit; the synchronous bridging unit is a bidirectional interface unit, one side interface realizes the connection with an external expansion interface of the processor, and the other side interface realizes the connection with an expandable peripheral interface unit; the request for accessing the external equipment is sent by the processor, and one side of the fast clock domain of the synchronous bridging unit receives the access request and synchronizes the request to one side of the slow clock domain; signals on two sides of different clock domains in the synchronous bridging unit realize a clock domain crossing synchronous function of transmitting data and control signals from a high-speed interface to a low-speed interface in a request, sampling and feedback handshake mode; the expandable peripheral interface unit is a bidirectional interface unit, one side interface realizes the connection with the synchronous bridging unit, and the other side realizes the connection with the multi-path low-speed peripheral equipment.
Furthermore, address and data buses between the synchronous bridging unit and the extensible peripheral interface unit are realized in a 32-bit width discrete mode, and data input and data output are realized in a discrete mode.
Furthermore, a flow control backpressure signal is arranged between the synchronous bridging unit and the expandable peripheral interface unit, the flow control backpressure signal is used for feeding back the data processing condition of the current peripheral to the processor side, the sending behavior of the processor is controlled at the necessary moment of inputting the sending data, and the buffer area of the low-speed peripheral is ensured not to be filled with the frequent sending request of the processor, so that the overflow is caused.
Furthermore, the synchronous bridge unit works by using an extended peripheral interface clock at the side connected with the external expansion interface of the processor, and the working frequency of the peripheral interface clock is 1/2 or 1/3 of the frequency of the external expansion interface clock of the processor.
Furthermore, the expandable peripheral interface unit completes configuration in a macro parameter definition mode, and at most 232 external expansion low-speed devices are connected.
Furthermore, the expandable peripheral interface unit is provided with a register array which is used for collecting and storing the interrupt state of the external expandable low-speed equipment and reporting the interrupt to the processor.
(III) advantageous effects
The bridging device for multi-path low-speed peripheral integration provided by the invention can ensure that the external expansion interface of the higher-speed processor can stably and reliably transmit data to the low-speed external equipment. Compared with the scheme built by using discrete devices, the invention can greatly reduce the area of the circuit board, achieve the purpose of reducing the cost and simultaneously provide convenience for logic debugging and use. The invention can conveniently provide user extension setting in the application process, is convenient to increase or reduce the logic use resource amount according to the actual use condition and has good adaptability. In addition, the expandable peripheral unit in the invention can be used in a cascade mode to construct a secondary address mapping relation, and has stronger adaptability to the design with less address space. Under the condition of allowing bandwidth and FPGA resources, a processor peripheral interface and any multi-path low-speed peripheral equipment can be provided to realize cross-clock domain synchronous processing.
Drawings
FIG. 1 is a block diagram of a bridge device according to an embodiment of the present invention;
fig. 2 is a schematic diagram illustrating connection details of a bridging device according to an embodiment of the present invention.
Detailed Description
In order to make the objects, contents and advantages of the present invention clearer, the following detailed description of the embodiments of the present invention will be made in conjunction with the accompanying drawings and examples.
The embodiment provides a bridging device for multi-path low-speed peripheral integration, which integrates six-path serial ports and four-path CAN controllers, and the architecture of the bridging device is shown in fig. 1. The bridging device comprises a synchronous bridging unit and an extensible peripheral interface unit. The synchronous bridging unit is a bidirectional interface unit, and an interface at one side is connected with an external expansion interface of the processor; and the interface at the other side realizes the connection with the extensible peripheral interface. The processor can use a synchronous extension mode to realize interconnection with the synchronous bridging unit by using any clock within 100 MHz. The request for accessing the external device is sent by the processor, and the fast clock domain side of the synchronous bridging unit receives the access request and synchronizes the request to the slow clock domain side. For the case that one side of the slow clock domain is divided into a plurality of clock distributions, a synchronous bridging unit can be used for secondary division.
Details of the connection between the synchronization bridge unit and the extensible peripheral interface unit are shown in fig. 2. The synchronous bridging unit interface has the characteristics of high bandwidth and controllable flow. The address bus and the data bus are realized in a 32-bit width discrete mode, the data input and the data output are realized in a discrete mode, and the maximization of the working bandwidth is ensured by the parallel 32-bit bidirectional data channel. The interface is provided with a flow control backpressure signal, can feed back the current data processing condition of the peripheral equipment to the processor side, provides the flow control backpressure signal at the necessary moment of inputting and sending data, controls the sending behavior of the processor, ensures the reliability of the working process of the peripheral equipment, and ensures that the buffer area of the low-speed peripheral equipment cannot be filled with the frequent sending request of the processor to cause overflow. The other side of the synchronous bridging unit works by using an extended peripheral interface clock, and the working frequency of the peripheral interface clock is specified to be about 1/2 or 1/3 of the frequency of the external extended interface clock of the processor, and no special phase requirement exists. The synchronous processing of the clock domain crossing signals is realized by the signals at two sides of different clock domains through request, sampling and feedback handshake inside the synchronous bridging unit.
From the architecture perspective, the expandable peripheral interface unit is also a bidirectional interface unit, one side interface realizes the connection with the synchronous bridging unit, and the other side realizes the connection with the multi-path low-speed peripheral equipment. The expandable peripheral interface part completes configuration by a macro definition parameter mode, and can be connected with 232 low-speed peripheral equipment at most under the condition that the peripheral expansion address of the processor allows. The expandable peripheral interface unit configured by macro definition switch can define any position in 32-bit address as the starting point of the chip selection address segment of the peripheral unit and can specify any width in 32-bit address width as the decoding width. In addition, the expandable peripheral interface unit is also provided with a register array which can be used for collecting and storing the interrupt state of the external expandable low-speed equipment and reporting the interrupt to the processor. The processor can inquire the concrete register number of the reported interrupt by a register access mode and take corresponding processing action.
The above description is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, several modifications and variations can be made without departing from the technical principle of the present invention, and these modifications and variations should also be regarded as the protection scope of the present invention.
Claims (6)
1. A bridging device for multi-path low-speed peripheral integration is characterized in that the bridging device comprises a synchronous bridging unit and an expandable peripheral interface unit; wherein,
the synchronous bridging unit is a bidirectional interface unit, one side interface realizes the connection with an external expansion interface of the processor, and the other side interface realizes the connection with the expandable peripheral interface unit; the request for accessing the external equipment is sent by the processor, and the quick clock domain side of the synchronous bridging unit receives the access request and synchronizes the request to the slow clock domain side; signals on two sides of different clock domains in the synchronous bridging unit realize a clock domain crossing synchronous function of transmitting data and control signals from a high-speed interface to a low-speed interface in a request, sampling and feedback handshake mode;
the extensible peripheral interface unit is a bidirectional interface unit, one side interface is connected with the synchronous bridging unit, and the other side interface is connected with the multi-path low-speed peripheral equipment.
2. The bridging apparatus according to claim 1, wherein the address and data buses between the synchronous bridging unit and the expandable peripheral interface unit are implemented in a 32-bit width discrete manner, and the data input and data output are implemented in a discrete manner.
3. The bridging apparatus according to claim 1, wherein a flow control backpressure signal is provided between the synchronous bridging unit and the expandable peripheral interface unit, the flow control backpressure signal is used for feeding back a data processing status of a current peripheral to the processor side, and when necessary data is input and sent, sending behavior of the processor is controlled, so that it is ensured that a buffer of a low-speed peripheral is not filled with frequent sending requests of the processor, which results in overflow.
4. The bridge apparatus as claimed in claim 1, wherein the synchronous bridge unit operates with an extended peripheral interface clock on the side of the processor external expansion interface connection, the peripheral interface clock operating at 1/2 or 1/3 times the processor external expansion interface clock frequency.
5. The bridging apparatus according to claim 1, wherein the extensible peripheral interface unit is configured in a macro-defined parameter manner, and is connected to a maximum of 232 external extensible low-speed devices.
6. The bridge apparatus as claimed in claim 1, wherein the extensible peripheral interface unit is provided with a register array for collecting and storing the interrupt status of the external extensible low speed device and reporting the interrupt to the processor.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201811276109.2A CN109445855B (en) | 2018-10-30 | 2018-10-30 | Bridging device for multi-path low-speed peripheral integration |
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| CN201811276109.2A CN109445855B (en) | 2018-10-30 | 2018-10-30 | Bridging device for multi-path low-speed peripheral integration |
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