CN102073481A - Multi-kernel DSP reconfigurable special integrated circuit system - Google Patents
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Abstract
The invention discloses a multi- kernel DSP (digital signal processing) reconfigurable special integrated circuit system, belonging to the technical field of digital signal processing, and comprising: an internal bus, and a control processor kernel, an enhanced direct memory access, an input and output cache, a DSP multi-kernel array, a configuration information cache, a reconfigurable logic unit and an internal cache which are all connected with the internal bus, wherein the DSP multi-kernel array is connected with the configuration information cache and the reconfigurable logic unit through a reconfigurable on-chip interconnection mode and transmits the configuration information and reconfigurable information. The multi-kernel DSP reconfigurable special integrated circuit system can be well combined with an IP multiplexing technology of SoC (System on a Chip), a multi-kernel DSP reconfigurable ASIC (Application Specific Integrated Circuit) takes the DSP multi-kernel array as a core, and simultaneously, integrates IP modules, such as a logic control, an embedded memory, a data interface and the like, thereby being capable of flexibly and efficiently implement large scale computing.
Description
Technical field
What the present invention relates to is a kind of device of digital signal processing technique field, specifically is a kind of multi-core DSP restructural special IC system.
Background technology
In the large-scale calculations field, reconfigurable system is one of a present architecture research focus, and it combines the dirigibility of general processor and the high efficiency of ASIC (special chip) well, is more satisfactory solution in the large-scale calculations.
Tradition DSP has that arithmetic speed is low, hardware configuration not restructural, exploitation upgrade cycle long and shortcoming such as portable not, towards large-scale calculations the time, this shortcoming is just more obvious.ASIC has greater advantage at aspects such as performance, area and power consumptions, but changeable application demand and the complexity that increases fast make the design of ASIC and validation difficulty big, and the construction cycle is long, is difficult to satisfy the product requirement of application fast.In programmable logic device (PLD), though the Virtex-6 Series FPGA (field programmable gate array) of Xilinx company utilizes the DSP48E1 slice of 600MHz to realize surpassing 1000 GMACS (1 * 10
12Inferior multiply accumulating computing/second) performance, but towards large-scale calculations the time needs the circuit scale of configuration excessive, and is comprehensive and setup time is long, and actual operating frequency is not high, is difficult to keep the high performance while, the target of pursuit dirigibility and low-power consumption.
In existing restructural research about DSP, totem (TOTEM) plan of Washington, DC university and Northwest University is arranged, the dragon of Northwestern Polytechnical University rises the research of DR restructural dsp processor.They have all studied reconfigurable DSP is main target, emphasizes its high-performance and dirigibility, has but sacrificed its logic control as general processor.Because the serial structure of DSP, hundreds of back and forth may circulate when carrying out complex calculation, therefore speed instead rather than very fast, single dsp processor is difficult to satisfy the above performance requirement of 10 GMACS, when large-scale calculations, the situation that often needs high-level parallel processing, the inferior position of single DSP is just more obvious.On general marketplace, series of products combine DSP and CPU to " Leonardo da Vinci (the Da Vinci) " of TI (Texas Instruments) company, but this technology does not relate to the restructural technology.
Find by prior art documents, Chinese patent application number is: 200410013670.3, name is called: a kind of based on CORDIC cellular array formula restructural DSP engine chip structure, this patent disclosure a kind of be restructural (hardware programmable) the array chip inner structure that the coarse particle degree elementary cell of core is formed with the cordic algorithm.And, Chinese patent application number is: 200610086398.0, name is called: reconstructable digital signal processor, this disclosure of the Invention a kind of reconstructable digital signal processor (DSP), the hardware resource of device inside can carry out structural rearrangement according to different application demands, can realize the filtering operation of various ways.But both do not make full use of the logic control ability of CPU, and towards extensive computing the time, it is the most efficient that its counting yield is difficult to reach.
Find by retrieval in addition: american documentation literature 2002/0056030A1, name is called: Shared Program Memory For use in Multicore DSP DEVICES (shared drive that is used for multi-core DSP equipment), proposition comprises the multi-core DSP of sharing the formula program storage, can reduce the power consumption expense.But do not relate to reconfigurable thought yet.And american documentation literature number 2008/0189514 A1, name is called: Reconfigurable Logic in Processors (the configurable reconfigurable logic unit in the processor) points out that processor inter-process unit can dispose the reconfigurable logic unit according to practical application.But when each processing unit was selected at a thread, by the control program configuration, this processor expense on efficiency based on SIMD was very big.
Summary of the invention
The present invention is directed to the prior art above shortcomings, a kind of multi-core DSP restructural special IC system is provided, on the basis of high-performance that keeps ASIC and low-power consumption, had characteristics such as Design of Programmable Logic Parts alterability and dirigibility again.This technology can combine well with the IP reuse technology of SoC, multi-core DSP restructural ASIC is to be core with DSP multinuclear array, simultaneously integrated IP modules such as steering logic, embedded memory and data-interface, thus can realize large-scale calculations flexibly, efficiently.
The present invention is achieved by the following technical solutions, the present invention includes: internal bus and be attached thereto the processor controls kernel that connects, the enhancement mode direct memory access, the input and output buffer memory, DSP multinuclear array, the configuration information buffer memory, reconfigurable logic unit and inner buffer, wherein: the processor controls kernel carries out data by internal bus, the transmission of address and control information, the enhancement mode direct memory access is by internal bus and inner buffer, the input and output buffer memory, DSP multinuclear array is connected and transmits the handled data message of DSP multinuclear array, DSP multinuclear array is by internal bus and configuration information buffer memory, reconfigurable logic unit is connected and transmission configuration and restructural information, and internal bus adopts based on multistage route and configurable reconfigurable direct-connected last mutual contact mode.
Described processor controls kernel comprises: two central processing units, interruptable controller, detecting control module, consistent interface, L2 cache, metadata cache and Instructions Caches, wherein: central processing unit is connected with metadata cache and transmits metadata cache information, central processing unit and instruction buffer memory is connected and the transfer instruction cache information, interruptable controller connects central processing unit and detects control module and transmit interrupting information, and L2 cache is connected with consistent interface and transmitting data information and command information.
Described DSP multinuclear array comprises: logical block and clock control circuit are examined, detected to number of digital signal processor, some dual ported register, restructural admittedly, wherein: digital signal processor is connected with detecting steering logic unit and transmits data and configuration information, dual ported register linking number word signal processor and restructural are examined admittedly and are transmitted data restructural information and endorse reconfiguration information admittedly, and clock control circuit is connected and the transfer clock control information with detecting steering logic unit, the solid nuclear phase of restructural.
Described reconfigurable logic unit is calculated acceleration components by the programmable logic block of coarseness structure or combination grain structure by wiring and enhancement mode and is linked to each other and form, wherein: enhancement mode is calculated the Float Point Unit FPU (Floating Point Unit) of acceleration components employing based on IEEE 754 standards, support adds, subtracts, multiplication and division, comparison operation, take the choice mode that rounds up, special denotation approach is arranged overflowing with illegal operation.The unit adopts conventional hardware anomalies mechanism, to overflow, divisor is 0, the handling unusually of illegal operation and abnormal operation number.
Described reconfigurable last mutual contact mode is meant: adopt adaptive route controlling mechanism, between multistage route, add configurable direct-connected, the equipment that connects for on-chip interconnect provides the low communication that postpones, and wherein: direct-connected foundation and dismounting realize by the technology of the dynamic reconfigurable of FPGA.
Compared with prior art, the device of system's formation of the present invention's explanation has following beneficial effect:
The inside reconfigurable logic unit function of the similar FPGA of the present invention can be dynamically heavily loaded in the ASIC operational process, makes the flexible change that can realize topology between many DSP in the sheet to adapt to the demand of various parallel algorithms, makes algorithm carry out efficient near the highest." many DSP+FPGA+ examine admittedly " structure of system can be divided into system task lower layer signal processing and the preprocessing part that is fit to the FPGA processing and be fit to the mass data calculating section that DSP handles, and is convenient to bring into play both advantages.This structure has good management and running ability of CPU and the powerful digital signal processing capability of DSP simultaneously, can finish classical digital signal processing algorithm and a series of problems such as the definite function that need expand and characteristic simultaneously.Utilize by simplifying the saved resources of chip of cpu function, design and Implement the function that some large-scale data computing aspects need be strengthened.
Description of drawings
Fig. 1 is a structural representation of the present invention.
Fig. 2 is a processor controls kernel synoptic diagram.
Fig. 3 is a DSP multinuclear array synoptic diagram.
Embodiment
Below embodiments of the invention are elaborated, present embodiment is being to implement under the prerequisite with the technical solution of the present invention, provided detailed embodiment and concrete operating process, but protection scope of the present invention is not limited to following embodiment.
As shown in Figure 1, present embodiment comprises: processor controls kernel 1, enhancement mode direct memory access 2, input and output buffer memory 3, DSP multinuclear array 4, configuration information buffer memory 5, reconfigurable logic unit 6, inner buffer 7 and internal bus 8, wherein: processor controls kernel 1 is connected by each module of internal bus 8 and other and transmits data, address and control information, enhancement mode direct memory access 2 is by internal bus 8 and inner buffer 7, input and output buffer memory 3, DSP multinuclear array 4 is connected and transmits the handled data message of DSP multinuclear array, and DSP multinuclear array 4 is gone up mutual contact mode and configuration information buffer memory 5 by reconfigurable, reconfigurable logic unit 6 is connected and transmission configuration and restructural information.
As shown in Figure 2, described processor controls kernel 1 comprises: two central processing units 9,10, interruptable controller 11, detecting control module 12, consistent interface 13, L2 cache 14, metadata cache 15,16 and Instructions Cache 17,18, wherein: central processing unit 9,10 with metadata cache 15,16 are connected and transmit metadata cache information, central processing unit 9,10 and instruction buffer memorys 17,18 are connected and the transfer instruction cache information, interruptable controller 11 connects central processing unit 9,10 with detecting control module 12 and transmit interrupting information, L2 cache 14 be connected with consistent interface 13 also transmitting data information and command information.
Described central processing unit, in the present embodiment by the register parts, control assembly and arithmetic unit are formed, and are responsible for the scheduling and the logical operation of task in restructural special IC system, coordinate, control and the management total system.
Described interruptable controller is formed the interrupt source that management is outside by interrupt request register, interrupt mask register, interrupt service register, priority comparer and read-write steering logic in the present embodiment.
Described detecting logical block is made up of control register, status register and part control signal in the present embodiment, mainly realizes the cache consistance, and initialization L2 buffer memory.
Described consistent interface, be 32 from port, be used for managing the enhancement mode direct memory access.
Described L2 cache. in the present embodiment, the inner kernel of CPU has mutually independently L2 cache, data cached is that (being transmitted in CPU inside can realize the System Request Interface that relies on CPU built-in for system request interface, SRI) control synchronously.
Described metadata cache and Instructions Cache in the present embodiment, adopt data code Instruction Trace Cache design data buffer memory, reduce the requirement of CPU to the data buffer memory capacity; Adopt the dynamic tracking buffer memory to realize Instructions Cache, it directly links to each other with performance element and dynamic tracking engine, can find performed instruction to realize the realization of L1 buffer memory soon by the dynamic tracking engine.
As shown in Figure 3, described DSP multinuclear array 4 comprises: four digital signal processors 19,20,21,22, two dual ported register 23,24, restructural examines 25 admittedly, detecting logical block 26 and clock control circuit 27, wherein: digital signal processor 19,20,21,22 are connected with detecting steering logic unit 26 and transmit data and configuration information, dual ported register 23,24 linking number word signal processors 19,20,21,22 examine 25 and transmit data restructural information and endorse reconfiguration information admittedly admittedly with restructural, clock control circuit 27 with detect steering logic unit 26, restructural is examined 25 admittedly and is connected and the transfer clock control information.
Described digital signal processor adopts TMS320C64X in the present embodiment, have eight highly independently fixed-point multiplication arithmetic elements, the access structure that support does not line up, support 64 32 the one-level data cache of one-level program cache, 80KB of general-purpose register, 32KB and the secondary cache of 64KB, carry out the high-efficiency management and the coordination of multinuclear, the interconnected of many DSP can be realized topological restructural according to different executing the task.
Described dual ported register in the present embodiment, contains 4 32 general-purpose register, have one write the end and two read end.
Described restructural is examined admittedly in the present embodiment and is achieved by the programmable logic block of reconfigurable logic unit by coarseness structure or combination grain structure.
Described detecting logical block is made up of control register, status register and part control signal in the present embodiment, mainly realizes the cache consistance, and initialization L2 buffer memory.
Described clock control circuit is realized by clock signal generator and starting or stopping control circuit in the present embodiment.
The framework of multi-core DSP restructural special IC system is responsible for task analysis, command assignment scheduling and a spot of serial computing for serving as the control core with the processor controls kernel; And concrete data computation such as the processing of large-scale data is packaged into the kernel program that is fit to High Performance DSP multinuclear array computation to task by processor controls, is handled by High Performance DSP multinuclear array.Both link to each other by high-speed internal bus, and respectively carry high-speed cache (Cache), realize obtaining fast data.
Reconfigurable high-order mutual contact mode is in twos adopted in data communication between DSP multinuclear array 4 and the reconfigurable logic unit 5, and DSP multinuclear array links to each other with solid vouching is first by reconfigurable dual ported register, to finish the transmission of information and data.The mutual contact mode of traditional register file as not solving the problem of access conflict, tends to cause data to make mistakes when multiple parallel is visited, thus among the present invention its registers in the register file to each solid nuclear.When work, DSP multinuclear array is by dual ported register and solid vouching reconfigurable linking to each other of unit, interconnected in twos by the reconfigurable high-order of dynamic adjustment, to realize DSP multinuclear array and the change of the mutual contact mode of vouching unit admittedly, to reduce bandwidth, increase arithmetic speed, reach high-effect computation purpose.Simultaneously, in the chip multi-core system, if mistake appears in certain nuclear, can by reconfigurable high-order in twos mutual contact mode with redundant nuclear it is replaced, perhaps directly it is directly turned off and isolates system, and keep the correct of systemic-function.Than the NoC that adopts the interconnected composition of distributed router, be difficult to adopt similar way to improve reliability, because single routing node mistake even may destroy the connectedness of whole network, and further cause the mistake of total system.Compare with existing high-order multistage interconnection network, reconfigurable high-order in twos mutual contact mode it have stronger reconfigurability and reliability.The present invention has protected reconfigurable high-order mutual contact mode in twos.
The purpose of parallel processing is to shorten the task executions time by adopting a plurality of processing units to handle input information simultaneously.By the Amdahl law as can be known: speed-up ratio and tasks in parallel degree and processing unit number are closely related.When relating to extensive computing, the tasks in parallel degree is often very high, be difficult to realize computing efficiently by single DSP kernel, so we have adopted High Performance DSP multinuclear array, when spending in the face of different tasks in parallel, topological structure by reconfigurable logic unit change DSP multinuclear array to reach most economical account form efficiently, has very strong versatility and adaptability with respect to conventional attachment system.
The hardware restructural of chip is realized by restructural resource (array) FPGA, requirement according to algorithms of different, mode by software-hardware synergism, processor controls is loaded into restructural information among restructural resource (array) FPGA by the configuration information buffer memory, and it can also realize that lower layer signal is handled and the pre-service of data simultaneously.
Claims (6)
1. multi-core DSP restructural special IC system, comprise: internal bus and be attached thereto the processor controls kernel that connects, the enhancement mode direct memory access, the input and output buffer memory, DSP multinuclear array, the configuration information buffer memory, reconfigurable logic unit and inner buffer, it is characterized in that: the processor controls kernel carries out data by internal bus, the transmission of address and control information, the enhancement mode direct memory access is by internal bus and inner buffer, the input and output buffer memory, DSP multinuclear array is connected and transmits the handled data message of DSP multinuclear array, and DSP multinuclear array is gone up mutual contact mode and configuration information buffer memory by reconfigurable, reconfigurable logic unit is connected and transmission configuration and restructural information.
2. multi-core DSP restructural special IC according to claim 1 system, it is characterized in that, described processor controls kernel comprises: two central processing units, interruptable controller, the detecting control module, consistent interface, L2 cache, metadata cache and Instructions Cache, wherein: central processing unit is connected with metadata cache and transmits metadata cache information, central processing unit and instruction buffer memory is connected and the transfer instruction cache information, interruptable controller connects central processing unit and detects control module and transmit interrupting information, and L2 cache is connected with consistent interface and transmitting data information and command information.
3. multi-core DSP restructural special IC according to claim 1 system, it is characterized in that, described DSP multinuclear array comprises: the number of digital signal processor, some dual ported register, restructural is examined admittedly, detecting logical block and clock control circuit, wherein: digital signal processor is connected with detecting steering logic unit and transmits data and configuration information, dual ported register linking number word signal processor and restructural are examined admittedly and are transmitted data restructural information and endorse reconfiguration information admittedly, clock control circuit and detecting steering logic unit, the solid nuclear phase of restructural connects and the transfer clock control information.
4. multi-core DSP restructural special IC according to claim 1 system, it is characterized in that, described reconfigurable logic unit is calculated acceleration components by the programmable logic block of coarseness structure or combination grain structure by wiring and enhancement mode and is linked to each other and form, and wherein: enhancement mode is calculated the Float Point Unit of acceleration components employing based on IEEE 754 standards.
5. multi-core DSP restructural special IC according to claim 1 system is characterized in that, described metadata cache and Instructions Cache are respectively data code Instruction Trace Cache design data buffer memory and the dynamic tracking buffer memory realizes that instruction is slow.
6. multi-core DSP restructural special IC according to claim 1 system, it is characterized in that, described reconfigurable last mutual contact mode is meant: adopt adaptive route controlling mechanism, between multistage route, add configurable direct-connected, the equipment that connects for on-chip interconnect provides the low communication that postpones, and wherein: direct-connected foundation and dismounting realize by the technology of the dynamic reconfigurable of FPGA.
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| CN110737628A (en) * | 2019-10-17 | 2020-01-31 | 辰芯科技有限公司 | reconfigurable processor and reconfigurable processor system |
| CN111506540A (en) * | 2020-04-24 | 2020-08-07 | 中国电子科技集团公司第五十八研究所 | Hardware programmable heterogeneous multi-core system on chip |
| CN111786894A (en) * | 2020-07-01 | 2020-10-16 | 无锡中微亿芯有限公司 | FPGA device for realizing on-chip network transmission bandwidth expansion function |
| CN111786894B (en) * | 2020-07-01 | 2021-08-10 | 无锡中微亿芯有限公司 | FPGA device for realizing on-chip network transmission bandwidth expansion function |
| US11750510B2 (en) | 2020-07-01 | 2023-09-05 | Wuxi Esiontech Co., Ltd. | FPGA device for implementing expansion of transmission bandwidth of network-on-chip |
| CN117270000A (en) * | 2023-11-20 | 2023-12-22 | 北京凯芯微科技有限公司 | GNSS navigation receiver and method for cross multiplexing tracking channels thereof |
| CN117270000B (en) * | 2023-11-20 | 2024-01-30 | 北京凯芯微科技有限公司 | GNSS navigation receiver and method for cross multiplexing tracking channels thereof |
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