WO2020052171A1

WO2020052171A1 - Hardware system and electronic device

Info

Publication number: WO2020052171A1
Application number: PCT/CN2018/124854
Authority: WO
Inventors: 李炜; 曹庆新; 黎立煌
Original assignee: 深圳云天励飞技术有限公司
Priority date: 2018-09-11
Filing date: 2018-12-28
Publication date: 2020-03-19
Also published as: CN110888675A; CN110888675B

Abstract

A hardware system and an electronic device. The hardware system (100) comprises: a central processing unit (110), a data memory (120), a buffer access element (130) and a task manager (140), wherein the central processing unit (110) is connected to the task manager (140) and the buffer access element (130); the data memory (120) is connected to the task manager (140) and the buffer access element (130); the central processing unit (110) is used for issuing at least one buffer access task to the task manager (140) and the buffer access element (130); the buffer access element (130) is used for executing the at least one buffer access task to access the data memory (120); and the task manager (140) is used for monitoring, based on the at least one buffer access task, the execution of the at least one buffer access task by the buffer access element (130). The hardware system and the electronic device facilitate the improvement of the operating efficiency of the hardware system and reduction of the interruption of the central processing unit.

Description

Hardware systems and electronics

This application claims priority from a Chinese patent application filed with the Chinese Patent Office on September 11, 2018, with an application number of 201811056568.X and an invention name of "Hardware System and Electronic Equipment", the entire contents of which are incorporated herein by reference .

Technical field

The present application relates to the field of computer technology, and in particular, to a hardware system and an electronic device.

Background technique

Generally speaking, if there is data exchange between multiple functional modules within a system, the traditional solution is generally carried out through a shared data cache. In the traditional solution, after a functional module needs to pass data to the shared data cache, it needs to interrupt the central processing unit, and then the central processing unit notifies the other functional module that the data is ready, so that another functional module can retrieve the data from the shared The data cache reads the data it needs.

However, in practice, it is found that the traditional scheme requires relatively constant interruption of the central processing unit, which makes the operating efficiency of the system relatively low.

Summary of the Invention

The embodiments of the present application provide a hardware system and an electronic device, so as to improve the operating efficiency of the hardware system and reduce the interruption of the central processing unit.

A first aspect of the present application provides a hardware system, including:

A hardware system, comprising: a central processing unit, a data buffer, a cache access unit, and a task manager;

Wherein, the central processing unit is connected to the task manager and the cache access unit;

The data buffer is connected to the task manager and the cache access unit;

The central processor is configured to deliver at least one cache access task to the task manager and the cache access unit;

The cache access unit is configured to execute the at least one cache access task to access the data buffer;

The task manager is configured to monitor the execution of the at least one cache access task by the cache access unit based on the at least one cache access task.

In some possible implementation manners, the at least one cache access task includes a cache access task T1 and a cache access task T0, and the cache access task T0 is a cache access task on which the cache access task T1 depends;

The task manager is specifically configured to, after receiving an access request q1 for the cache access task T1 from the cache access unit, determine whether to allow the response to the access request based on the completion of the cache access task T0 q1;

If it is determined that it is allowed to respond to the access request q1, the task manager sends an access response aq1 for responding to the access request q1 to the cache access unit, and the access response aq1 is used to indicate that the cache access unit is allowed to respond to the access request q1. The data buffer executes the cache access task T1.

In some possible implementation manners, when determining whether to allow response to the access request q1 based on the completion of the cache access task T0,

The task manager is specifically configured to: when the cache access task T0 is completed, determine to allow response to the access request q1; when the cache access task T0 is not completed, request the access requested by the cache access task T1 The cached pointer is compared with the current pointer of the cache access task T0. If the pointer comparison is passed, the judgment is allowed to respond to the access request q1; if the pointer comparison fails, the judgment is not allowed to respond to the access request q1 .

In some possible implementation manners, the data buffer includes a plurality of cache slices, and the cache access task T1 includes the following fields:

The first field to indicate the slice identification of the accessed cache slice, the second field to indicate the start address of the accessed cache slice, the third field to indicate the length of the accessed data, and the cache access task. T1 depends on the fields of the cache access task T0.

In some possible implementation manners, the access request q1 includes the following fields: the first field and a fourth field for indicating a unit identifier of a cache access unit that issued the access request q1;

or,

The access request q1 includes the following fields: the second field, the third field, and the fourth field;

Alternatively, the access request q1 includes the following fields: the second field, the third field, and a fifth field for indicating a task identifier of the cache access task T1.

In some possible implementation manners, the cache access unit includes the following access subunits: an external data reading subunit, an external data retrieval subunit, an internal data reading subunit, and an internal data retrieval subunit;

The hardware system further includes an external memory and an arithmetic unit;

Wherein, the external data reading subunit and the external data storing subunit are connected between the external memory and the data buffer; the internal data reading subunit and the internal data storing subunit are connected to all Said operation unit and said data buffer.

The external data reading subunit is configured to store data read from the external memory into the data buffer;

The external data return subunit is configured to store data read from the data buffer into the external memory;

The internal data reading subunit is configured to provide data read from the data buffer to the arithmetic unit for operation;

The internal data return subunit is configured to store result data obtained by the operation of the operation unit into the data buffer.

In some possible implementation manners, a central processing unit communicates with the task manager, the external data reading sub-unit, the external data storing sub-unit, the internal data reading sub-unit, and the internal unit through a bus. Data retrieval sub-unit connection;

The central processing unit is specifically configured to issue a cache access task of the external data reading subunit to the external data reading subunit through a bus; and issue an office to the external data return subunit. The cache access task of the external data return sub-unit; and the cache access task of the internal data return sub-unit is issued to the internal data return sub-unit, and an office is issued to the external data return sub-unit The cache access task of the external data reading and storing subunit; and delivering the external data reading subunit, the external data storing subunit, the internal data reading subunit, and the task manager to the task manager; A cache access task of the internal data return subunit.

In some possible implementation manners, the task manager includes: a cache access controller and a cache access task queue;

The cache access task queue is configured to store the external data reading subunit, the external data storing subunit, the internal data storing subunit, and the internal data issued by the central processing unit. Cache access tasks of sub-units;

Wherein, in the aspect of determining whether to allow response to the access request q1 based on the completion of the cache access task T0 on which the cache access task T1 depends, the cache access controller in the task manager is configured to:

When the cache access task T0 on which the cache access task T1 depends has been completed, it is judged that it is allowed to respond to the access request q1;

When the cache access task T0 is not completed, the pointer of the cache access task T1 requested to access the cache is compared with the current pointer of the cache access task T0. If the pointer comparison is passed, the decision is allowed to respond to the Access request q1; if the pointer comparison fails, it is determined that it is not allowed to respond to the access request q1.

In some possible implementation manners, the cache access task queue includes a first sub queue, a second sub queue, a third sub queue, and a fourth sub queue:

The first sub-queue is configured to store a cache access task of the external data reading sub-unit issued by the central processing unit;

The second sub-queue is configured to store a cache access task of the external data return sub-unit delivered by the central processing unit;

The third sub-queue is configured to store a cache access task of the internal data reading sub-unit issued by the central processing unit;

The fourth sub-queue is configured to store a cache access task of the internal data return sub-unit delivered by the central processing unit;

The cache access controller includes: a first sub-controller, a second sub-controller, a third sub-controller, and a fourth sub-controller:

The first sub-controller is a cache access controller of an external data reading sub-unit; the second sub-controller is a cache access controller of an external data return sub-unit; and the third sub-controller is internal data Read the cache access controller of the sub-unit; the fourth sub-controller is a cache access controller of the internal data return sub-unit.

A second aspect of the present application provides an electronic device including a casing and a hardware system housed in the casing, where the hardware system is any one of the hardware systems provided in the first aspect.

It can be seen that, in the above-mentioned hardware system, a task manager, which is different from a central processor, is introduced. The central processor is mainly used to deliver cache access tasks to the task manager and the cache access unit, and task management The processor is configured to monitor the execution of the at least one cache access task by the cache access unit based on the cache access task of the cache access unit. In other words, the execution of cache access tasks no longer requires the central processor to control through interrupts, but the task manager is responsible for managing the data buffer and scheduling the cache access unit, which is beneficial to reducing the central processor. Interruption. Since the execution of the cache access task can be completed automatically by other hardware (that is, the task manager) other than the CPU, the dedicated hardware outside the CPU (that is, the task manager that is different from the CPU) can be realized. Automatic management of data buffers and cache access units, compared to the traditional technology of central processing of data buffers by a central processor (in traditional technology, in addition to its main job, the central processor also needs to manage the data buffers) Access, then the management of the data buffer can be considered a part-time job of the central processor), the response speed of the dedicated hardware to manage the data buffer is relatively faster, which is more conducive to improving the utilization of the data buffer; and because By reducing the interruption of the central processing unit, the central processing unit can focus more on its own work related to the system operation, which is conducive to greatly improving the operating efficiency of the entire system.

Within the cache access unit, more subunits can be subdivided based on different access mechanisms. For example, when the cache access unit includes an external data read subunit, an external data return subunit, an internal data read subunit, and an internal data return subunit Units and other sub-units, the task manager can coordinate the data access work between these sub-units, which is conducive to improving the access efficiency of the data buffer and further improving the utilization of the data buffer.

BRIEF DESCRIPTION OF THE DRAWINGS

The drawings used in the description of the embodiments are briefly described below.

1-A is a schematic diagram of a hardware system architecture according to an embodiment of the present application;

1-B is a schematic diagram of another hardware system architecture according to an embodiment of the present application;

FIG. 1-C is a schematic diagram of another hardware system architecture according to an embodiment of the present application; FIG.

FIG. 1-D is a schematic diagram of another hardware system architecture according to an embodiment of the present application; FIG.

2 is a schematic diagram of a central processing unit according to an embodiment of the present application delivering a task to a task manager and each cache access unit through a task bus;

3 is a schematic diagram of an internal architecture of a task manager according to an embodiment of the present application;

4 is a schematic diagram of an internal architecture of another task manager according to an embodiment of the present application;

5 is a schematic flowchart of a processing method of a hardware system according to an embodiment of the present application;

6-A and 6-B are schematic diagrams of two data formats of a task provided by an embodiment of the present application;

7-A is a schematic diagram of a situation in which tasks are cached in each sub-queue in the task manager provided in the embodiment of the present application;

7-B is a schematic diagram of another situation of caching tasks in each sub-queue in the task manager provided in the embodiment of the present application;

FIG. 8 is a schematic diagram of an execution association relationship of some tasks provided by an embodiment of the present application.

detailed description

In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiment of the present application will be clearly and completely described with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiment is only Examples of this application are part, but not all. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art should fall within the protection scope of this application.

Each of them will be described in detail below. The terms "first", "second", "third", "fourth", and "fifth" in the description and claims of the present application and the above-mentioned drawings are used to distinguish different objects, and It is not used to describe a specific order. Furthermore, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that contains a series of steps or units is not limited to the listed steps or units, but optionally also includes steps or units not listed, or optionally also Include other steps or units inherent to these processes, methods, products, or equipment.

The embodiments of the present application strive to design a hardware system, which is conducive to reducing the interruption of the central processing unit and improving the operating efficiency of the hardware system.

Referring to FIG. 1-A, FIG. 1-A is a schematic diagram of a hardware system architecture provided by an embodiment of the present application. As shown in the example of FIG. 1-A, the hardware system 100 mainly includes a central processing unit 110, a data buffer 120, a cache access unit 130, and a task manager 140.

The central processing unit 110 is connected to the task manager 140 and the cache access unit 130.

The data buffer 120 is connected to the task manager 140 and the cache access unit 130.

The central processing unit 110 is configured to deliver at least one cache access task (for example, one cache access task or multiple cache access tasks) to the task manager 140 and the cache access unit 130.

The cache access unit 130 is configured to execute the at least one cache access task to access the data buffer 120.

The task manager 140 is configured to monitor the execution of the at least one cache access task by the cache access unit 130 based on at least one cache access task of the cache access unit 130.

It can be seen that the above solution introduces the task manager hardware into the hardware system. The central processor is mainly used to deliver cache access tasks to the task manager and the cache access unit, and the task manager is used to The cache access task of the cache access unit monitors the cache access unit 130 performing the at least one cache access task. In other words, the execution of cache access tasks no longer requires the central processor to control through interrupts, but the task manager is responsible for managing the data buffer and scheduling the cache access unit, which is beneficial to reducing the central processor. Interruption. Since the execution of the cache access task can be completed automatically by other hardware (that is, the task manager) other than the CPU, the dedicated hardware outside the CPU (that is, the task manager that is different from the CPU) can be realized. Automatic management of data buffers and cache access units, compared to the traditional technology of central processing of data buffers by a central processor (in traditional technology, in addition to its main job, the central processor also needs to manage the data buffers) Access, the management of the data buffer can be considered a part-time job of the central processor), the response speed of the dedicated hardware to manage the data buffer is relatively faster, which is more conducive to improving the utilization of the data buffer; With the interruption of the central processing unit, the central processing unit can focus more on its own work related to the system operation, which is conducive to greatly improving the operating efficiency of the entire system.

In some possible implementation manners, at least two components of the central processing unit 110, the data buffer 120, the cache access unit 130, and the task manager 140 may be connected through a bus. For example, the central processing unit 110, the data buffer 120, the cache access unit 130, and the task manager 140 are all connected through a bus.

Of course, in addition to the components shown in the example of FIG. 1-A, the hardware system 100 may further include some other components. For example, refer to FIG. 1-B, which is a schematic diagram of another hardware system architecture provided by an embodiment of the present application. As shown in the example of FIG. 1-B, the hardware system 100 may further include an operation unit 150. As shown in the example of FIG. 1-B, the cache access unit 130 may include the following access subunits: an internal data reading subunit 133 and an internal data return subunit 134. The internal data reading subunit 133 and the internal data returning subunit 133 are connected between the operation unit 150 and the data buffer 120.

The internal data reading subunit 133 may be configured to provide data read from the data buffer 120 to the operation unit 150 for operations. The internal data return sub-unit 134 may be configured to store the result data obtained by the operation unit 150 into the data buffer 120.

The operation unit 150 may include at least one operator unit, and the at least one operator unit may include, for example, at least one convolution operator unit, at least one addition operator unit, at least one subtraction operator unit, and / or at least one Other operator units, etc.

Referring to FIG. 1-C, FIG. 1-C is a schematic diagram of another hardware system architecture provided by an embodiment of the present application. As shown in the example of FIG. 1-C, the hardware system 100 may further include an external memory 160. As shown in the example of FIG. 1-C, the cache access unit 130 may include the following access subunits: an external data reading subunit 131 and an external data return subunit 132. The internal data reading subunit 131 and the internal data returning subunit 132 are connected between the external memory 160 and the data buffer 120.

The external data reading subunit 131 is configured to store data read from the external memory 160 into the data buffer 120. The external data return sub-unit 132 is configured to store data read from the data buffer 120 into the external memory 160.

Referring to FIG. 1-D, FIG. 1-D is a schematic diagram of still another hardware system architecture according to an embodiment of the present application. As shown in the example of FIG. 1-D, the hardware system 100 may include both the operation unit 150 and the external memory 160.

As shown in the example of FIG. 1-D, the cache access unit 130 may include the following access subunits: an external data read subunit 131, an external data readback subunit 132, an internal data read subunit 133, and an internal data readback subunit. 134. For a working mechanism of each access subunit in the cache access unit 130, refer to the foregoing example description.

Within the cache access unit, more sub-units can be subdivided based on different access mechanisms. For example, the cache access unit 130 includes an external data reading sub-unit 131, an external data return sub-unit 132, an internal data reading sub-unit 133, and an internal data return Storing the sub-units such as the sub-unit 134, the task manager 140 can coordinate the data access work between these sub-units, which is conducive to improving the access efficiency of the data buffer and further improving the utilization of the data buffer 120.

The external memory 160 is a memory relatively far from the computing unit 150, and the data buffer 120 is a memory relatively close to the computing unit 150. The external memory 120 may be, for example, an on-chip random access memory, an off-chip random access memory, and specifically may be a double data rate (SDRAM) synchronous dynamic random access memory (SDRAM) or other types of random access memories.

Among them, in some embodiments of the present application, the cache access unit may use dma (direct memory access) technology to perform access to related data.

The external data reading subunit 131 may be, for example, eidma (external input direct memory access), and the external data reading subunit 131 may read data in the external memory 160 into the data buffer 120.

The external data retrieval sub-unit 132 may be, for example, eodma (external output direct memory access), and the external data retrieval sub-unit 132 may store the data in the data buffer 120 into the external memory 160.

The internal data reading sub-unit 141 may be, for example, an idma (input direct memory access), and the internal data reading sub-unit 141 may read the data in the data buffer 120 to the arithmetic unit 150 for calculation.

The internal data return sub-unit 142 may be, for example, odma (output direct memory access), and the internal data return sub-unit 141 may return the operation result of the operation unit 150 to the data buffer 120.

The central processing unit 110 may include, for example, a central processing unit (CPU) or other processors, such as a digital signal processor (DSP), a microprocessor, a micro central processing unit, or a neural network calculator. In some specific applications, the components of the hardware system may be coupled together through a bus system, for example. The bus system may include a data bus, a power bus, a control bus, and a status signal bus. The central processing unit 110 may be an integrated circuit chip with signal processing capabilities. In some implementation processes, in addition to the unit executing software instructions, the central processing unit 110 may also include other hardware accelerators, such as an application-specific integrated circuit, a field programmable gate array or other programmable logic device, a discrete gate, or a transistor. Logic devices, discrete hardware components, etc.

The central processing unit 110 is, for example, configured to issue a task through a task bus (task_bus). The task manager 140 (task manager) performs management of the data buffer 120 and coordinated and synchronous management of each cache access unit.

Referring to FIG. 2, FIG. 2 is a schematic diagram of sending tasks by a central processing unit 110 to a task manager and various cache access units through a task bus (task_bus).

The following examples illustrate some possible ways for the task manager 140 to cooperatively manage the cache access unit to access the data buffer.

In some possible implementation manners, the task manager 140 may be configured to, after receiving an access request q1 for the cache access task T1 from the cache access unit, determine based on the completion of the cache access task T0 on which the cache access task T1 depends. Whether to respond to the access request q1. If it is determined that the access request q1 is allowed to be responded, an access response aq1 for responding to the access request q1 is sent to the cache access unit, and the access response aq1 is used to indicate that the cache access unit is allowed to respond to the data buffer The access request q1 is executed.

For example, in determining whether it is allowed to respond to the access request q1 based on the completion of the cache access task T1 on which the cache access task T1 depends, the task manager 140 may be configured to: when the cache access task T1 depends on the cache access task T0 If it is completed, it is judged that it is allowed to respond to the access request q1; when the cache access task T0 is not completed, the pointer to access the cache requested by the cache access task T1 and the current pointer of the cache access task T0 may be further performed Pointer comparison. If the pointer comparison passes, it is judged that the access request q1 is allowed to be responded; if the pointer comparison fails, it may be judged that the access request q1 is not allowed to be responded to.

Among them, the current pointer of the cache access task T0 lags behind the pointer requested by the cache access task T1 to indicate that the pointer has passed the comparison; when the current pointer of the cache access task T0 is not behind the pointer of the cache access task T1 requested to access the cache Indicates that the pointer comparison failed.

Among them, the cache access task T1 depends on the cache access task T0, which means that the execution of the cache access task T1 must depend on the execution of the cache access task T0, that is, the execution of the cache access task T1 is based on the successful execution of the cache access task T0. That is, after the cache access task T0 is successfully executed, the cache access task T1 can be executed.

For example, if the cache access task T1 is a read data buffer 120 (data memory) and the cache access task T0 is a write data buffer 120, then the data that the cache access task T1 wants to read from the data buffer 120 may be Some or all of the data written by the cache access task T0 to the data buffer 120. Only after the cache access task T0 is successfully executed, can the cache access task T1 read the corresponding data from the data buffer 120. If the cache access task T0 If it is not successfully executed, then the data buffer 120 does not have the data to be read by the cache access task T1, then the cache access task T1 cannot be successfully executed. In this case, the cache access task T1 depends on the cache access task T0.

The data buffer 120 may include multiple buffers.

In some possible implementation manners, the cache access task T1 may include the following fields: a field for indicating a slice ID (buffer ID) of the accessed cache slice, a field for indicating a start address of the accessed cache slice, and an instruction for indicating A field of the length of the accessed data, a field for indicating the cache access task T0 on which the cache access task T1 depends, and the like. It can be seen that the above-mentioned fields included in the cache access task are helpful for clearly indicating the corresponding cache access task, the cache location accessed, and the length of the cache space accessed.

In some possible implementation manners, the access request q1 may include the following fields: a field used to indicate a start address of the accessed cache slice, and a field used to indicate a unit identifier of a cache access unit that issued the access request q1;

Alternatively, the access request q1 may include the following fields: a field used to indicate the start address of the accessed cache slice, a field used to indicate the length of the accessed data, and used to indicate the cache access unit that issued the access request q1 Field of the unit identification;

Alternatively, the access request q1 may include the following fields: a field used to indicate the start address of the accessed cache slice, a field used to indicate the length of the accessed data, and used to indicate the task identifier of the cache access task T1. Field.

In some possible implementation manners, when the central processing unit 110 communicates with the task manager 140, the external data reading subunit 131, the external data storing subunit 132, the internal data reading subunit 133, and The internal data storage subunit 134 is connected. Then, the central processing unit 110 may be specifically configured to send a cache access task of the external data reading subunit 131 to the external data reading subunit 131 through a bus; and return the subdata to the external data. The unit 132 issues a cache access task of the external data retrieval subunit 132; and issues a cache access task of the internal data retrieval subunit 133 to the internal data retrieval subunit 133, and sends the cache access task to the external data retrieval subunit 133. The data retrieval subunit 134 issues a cache access task of the external data reading and retrieval subunit 134; and issues the external data reading subunit 131 and the external data retrieval to the task manager 140 A cache access task of the sub-unit 132, the internal data return sub-unit 133, and the internal data return sub-unit 134.

In some possible implementations, referring to FIG. 3, the task manager 140 may include a cache access controller 142 and a cache access task queue 141. The cache access task queue is configured to store the external data reading subunit, the external data storing subunit, the internal data storing subunit, and the internal data issued by the central processing unit. Cache access tasks for sub-units.

In terms of determining whether it is allowed to respond to the access request q1 based on the completion of the cache access task T1 on which the cache access task T1 is dependent, the cache access controller 142 in the task manager 140 may be used to: When the cache access task T0 on which the cache access task T1 depends is completed, it is determined to be allowed to respond to the access request q1; when the cache access task T0 is not completed, the pointer to access the cache requested by the access request q1 and the cache The current pointer of the access task T0 is compared with the pointer. If the pointer comparison is passed, the decision is allowed to respond to the access request q1; if the pointer comparison fails, the decision is not allowed to respond to the access request q1.

Referring to FIG. 4, FIG. 4 illustrates an example of a cache access task queue 141 and a cache access controller 142 included in the task manager 140.

Among them, the cache access task queue 141 includes a first sub-queue (such as eidma task queue), a second sub-queue (such as eodma task queue), a third sub-queue (such as idma task queue), and a fourth sub-queue (such as odma task task). queue). The first sub-queue is used to store a cache access task of the external data reading sub-unit issued by the central processing unit 110. The second sub-queue is configured to store a cache access task of the external data return sub-unit delivered by the central processing unit 110. The third sub-queue is used to store a cache access task of the internal data reading sub-unit issued by the central processing unit 110. The fourth sub-queue is used to store a cache access task of the internal data return sub-unit delivered by the central processing unit 110.

It can be understood that if the sub-queue is further divided inside the cache access task queue, so that different sub-queues store cache access tasks that need to be performed by different cache access subunits, then it will be easier to implement the classification management of cache access tasks and help simplify cache access. The read complexity of the task further improves the read efficiency of the cache access task.

The cache access controller 142 includes:

The first sub-controller (such as eidma cache access controller), the second sub-controller (such as eodma cache access controller), the third sub-controller (such as idma cache access controller), and the fourth sub-controller (such as odma Cache Access Controller). The first sub-controller is a cache access controller of the external data reading sub-unit. The second sub-controller is a cache access controller of an external data retrieval sub-unit; the third sub-controller is a cache access controller of an internal data reading sub-unit; and the fourth sub-controller is internal data Cache access controller to store subunits.

It can be seen that if each cache access unit is configured with a corresponding cache access sub-controller, it is more conducive to independent control of the cache access unit, and further facilitates the collaborative management and control of the data access unit.

The following describes some work processes of the hardware system with reference to the drawings.

Referring to FIG. 5, other working processes of the hardware system 100 are described below with reference to FIG. 5. The following describes the collaborative execution process of data access tasks to describe how the central processor and the task manager work together to complete the data access of the data buffer.

501. The central processing unit 110 sends tasks to the task manager 140, eodma 132, eidma 131, idma 133, and odma 134 through a task bus.

Among them, the tasks that access the data buffer 120 are stored in the respective buffer queues of the task manager 140. Among them, in one embodiment, only tasks that operate on the data buffer 120 and have a dependency relationship with each other are entered into the buffer queue in the task manager 140.

Among them, the tasks in the buffer task can indicate the following information:

The buffer ID of the accessed buffer (cache chip), the start address of the accessed buffer, the length of the accessed data, and the task on which the current task depends.

In addition, if the task that the current task depends on is reading data memory, the task can also indicate from which unit the input data of the current task comes from (can be called a data source unit). If the task write on which the current task depends is data memory, the task can also indicate to which unit the output data of the current task goes (for example, it can be called a data target unit).

See Figure 6-A and Figure 6-B. Figure 6-A and Figure 6-B illustrate two data formats for tasks. The task may include a bufferID field indicating the bufferID of the accessed buffer, an address field indicating the start address of the accessed buffer, a length field indicating the length of the accessed data, and a record of the task on which the current task depends. Depends on the task field, the data source unit field used to record the data source unit identification, or the data target unit field used to record the data target unit.

Assume that the central processor sends the task through task_bus as follows: eidma_task1: reads the data data001 from the external memory to the buf0 of the data buffer 120. idma_task1: read the data data001 written by eidma_task1 into buf0, and send the read data data001 to the arithmetic unit for calculation. odma_task1: The operation result data data002 obtained by operating the operation unit on data data001 is stored in buf1 of the data buffer 120. eodma_task1: Read the operation result data data002 stored in buf1 by odma task1, and store the read operation result data data002 into the external memory.

Referring to FIG. 7-A, FIG. 7-A illustrates an example of a task cached by each sub-queue of the cache access task for storing eodma, eidma, idma, and odma in the task manager.

Among them, eodma task queue is used to store the cache access task of eodma, and eidma task queue is used to store the cache access task of eidma. Among them, the idma task queue is used to store the cache access tasks for eodma, and the odma task queue is used to store the cache access tasks for eodma.

502. The eidma sends a memory request (task execution request) of the task eidma_task1 to the task manager.

503. The task manager receives a memory request for the task eidma_task1, the eidma cache access controller in the task manager reads the task eidma_task1 in the eidma task queue, and determines whether to respond to the memory request for the task eidma_task1.

Among them, if the task that the task eidma_task1 depends on has been completed, then it can respond to the memory request for the task eidma_task1. If the task that task eidma_task1 depends on has not been completed, then it does not respond to the memory request for task eidma_task1. If the current request fails to respond, the data memory controller can backpressure the corresponding unit that initiated the request. Among them, back pressure means to notify the corresponding unit that initiated the request to extend the tolerance time to wait for the corresponding response. For example, the normal time to wait for the corresponding response is 2 seconds, while back pressure can inform the corresponding unit that initiated the request to wait for the corresponding response The tolerance time is extended to 5 seconds or other periods of not less than two seconds.

Here, take the task that the task eidma_task1 depends on has been completed as an example. Then, the eidma cache access controller in the task manager can notify the data memory controller to respond to the memory request of the task eidma_task1, which can be specifically notified through the xxx_buf_rdy instruction.

504. The eidma131 reads the data to be processed data001 from the external memory 120 to the buf0 of the data buffer 120 according to the guide of the eidma_task1.

505. The task manager 140 notifies (for example, the xxx_buf_rdy instruction) that the IDMA reads the data data001 from the data buffer 120.

506. After receiving the notification from the task manager 140, idma133 reads the data data001 required for calculation to the computing unit 150. Correspondingly, the operation unit 150 performs an operation on the data data001 and obtains an operation result data002.

507. The odma 134 stores the operation result data002 obtained by the operation unit 150 on the data data001 into the buf1 of the data buffer 120.

508. The task manager 140 may notify the eodma 132 to read the data data002 from buf1 of the data buffer 120 and then save the data002 to the external memory 160.

509. When the task manager 140 instructs eodma132 to read the data data002 from the data buffer 120 and then save it to the external storage 160, then, eodma132 reads the data data002 from the data buffer 120 and then saves it to the external storage. 160.

It can be seen that in the above example process, the central processing unit assigns tasks to eidma, idma, odma, eodma, and task manager through the task bus (task_bus). eidma, idma, odma, and eodma will work according to the assigned task. Among them, task manager dynamically monitors each cache access unit (eidma, idma, odma, and eodma), and performs coordinated management of task execution of each access unit according to the issued task.

The above example is described by taking each unit in eidma, idma, odma, and eodma as an example for description. Of course, the central processing unit may also issue more tasks to them. For example, the tasks that the central processor gives each unit through task_bus can also be as follows:

eidma_task1: Read the initial data data001 stored in external memory to buf0 of data memory.

idma_task1: Read the data data001 written by eidma task1 into buf0, and send the read data001 to the process element for calculation.

odma_task1: The result data data002 obtained by the process element calculation data data001 is stored in buf1 of the data memory.

idma_task2: read the data 002 stored in buf1 by odma task1, and send the read data data002 to process element for calculation.

odma_task2: The result data data003 obtained by the process element calculation data data002 is stored in buf0 of the data memory.

idma_task3: Read the data data003 stored in buf0 by odma task2, and send the read data data003 to process element for calculation.

odma_task3: Result data data004 obtained by process element calculation data data003 is stored in buf1 of data memory.

eodma_task1: Read the data 004 stored in buf1 by odma task3, and store the data 004 read in external memory.

Referring to FIG. 7-B, FIG. 7-B illustrates another example of a task cached by each sub-queue of a cache access task for storing eodma, eidma, idma, and odma in task management.

Referring to FIG. 8, the execution association relationship of these tasks is illustrated in FIG. 8. The dotted arrows indicate the order in which tasks are performed.

In the example shown in FIG. 8, eidma_task1 is executed first. Eidma_task1 instructs to write data001 to buf0. After idma_task1 which depends on eidma_task1 is executed on eidma_task1, it instructs to read data001 from buf0 to the computing unit for calculation.

After odma_task1 is executed on idma_task1, odma_task1 indicates that data002 generated by calculating data001 is written to buf1. After idma_task2, which depends on odma_task1, is executed on odma_task1, it indicates that data002 is read from buf1 and calculated by the computing unit.

After odma_task2 is executed on idma_task2, odma_task2 instructs to write data003 resulting from the calculation of data002 to buf0. After idma_task3, which depends on odma_task2, is executed on odma_task2, it instructs to read data002 from buf1 for calculation by the computing unit.

After odma_task3 is executed on idma_task3, odma_task3 instructs to write data004 generated by calculating data003 to buf1. After eodma_task1 which depends on odma_task3 is executed on odma_task3, it instructs to read data004 from buf1 and store the read data data004 into external memory.

It can be understood that the tasks issued by the central processing 110 are various and are not limited to the above examples. For execution processes of other tasks, reference may be made to the example execution processes of the foregoing embodiments, and details are not described herein again.

As mentioned above, the above embodiments are only used to illustrate the technical solution of the present application, but not limited thereto. Although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those skilled in the art that: The technical solutions described in the foregoing embodiments are modified, or some technical features are equivalently replaced; and these modifications or replacements do not deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

A hardware system, comprising: a central processing unit, a data buffer, a cache access unit, and a task manager;

Wherein, the central processing unit is connected to the task manager and the cache access unit;

The data buffer is connected to the task manager and the cache access unit;

The central processor is configured to deliver at least one cache access task to the task manager and the cache access unit;

The cache access unit is configured to execute the at least one cache access task to access the data buffer;

The task manager is configured to monitor the execution of the at least one cache access task by the cache access unit based on the at least one cache access task.
The system according to claim 1, wherein the at least one cache access task comprises a cache access task T1 and a cache access task T0, and the cache access task T0 is a cache access task on which the cache access task T1 depends. ;

The task manager is specifically configured to, after receiving an access request q1 for the cache access task T1 from the cache access unit, determine whether to allow the response to the access request based on the completion of the cache access task T0 q1;

If it is determined that it is allowed to respond to the access request q1, the task manager sends an access response aq1 for responding to the access request q1 to the cache access unit, and the access response aq1 is used to indicate that the cache access unit is allowed to respond to the access request q1. The data buffer executes the cache access task T1.
The system according to claim 2, characterized in that, when determining whether to allow response to the access request q1 based on the completion of the cache access task T0,

The task manager is specifically configured to: when the cache access task T0 is completed, determine to allow response to the access request q1; when the cache access task T0 is not completed, request the access requested by the cache access task T1 The cached pointer is compared with the current pointer of the cache access task T0. If the pointer comparison is passed, the judgment is allowed to respond to the access request q1; if the pointer comparison fails, the judgment is not allowed to respond to the access request q1 .
The system according to claim 3, wherein the data buffer includes a plurality of cache slices, and the cache access task T1 includes the following fields:

The first field to indicate the slice identification of the accessed cache slice, the second field to indicate the start address of the accessed cache slice, the third field to indicate the length of the accessed data, and the cache access task. T1 depends on the fields of the cache access task T0.
The system according to claim 3 or 4, wherein the access request q1 includes the following fields: the first field and a fourth field for indicating a unit identifier of a cache access unit issuing the access request q1 ;

or,

The access request q1 includes the following fields: the second field, the third field, and the fourth field;

Alternatively, the access request q1 includes the following fields: the second field, the third field, and a fifth field for indicating a task identifier of the cache access task T1.
The system according to any one of claims 1 to 5, wherein the cache access unit comprises the following access subunits: an external data reading subunit, an external data storing subunit, an internal data reading subunit, and Internal data storage subunit;

The hardware system further includes an external memory and an arithmetic unit;

Wherein, the external data reading subunit and the external data storing subunit are connected between the external memory and the data buffer; the internal data reading subunit and the internal data storing subunit are connected to all Between the arithmetic unit and the data buffer;

The external data reading subunit is configured to store data read from the external memory into the data buffer;

The external data return subunit is configured to store data read from the data buffer into the external memory;

The internal data reading subunit is configured to provide data read from the data buffer to the arithmetic unit for operation;

The internal data return subunit is configured to store result data obtained by the operation of the operation unit into the data buffer.
The system according to claim 6, wherein the central processing unit communicates with the task manager, the external data reading subunit, the external data storing subunit, and the internal data reading through a bus. The sub-fetch unit is connected to the internal data storage sub-unit;

The central processing unit is specifically configured to issue a cache access task of the external data reading subunit to the external data reading subunit through a bus; and issue an office to the external data return subunit. The cache access task of the external data return sub-unit; and the cache access task of the internal data return sub-unit is issued to the internal data return sub-unit, and an office is issued to the external data return sub-unit The cache access task of the external data reading and storing subunit; and delivering the external data reading subunit, the external data storing subunit, the internal data reading subunit, and the task manager to the task manager; A cache access task of the internal data return subunit.
The system according to claim 5 or 6 or 7, characterized in that:

The task manager includes: a cache access controller and a cache access task queue;

The cache access task queue is configured to store the external data reading subunit, the external data storing subunit, the internal data storing subunit, and the internal data issued by the central processing unit. Cache access tasks of sub-units;

Wherein, in the aspect of determining whether to allow response to the access request q1 based on the completion of the cache access task T0 on which the cache access task T1 depends, the cache access controller is configured to:

When the cache access task T0 on which the cache access task T1 depends has been completed, it is judged that it is allowed to respond to the access request q1;

When the cache access task T0 is not completed, the pointer of the cache access task T1 requested to access the cache is compared with the current pointer of the cache access task T0. If the pointer comparison is passed, the decision is allowed to respond to the Access request q1; if the pointer comparison fails, it is determined that it is not allowed to respond to the access request q1.
The system according to claim 8, wherein the cache access task queue comprises a first sub-queue, a second sub-queue, a third sub-queue and a fourth sub-queue:

The first sub-queue is configured to store a cache access task of the external data reading sub-unit issued by the central processing unit;

The second sub-queue is configured to store a cache access task of the external data return sub-unit delivered by the central processing unit;

The third sub-queue is configured to store a cache access task of the internal data reading sub-unit issued by the central processing unit;

The fourth sub-queue is configured to store a cache access task of the internal data return sub-unit delivered by the central processing unit;

The cache access controller includes: a first sub-controller, a second sub-controller, a third sub-controller, and a fourth sub-controller:

The first sub-controller is a cache access controller of an external data reading sub-unit; the second sub-controller is a cache access controller of an external data return sub-unit; and the third sub-controller is internal data Read the cache access controller of the sub-unit; the fourth sub-controller is a cache access controller of the internal data return sub-unit.
An electronic device, comprising: a housing and a hardware system housed in the housing, the hardware system being the hardware system according to any one of claims 1 to 9.