CN109672524A - SM3 algorithm wheel iteration system and alternative manner based on coarseness reconstruction structure - Google Patents
SM3 algorithm wheel iteration system and alternative manner based on coarseness reconstruction structure Download PDFInfo
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- CN109672524A CN109672524A CN201811514910.6A CN201811514910A CN109672524A CN 109672524 A CN109672524 A CN 109672524A CN 201811514910 A CN201811514910 A CN 201811514910A CN 109672524 A CN109672524 A CN 109672524A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/08—Key distribution or management, e.g. generation, sharing or updating, of cryptographic keys or passwords
- H04L9/0861—Generation of secret information including derivation or calculation of cryptographic keys or passwords
- H04L9/0863—Generation of secret information including derivation or calculation of cryptographic keys or passwords involving passwords or one-time passwords
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/06—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols the encryption apparatus using shift registers or memories for block-wise or stream coding, e.g. DES systems or RC4; Hash functions; Pseudorandom sequence generators
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/06—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols the encryption apparatus using shift registers or memories for block-wise or stream coding, e.g. DES systems or RC4; Hash functions; Pseudorandom sequence generators
- H04L9/0618—Block ciphers, i.e. encrypting groups of characters of a plain text message using fixed encryption transformation
- H04L9/0625—Block ciphers, i.e. encrypting groups of characters of a plain text message using fixed encryption transformation with splitting of the data block into left and right halves, e.g. Feistel based algorithms, DES, FEAL, IDEA or KASUMI
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/06—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols the encryption apparatus using shift registers or memories for block-wise or stream coding, e.g. DES systems or RC4; Hash functions; Pseudorandom sequence generators
- H04L9/0643—Hash functions, e.g. MD5, SHA, HMAC or f9 MAC
Abstract
The present invention discloses a kind of SM3 algorithm wheel iteration system and alternative manner based on coarseness reconstruction structure, iteration system includes system bus, reconfigurable processor and microprocessor, reconfigurable processor includes configuration unit, input first-in first-out register group, output first-in first-out register group, general-purpose register and 4 reconfigurable arrays blocks, configuration unit incoming line is connect through system bus with microprocessor, and line outlet is connect with each reconfigurable arrays block；Input first-in first-out register group is connect through system bus with microprocessor；4 reconfigurable arrays blocks are connect with input/output first-in first-out register group, general-purpose register respectively；Data storage, reading and transmitting are carried out through general-purpose register between 4 reconfigurable arrays blocks；Output first-in first-out register group is connect through system bus with microprocessor.Such technical solution realizes the efficient operation of SM3 algorithm by improving while supporting certain flexibility to the degree of parallelism of DES algorithm and optimization assembly line etc..
Description
Technical field
The invention belongs to imbedded reconfigurable system regions, in particular to a kind of base applied to fields such as communication, encryptions
In extensive coarseness imbedded reconfigurable system and its processing method.
Background technique
General processor and specific integrated circuit (ASIC) are the two big mainstream sides in traditional Computer Systems Organization field
Method.However, the continuous improvement with application field to indexs demands such as the performances, energy consumption, Time To Market of system, both tradition
The drawbacks of calculating mode, is just exposed.
General processor method is applied widely, but computational efficiency is low, although calculating can be improved in specific integrated circuit
Speed and computational efficiency meet performance requirement, but the flexibility of ASIC device is very poor.
In order to realize tradeoff well, Reconfigurable Computation (reconfigurable between flexibility and computational efficiency
Computing) technology is come into being.Reconfigurable Computation is one of the development trend of current computer systems construction applications, it
Framework combines the two strong point between general processor and ASIC.It, can by configuring to restructural equipment
To be allowed to be converted into a dedicated hardware system by a general computing platform, to complete specific calculating task, quite
It is unfolded over time and space simultaneously in calculating task, shows the flexibility and very high calculated performance of application.In addition, can
Reconstruction calculations technology also has the advantages such as low system energy consumption, high reliablity, Time To Market be short.These advantages make Reconfigurable Computation
Technology has broad application prospects in each application field especially Embedded Application field.Much in built-in field
Mainstream applications, such as multimedia application, enciphering/deciphering application and communications applications etc. are all very suitable to utilize Reconfigurable Computing Technology
It realizes.Current Reconfigurable Computing Technology is patrolled mainly or for the computing platform in sophisticated technology field with restructural
Volume device cost gradually decreases, and Reconfigurable Computing Technology constantly improve when operation, we have reason to believe Reconfigurable Computing Technology
The all the advantages having can make it fully develop talents in more fields.
Multiple reconfigurable system, such as ReMAP, AsAP, DRP etc. are studied both at home and abroad at present.But these arrays is mutual
Connection mode is relatively simple, and a large amount of bit shift and more wheel number, therefore operation are needed in SM3 algorithm wheel interative computation
Efficiency and speed it is lower.Traditional restructurable computing system is asked in terms of the operation efficiency of SM3 and execution cycle there are larger
Topic.
Summary of the invention
The purpose of the present invention is to provide a kind of SM3 algorithm wheel iteration system based on coarseness reconstruction structure and repeatedly
Certain flexibility is being supported the advantages that independently can configure using the concurrency processing of Reconfiguration Technologies, computing module for method
While, the efficient operation of SM3 algorithm is realized to the methods of the degree of parallelism of DES algorithm and optimization assembly line by improving.
In order to achieve the above objectives, solution of the invention is:
A kind of SM3 algorithm wheel iteration system based on coarseness reconstruction structure, including system bus, reconfigurable processor
And microprocessor, wherein the reconfigurable processor includes configuration unit, input first-in first-out register group, the advanced elder generation of output
Register group, general-purpose register and 4 reconfigurable arrays blocks out, the incoming line of the configuration unit by system bus with it is micro-
Processor connection, and the line outlet of configuration unit is connect with each reconfigurable arrays block respectively；And the input first in first out is posted
Storage group is connect by system bus with microprocessor；4 reconfigurable arrays blocks connect with input first-in first-out register group respectively
It connects, while being connect respectively with output first-in first-out register group again, and this 4 reconfigurable arrays blocks connect with general-purpose register
It connects；Carry out the storage, reading and transmitting of data between 4 reconfigurable arrays blocks mutually by general-purpose register；The output
First-in first-out register group is connect by system bus with microprocessor；
The SM3 algorithm wheel iteration system includes 5M+1 configuration flow figures, microprocessor by analyze the feature of SM3 come
The operation process for determining wheel iteration, the configuration flow figure for the wheel interative computation more taken turns is launched into that a width data flow diagram is mapped to can
Configuration information is formed in reconfigurable processor is sent to configuration unit；Microprocessor sends clear data to can weigh by system bus
Structure processor, clear data be stored into input first-in first-out register group, microprocessor and by primary data, generation key and
The wheel iteration of next figure is used in the intermediate data deposit general-purpose register of calculating；The configuration unit is used for storage configuration
Information, and send configuration information to each reconfigurable arrays block.
A kind of alternative manner of the SM3 algorithm iteration system based on coarseness reconstruction structure, includes the following steps；
Step 1, the data flow diagram of SM3 method iteration is summarized；
Step 2, the data entry mode of SM3 is formulated；
Step 3, the data flow diagram that the data entry mode and step 1 determined according to step 2 determines, configures restructural place
Device is managed, and generates configuration information；
Step 4, configuration information and reconfigurable processor primary data are stored in by corresponding memory by microprocessor
In；
Step 5, microprocessor starts reconfigurable processor, and configuration information and pending data are sent to restructural place
Manage device；
Step 6, reconfigurable processor carries out data processing according to configuration information and pending data, works as reconfigurable processor
After completing current task, interrupt signal is sent；And the data handled well are sent to microprocessor by system bus.
After adopting the above scheme, the present invention is directed to SM3 algorithm iteration, includes multiple operations by 4 reconfigurable arrays blocks
Unit improves the operation degree of parallelism of SM3 algorithm by general-purpose register, will take turns iteration more and move parallel in reconfigurable processor
The mode of position replacement optimizes and accelerates, and while with natural activity, improves the operation efficiency of SM3 method, to the greatest extent may be used
It can ground reduction execution cycle.
Detailed description of the invention
Fig. 1 is of the invention based on extensive coarseness imbedded reconfigurable system processor block diagram；
Fig. 2 to Fig. 7 is SM3 algorithm iteration configuration flow figure of the present invention；
Fig. 8 is extension of message rule schematic diagram；
Fig. 9 is compression function rule schematic diagram；
Figure 10 is SM3 algorithm wheel iteration entirety flow graph.
Specific embodiment
Below with reference to attached drawing, technical solution of the present invention and beneficial effect are described in detail.
As shown in Figure 1, the present invention provides a kind of SM3 algorithm wheel iteration system based on coarseness reconstruction structure, including
System bus, reconfigurable processor and microprocessor, are introduced separately below.
The reconfigurable processor includes configuration unit, input first-in first-out register group, output first-in first-out register
The incoming line of group, general-purpose register, 4 reconfigurable arrays blocks, look-up tables, the configuration unit passes through system bus and Wei Chu
Device connection is managed, and the line outlet of configuration unit is connect with each reconfigurable arrays block respectively；And the input first in first out deposit
Device group is connect by system bus with microprocessor；This 4 reconfigurable arrays blocks are respectively the 1st reconfigurable arrays block, the 2nd
Reconfigurable arrays block, the 3rd reconfigurable arrays block and the 4th reconfigurable arrays block；Each reconfigurable arrays block and input
First-in first-out register group connection, while again with output first-in first-out register group connect, and this 4 reconfigurable arrays blocks with
General-purpose register connection；The storage of data is carried out mutually by general-purpose register between this 4 reconfigurable arrays blocks, is read
And transmitting；The output first-in first-out register group is connect by system bus with microprocessor；SM3 algorithm wheel iteration system
System includes 5M+1 configuration flow figures, in which:
Microprocessor determines the operation process of wheel iteration by analyzing the feature of SM3, by the wheel interative computation more taken turns
Configuration flow figure be launched into a width data flow diagram be mapped in reconfigurable processor formed configuration information be sent to configuration unit.It is micro-
Processor sends clear data to reconfigurable processor by system bus, and clear data is stored into input first-in first-out register
Group.Microprocessor will be simultaneously used for next in the intermediate data of primary data, the key of generation and calculating deposit general-purpose register
Open the wheel iteration of figure.
The configuration unit is used for storage configuration information, and sends configuration information to each reconfigurable arrays block.
For the 5p-4 configuration flow figure, 1≤p≤M；(5p-4) a configuration flow figure inputs advanced elder generation for obtaining
The configuration information of its corresponding configuration unit of the message data of register group with reading out；(5p-4) a configuration flow figure according to
Configuration information is stored in general-purpose register to the original communication data of reading；Original communication data is loaded into down according to configuration information
Operation in one configuration flow figure, for next configuration flow figure；
For the 5p-3 configuration flow figure, 1≤p≤M；(5p-3) a configuration flow figure is a for obtaining (5p-4)
The original communication data of the deposit general-purpose register of configuration flow figure, the configuration information for reading its corresponding configuration unit, it is complete
At extension of message iteration；Extension of message digital data in general-purpose register is read by the 1st read port operation row selector；Institute
It states (5p-3) a configuration flow figure and extension of message first stage iteration in SM3 algorithm is completed according to configuration information；
For the 5p-2 configuration flow figure, 1≤p≤M；(5p-2) a configuration flow figure is a for obtaining (5p-3)
The original communication data of the deposit general-purpose register of configuration flow figure, the configuration information for reading its corresponding configuration unit, it is complete
At extension of message iteration；Extension of message digital data in general-purpose register is read by the 1st read port operation row selector；Institute
It states (5p-2) a configuration flow figure and extension of message second stage iteration in SM3 algorithm is completed according to configuration information；
For the 5p-1 configuration flow figure, 1≤p≤M；For the 5p-1 configuration flow segment for obtaining (5p-
2) the extension of message word of a configuration flow figure generation, reading are stored in the cryptographic Hash of general-purpose register, its corresponding configuration list
The configuration information of member；The cryptographic Hash stored in general-purpose register is read by the 1st read port operation row selector；Described
5p-1 configuration flow figure according to configuration information to the extension of message word of (5p-2) a reconfigurable arrays block, initial Hash value into
Row compression function the 0th obtains the average information of this block iteration to the 15th iteration；
For the 5p configuration flow figure, 1≤p≤M；It is a for obtaining (5p-1) for the 5p configuration flow segment
The extension of message word of configuration flow figure generation reads the cryptographic Hash, its corresponding configuration unit for being stored in general-purpose register
Configuration information；The cryptographic Hash stored in general-purpose register is read by the 1st read port operation row selector；The 5p
Configuration flow figure compresses the extension of message word of (5p-2) a reconfigurable arrays block, initial Hash value according to configuration information
Function the 16th obtains the average information of this block iteration to the 63rd iteration；
Reconfigurable arrays block a for (5M+1) obtains the average information of the 5M configuration flow figure and reads its correspondence
Configuration unit configuration information；(5M+1) a configuration flow figure is according to configuration information in the 5M reconfigurable arrays block
Between information and initial Hash value exclusive or obtain Hash Value.
Preferably, the configuration unit includes the configuration that is connected in turn and control interface, configuration memory and match
Parsing module is set, and the configuration is connect with control interface and system bus；Microprocessor passes sequentially through system bus and configuration
Required configuration information is sent to configuration memory, the configuration that the configuration memory storage sends over control interface
Information, and Command Line Parsing module is used to parse the configuration information of configuration memory, and the configuration information of parsing is sent to and can be weighed
Structure array block realizes configuration, starting and handover operation to reconfigurable arrays block.
Preferably, the reconfigurable arrays block includes read port operation row selector, write port operation row selector and N
Row reconfigurable arrays operation row, and this N row reconfigurable arrays operation row shares read port operation row selector and write port operation
Row selector；Wherein, the read port operation row selector in m-th of configuration flow figure is denoted as m-th of read port operation row selection
Device, the write port operation row selector in m-th of configuration flow figure are denoted as m-th of write port operation row selector, m-th of configuration
Line n reconfigurable arrays operation row in flow chart is denoted asRow reconfigurable arrays operation row, m=1 ..., 5M+1, n=
1 ..., N, 5M+1 are the number of configuration flow figure, and N is the line number for the reconfigurable arrays operation row that reconfigurable arrays block includes, M, N
Round numbers；And be sequentially connected in order between the configuration flow figure, and the reconfigurable arrays inside each reconfigurable arrays block
It is sequentially connected in order between operation row；
There are general by write port operation row selector for the intermediate data that configuration flow figure operation obtains in wheel iteration
In register file, and the intermediate data that configuration flow figure operation needs in wheel iteration passes through read port operation row selector
Read the information stored in general-purpose register；
TheRow reconfigurable arrays operation row is connected with input first-in first-out register group, while theRow can weigh
Structure array operation row is connected with output first-in first-out register group, and reconfigurable arrays operation row can be read by general-purpose register
Various buffered datas and various interim eap-message digests, while initial Hash value can be written to general-purpose register, these
Cryptographic Hash is used for the calculating of subsequent compression function；
In (5p-4) a configuration flow figure, 1≤p≤M；TheRow reconfigurable arrays operation row inputs advanced elder generation
Message data in register group out reads the configuration information of configuration unit by the 1st read port operation row selector；TheRow reconfigurable arrays operation row leads directly to message data according to configuration information to obtain next reconfigurable arrays block wheel
The intermediate data of iteration；And this intermediate data is written in general-purpose register by the 1st write port operation row selector；
Configuration flow figure a for (5p-3), 1≤p≤M；In (5p-3) a configuration flow figureRow can
Restructuring array operation row is loaded into the intermediate data of (5p-4) a configuration flow figure from general-purpose register；Pass through the 1st simultaneously
Initial Hash value in a write port operation row selector write-in general-purpose register；It is read by read port operation row selector
The configuration information of configuration unit；(5p-3) a configuration flow figure is according to configuration information in (5p-4) a configuration flow figure
Between data carry out extension of message interative computation, obtain the intermediate data of (5p-4) a configuration flow figure, complete extension of message the
One stage, this intermediate data was written in general-purpose register by the 4th write port operation row selector, for it is next can
The iterative calculation of restructuring array block wheel；
Configuration flow figure a for (5p-2), 1≤p≤M；In (5p-2) a configuration flow figureRow can
Restructuring array operation row is loaded into the intermediate data of (5p-3) a configuration flow figure from general-purpose register；Pass through the 1st simultaneously
Initial Hash value in a write port operation row selector write-in general-purpose register；It is read by read port operation row selector
The configuration information of configuration unit；(5p-2) a configuration flow figure is according to configuration information in (5p-3) a configuration flow figure
Between data carry out extension of message interative computation, obtain the intermediate data of (5p-3) a configuration flow figure, complete extension of message the
Two-stage, this intermediate data was written in general-purpose register by the 2nd write port operation row selector, for it is next can
The iterative calculation of restructuring array block wheel；
Configuration flow figure a for (5p-1), 1≤p≤M；In (5p-1) a configuration flow figureRow can
Restructuring array operation row is loaded into the intermediate data of (5p-2) a configuration flow figure from general-purpose register；It is transported by read port
Calculate the configuration information that row selector reads configuration unit；(5p-1) a configuration flow figure is a to (5p-2) according to configuration information
The intermediate data of configuration flow figure carries out compression function interative computation, obtains the intermediate data of (5p-1) a configuration flow figure,
The 0 to 15th iteration of compression function is completed, general deposit is written by the 3rd write port operation row selector in this intermediate data
In device heap, iterated to calculate for next reconfigurable arrays block wheel；
For the 5p configuration flow figure, 1≤p≤M；In the 5p configuration flow figureRow reconfigurable arrays fortune
Calculate the intermediate data that row is loaded into the 5p configuration flow figure from general-purpose register；It is read by read port operation row selector
The configuration information of configuration unit；The 5p configuration flow figure is according to configuration information to the mediant of (5p-1) a configuration flow figure
According to compression function interative computation is carried out, the intermediate data of the 5p configuration flow figure is obtained, is completed compression function the 16 to 63rd time
This intermediate data is written in general-purpose register by the 3rd write port operation row selector, is used for next configuration by iteration
Flow chart calculates；
For the 5M+1 configuration flow figure, in the 5M+1 configuration flow figureRow reconfigurable arrays operation
Row is loaded into the intermediate data of the 5M configuration flow figure from general-purpose register；The 5M+1 reconfigurable arrays root tuber is according to configuration
Information obtains Hash Value to the average information and cryptographic Hash exclusive or of the 5M configuration flow figure.
Preferably, every row reconfigurable arrays operation row includes that X1 data are loaded into unit, X2 data outputting unit, X3
A 32 bit arithmetic unit；Each arithmetic element selects any three uplinks or current row using corresponding read port operation row selector
Other arithmetic element outputs are as its input；1 data of kth of m-th of configuration flow figure line n reconfigurable arrays operation row carry
Enter unit and is denoted asA data are loaded into unit, 2 numbers of kth of m-th of configuration flow figure line n reconfigurable arrays operation row
Is denoted as according to output unitA data outputting unit, the kth 3 of m-th of configuration flow figure line n reconfigurable arrays operation row
A arithmetic element is denoted asA arithmetic element, theThe output of a arithmetic element is denoted asA operation, k1=
1...X1, k2=1...X2, k3=1...X3, k4=1...X4, X1, X2, X3 and the equal round numbers of X4；M-th of read port operation row
The intermediate data for the previous step that selector is read and reception parse the configuration information of Command Line Parsing module to select intermediate data
The arithmetic element of inflow；
TheWithA data are loaded into unit and are loaded into input first-in first-out register group
In data, while parsing the configuration information of Command Line Parsing module；It is general being read by the 1st read port operation row selector
The information of storage in register file and the corresponding permutation network for being selected data to flow into according to the configuration information of parsing, this is set
Switching network isWithA arithmetic element；TheWithA data outputting unit keep in its corresponding WithA arithmetic logic unit
Result and read configuration information decision output data to output first-in first-out register group, next line reconfigurable arrays operation
Capable or general-purpose register；
TheA data are loaded into the configuration information of unit resolves Command Line Parsing module, are passing through the 2nd, 3 read port
Operation row selector reads the operation data information of the 5m configuration flow figure stored in general-purpose register, and according to parsing
Configuration information come the corresponding operation that selects data to flow into, theA arithmetic element carries out operation, and will
Output data keep in its correspondingOutput unit, and output data to output first-in first-out register group, next
Row reconfigurable arrays operation row or general-purpose register.
Preferably, in the arithmetic element include mould add operation, XOR operation, with operation, NAND operation, shift operation,
Straight-through output arithmetic operation；Each arithmetic element has most 3 inputs and most 2 outputs simultaneously, and wherein arithmetic element executes
While above-mentioned arithmetic operation, support an optional input as output.
Preferably, the number of the reconfigurable arrays block is 4, is connected in turn from beginning to end between each reconfigurable arrays block
Together, the number of general-purpose register is 1, and the number of input first-in first-out register group is 4, output first in first out deposit
The number of device group is 4.
Preferably, each reconfigurable arrays block includes 4 row reconfigurable arrays operation rows, 4 read port operation row selectors
With 4 write port operation row selectors；Every row reconfigurable arrays operation row includes that 4 data are loaded into unit, 4 data input lists
Member, 8 32 arithmetic operation units.
Preferably, the M is the block number that message data presses 512bit piecemeal.
The alternative manner for the SM3 algorithm iteration system based on coarseness reconstruction structure that the present invention also provides a kind of, including
Following steps；
Step 1, the calculation features of SM3 method iteration are analyzed, and summarize data flow diagram；
Step 2, according to the operation process in data flow diagram, the data entry mode of SM3 is formulated；
Step 3, the data flow diagram that the data entry mode and step 1 determined according to step 2 determines is directed to restructural place
The characteristics of managing device configures reconfigurable processor, and generates configuration information；
Step 4, configuration information and reconfigurable processor primary data are stored in by corresponding memory by microprocessor
In；
Step 5, microprocessor starts reconfigurable processor, and configuration information and pending data are sent to restructural place
Manage device；
Step 6, reconfigurable processor carries out data processing according to configuration information and pending data, works as reconfigurable processor
After completing current task, interrupt signal is sent；And the data handled well are sent to microprocessor by system bus.
Preferably, reconfigurable processor according to configuration information and pending data carries out the specific of data processing in step 6
Process is:
Step 61: theA data are loaded into unit, and 128bit is successively carried every time from input first-in first-out register group
Enter the message data of initial 512 bit；The configuration information of configuration unit is read by the 1st read port operation row selector；Root
Pass through the according to configuration informationA arithmetic logic unit selection direct mode operation passes through 512bit message dataNumber
Store according to output unit to general-purpose register, be denoted as W0, W1 ..., W16.
Step 62: configuration flow figure a for (5p-3), 1≤p≤M；Pass through (5p-3) a read port operation row choosing
The configuration information that device reads configuration unit is selected, (5p-3) a configuration flow figure reads message data Wj- in general-purpose register
3, Wj-5, Wj-6, Wj-8, Wj-9, Wj-11, Wj-12, Wj-13, Wj-16,0≤j < 68 and j are even number, theRow can weigh
In structure array operation rowA data are loaded into unit and are loaded into Wj-3, Wj-9, Wj-12, Wj-13, theA operation
Unit inputs Wj-3, and Wj-9 completes displacement and XOR operation,It is exportedThe
A arithmetic element inputWj-16 completes XOR operation,It is exportedTheA arithmetic element inputPermutation function P1 is completed,It obtains
OutputTheA arithmetic element input Wj-16 completes shift operation,Exported (Wj-16 < < < 7)；TheA arithmetic element inputWithXOR operation is completed,It is exported TheA arithmetic element is defeated
EnterWithXOR operation is completed,It is exportedTheIn row reconfigurable arrays operation rowA data are loaded into unit and are loaded into Wj-6, theA arithmetic element inputWithXOR operation is completed,It is exported And pass throughData outputting unit is stored in general-purpose register.
TheThe of row reconfigurable arrays operation rowA data are loaded into unit and are loaded into Wj-2, Wj-8, Wj-11,
Wj-12, theA arithmetic element inputs Wj-2, and Wj-8 completes displacement and XOR operation,It is exportedTheA arithmetic element inputWj-15 completes XOR operation,It obtains
OutputTheA arithmetic element inputPermutation function P1 is completed,It is exportedTheA arithmetic element input Wj-12 completes to move
Bit arithmetic,Exported (Wj-12 < < < 7)；TheA arithmetic element inputWithComplete exclusive or
Operation,Obtain output P1TheRow can
In restructuring array operation rowA arithmetic element inputWithXOR operation is completed,It obtains defeated
Out TheA data are loaded into unit and are loaded into
Wj-5, theA arithmetic element inputWithXOR operation is completed,It is exportedAnd pass throughData are defeated
Out in unit deposit general-purpose register；Step 62 is repeated until j=67.
Step 63: configuration flow figure a for (5p-2), 1≤p≤M；Pass through (5p-2) a read port operation row choosing
Select the configuration information that device reads configuration unit, message data in (5p-3) a reconfigurable arrays block reading general-purpose register
Wk-12, Wk-11, Wk-15, Wk-16,0≤k < 64 and k are even number.TheIn row reconfigurable arrays operation rowA data are loaded into unit and are loaded into Wk-16 and Wk-12, theA arithmetic element inputs Wk-16, and Wk-12 completes different
Or operation,It is exportedTheWithA arithmetic element is
It is straight-through,OutputAnd pass throughData outputting unit is stored in general-purpose register.
TheIn row reconfigurable arrays operation rowA data are loaded into unit and are loaded into Wk-15 and Wk-11,
TheA arithmetic element inputs Wk-15, and Wk-11 completes XOR operation,It is exportedTheA arithmetic element be it is straight-through,OutputAnd pass throughData outputting unit is stored in general-purpose register；Step 63 is repeated until k=63
Step 64: configuration flow figure a for (5p-1), 1≤p≤M；(5p-3) and (5p-2) a restructural battle array
Column block is written to extension of message word group in general-purpose register；In (5p-1) a reconfigurable arrays blockRow can weigh
In structure array operation rowA data are loaded into unit from the cryptographic Hash ADE and constant Tj in general-purpose register,
0≤j < 16；TheA arithmetic element be sequentially completed SS1 ← ((A < < < 12)+E+ ((Tj < < < j)) < < < 7,With SS2+D operation.
TheIn row reconfigurable arrays operation rowA data are loaded into unit from general-purpose register
Cryptographic Hash BC and extension of message word Wj and Wj', 0≤j < 16；TheA arithmetic element is sequentially completed Boolean function
FFj(A,B,C)、TT1←FFj(A,B,C)+D+SS2+Wj', B < < < 9, SS1+Wj operation, theA output unit is successively
It will export D '=C, C '=B < < < 9, in B '=A and A '=TT1 write-in general-purpose register at this block cryptographic Hash.
TheIn row reconfigurable arrays operation rowA data are loaded into unit from general-purpose register
Cryptographic Hash EFGH；TheA arithmetic element is sequentially completed Boolean function GGj (E, F, G), TT2 ← GGj (E, F, G)+H+
SS1+Wj leads directly to E, F, G operation.
TheIn row reconfigurable arrays operation rowA arithmetic element is sequentially completed Boolean function displacement letter
Number E ← P0 (TT2), F < < < 19 operations, theA output unit will successively export E '=E ← P0 (TT2), F '=E, G '
In=F < < < 19 and H '=G write-in general-purpose register at this block cryptographic Hash；Step 64 is repeated to j=15.
Step 65: for the 5p configuration flow figure, 1≤p≤M；(5p-3) and (5p-2) a reconfigurable arrays block
It is written to extension of message word group in general-purpose register；In the 5p reconfigurable arrays blockRow reconfigurable arrays operation
In rowA data are loaded into unit from the cryptographic Hash ADE and constant Tj, 16≤j < 64 in general-purpose register；TheA arithmetic element be sequentially completed SS1 ← ((A < < < 12)+E+ ((Tj < < < j)) < < < 7,
With SS2+D operation.
TheIn row reconfigurable arrays operation rowA data are loaded into unit from the Kazakhstan in general-purpose register
Uncommon value BC and extension of message word Wj and Wj', 16≤j < 64；TheA arithmetic element be sequentially completed Boolean function FFj (A,
B,C)、TT1←FFj(A,B,C)+D+SS2+Wj', B < < < 9, SS1+Wj operation, theA output unit will successively export D '
=C, C '=B < < < 9, B '=A and A '=TT1 are written in general-purpose register at this block cryptographic Hash.
TheIn row reconfigurable arrays operation rowA data are loaded into unit from the Kazakhstan in general-purpose register
Uncommon value EFGH；TheA arithmetic element is sequentially completed Boolean function GGi (E, F, G), TT2 ← GGj (E, F, G)+H+SS1+
Wj leads directly to E, F, G operation.
TheIn row reconfigurable arrays operation rowA arithmetic element is sequentially completed Boolean function permutation function E
← P0 (TT2), F < < < 19 operations, theA output unit will successively export E '=E ← P0 (TT2), and F '=E, G '=F < < <
In 19 and H '=G write-in general-purpose register at this block cryptographic Hash；Step 65 is repeated until j=63.
Step 66: for the 5M+1 configuration flow figure, the 5M+1 configuration flow figure reads the 5M configuration flow figure
And 5M-5 configuration flow figure is written in general-purpose register in the 5M+1 reconfigurable arrays block of cryptographic Hash
In row reconfigurable arrays operation rowA data are loaded into unit and general register are written from the 5M configuration flow figure
Cryptographic Hash ABCD in heap, theA arithmetic element is configured to direct mode operation；
TheIn row reconfigurable arrays operation rowIt is restructural from 5M-5 that a data are loaded into unit
Cryptographic Hash A ', B ', C ' and D ' in array block general-purpose register, theA arithmetic element is sequentially completedTheHash Value is sent into output first in, first out and posted by a data outputting unit
General-purpose register is written simultaneously in storage array；Step 66 is repeated to the identical operation of EFGH completion.
Preferably, the rule of the P0 in the step 62,63,64 and 65, P1 displacement is as follows:
P0 (X)=X ⊕ (X < < < 9) ⊕ (X < < < 17)
X is word in P1 (X)=X ⊕ (X < < < 15) ⊕ (X < < < 23) formula.
Boolean function FFi and GGi rule in the step 62,63,64 and 65 is as follows:
XYZ is word in formula.
Constant in the step 64 is as follows:
Indicate exclusive or, ∧ indicate with ,~indicate it is non-, | indicate or.
The above examples only illustrate the technical idea of the present invention, and this does not limit the scope of protection of the present invention, all
According to the technical idea provided by the invention, any changes made on the basis of the technical scheme each falls within the scope of the present invention
Within.
Claims (10)
1. a kind of SM3 algorithm wheel iteration system based on coarseness reconstruction structure, it is characterised in that: including system bus, can
Reconfigurable processor and microprocessor, wherein the reconfigurable processor include configuration unit, input first-in first-out register group,
First-in first-out register group, general-purpose register and 4 reconfigurable arrays blocks are exported, the incoming line of the configuration unit, which passes through, is
System bus is connect with microprocessor, and the line outlet of configuration unit is connect with each reconfigurable arrays block respectively；And the input
First-in first-out register group is connect by system bus with microprocessor；4 reconfigurable arrays blocks respectively with input first in first out
Register group connection, while again respectively with output first-in first-out register group connect, and this 4 reconfigurable arrays blocks with it is general
Register file connection；Carry out the storage, reading and biography of data between 4 reconfigurable arrays blocks mutually by general-purpose register
It passs；The output first-in first-out register group is connect by system bus with microprocessor；
The SM3 algorithm wheel iteration system includes 5M+1 configuration flow figures, and microprocessor is determined by analyzing the feature of SM3
Take turns iteration operation process, by the configuration flow figure for the wheel interative computation more taken turns be launched into a width data flow diagram be mapped to it is restructural
Configuration information is formed in processor is sent to configuration unit；Microprocessor sends clear data to restructural place by system bus
Manage device, clear data is stored into input first-in first-out register group, microprocessor and by primary data, the key of generation and calculating
Intermediate data deposit general-purpose register in be used for next figure wheel iteration；The configuration unit is believed for storage configuration
Breath, and send configuration information to each reconfigurable arrays block.
2. the SM3 algorithm wheel iteration system based on coarseness reconstruction structure as described in claim 1, it is characterised in that: institute
Stating configuration unit includes the configuration and control interface, configuration memory and Command Line Parsing module being connected in turn, and described
Configuration is connect with control interface and system bus；Microprocessor passes sequentially through system bus and configuration will be required with control interface
Configuration information be sent to configuration memory, the configuration information that the configuration memory storage sends over, and Command Line Parsing mould
Block is used to parse the configuration information of configuration memory, and the configuration information of parsing is sent to reconfigurable arrays block.
3. the SM3 algorithm wheel iteration system based on coarseness reconstruction structure as described in claim 1, it is characterised in that: institute
Stating reconfigurable arrays block includes read port operation row selector, write port operation row selector and N row reconfigurable arrays operation
Row, and this N row reconfigurable arrays operation row shares read port operation row selector and write port operation row selector；Wherein, m
Read port operation row selector in a configuration flow figure is denoted as m-th of read port operation row selector, m-th of configuration flow figure
In write port operation row selector be denoted as m-th of write port operation row selector, the line n in m-th of configuration flow figure can
Restructuring array operation row is denoted asRow reconfigurable arrays operation row, m=1 ..., 5M+1, n=1 ..., N, 5M+1 are configuration
The number of flow chart, N are the line number for the reconfigurable arrays operation row that reconfigurable arrays block includes, M, N round numbers；And the configuration
Be sequentially connected in order between flow chart, and between the reconfigurable arrays operation row inside each reconfigurable arrays block in order according to
Secondary connection；The intermediate data that configuration flow figure operation obtains in wheel iteration is posted by write port operation row selector there are general
In storage heap, and the intermediate data that configuration flow figure operation needs in wheel iteration is read by read port operation row selector
Take the information stored in general-purpose register.
4. the SM3 algorithm wheel iteration system based on coarseness reconstruction structure as claimed in claim 3, it is characterised in that: institute
Stating every row reconfigurable arrays operation row includes that X1 data are loaded into unit, X2 data outputting unit and X3 32 bit arithmetic lists
Member, each arithmetic element select any three uplinks or the other arithmetic elements of current row using corresponding read port operation row selector
Output is as its input；1 data of kth of m-th of configuration flow figure line n reconfigurable arrays operation row are loaded into unit and are denoted as theA data are loaded into unit, 2 data outputting unit notes of kth of m-th of configuration flow figure line n reconfigurable arrays operation row
It isA data outputting unit, 3 arithmetic elements of kth of m-th of configuration flow figure line n reconfigurable arrays operation row
It is denoted asA arithmetic element, theThe output of a arithmetic element is denoted asA operation, k1=1...X1, k2
=1...X2, k3=1...X3, k4=1...X4, X1, X2, X3 and the equal round numbers of X4；M-th of read port operation row selector is read
The fortune that the intermediate data of the previous step taken and reception parse the configuration information of Command Line Parsing module intermediate data is selected to flow into
Calculate unit；
TheWithA data are loaded into unit and are loaded into input first-in first-out register group
Data, while parsing the configuration information of Command Line Parsing module；General deposit is being read by the 1st read port operation row selector
The information of storage in device heap and the corresponding permutation network for being selected data to flow into according to the configuration information of parsing, the replacement web
Network isWithA arithmetic element；TheWithIt is a
Data outputting unit keep in its corresponding WithThe result of a arithmetic logic unit is simultaneously
It reads configuration information decision and outputs data to output first-in first-out register group, next line reconfigurable arrays operation row or general
Register file；
TheA data are loaded into the configuration information of unit resolves Command Line Parsing module, are passing through the 2nd, 3 read port operation
Row selector reads the operation data information of the 5m configuration flow figure stored in general-purpose register, and matching according to parsing
The corresponding operation that confidence ceases to select data to flow into, theA arithmetic element carries out operation, and will output
Data keep in its correspondingOutput unit, and outputting data to output first-in first-out register group, next line can
Restructuring array operation row or general-purpose register.
5. the SM3 algorithm wheel iteration system based on coarseness reconstruction structure as claimed in claim 4, it is characterised in that: institute
Stating each reconfigurable arrays block includes 4 row reconfigurable arrays operation rows, 4 read port operation row selectors and 4 write port fortune
Row selector is calculated, every row reconfigurable arrays operation row includes that 4 data are loaded into unit, 4 data input cells and 8 32 fortune
Calculate unit.
6. a kind of alternative manner of the SM3 algorithm iteration system based on coarseness reconstruction structure, it is characterised in that including following
Step；
Step 1, the data flow diagram of SM3 method iteration is summarized；
Step 2, the data entry mode of SM3 is formulated；
Step 3, the data flow diagram that the data entry mode and step 1 determined according to step 2 determines, configures reconfigurable processing
Device, and generate configuration information；
Step 4, configuration information and reconfigurable processor primary data are stored in corresponding memory by microprocessor；
Step 5, microprocessor starts reconfigurable processor, and configuration information and pending data are sent to reconfigurable processing
Device；
Step 6, reconfigurable processor carries out data processing according to configuration information and pending data, when reconfigurable processor is completed
After current task, interrupt signal is sent；And the data handled well are sent to microprocessor by system bus.
7. the alternative manner of the SM3 algorithm wheel iteration system based on coarseness reconstruction structure as claimed in claim 6, special
Sign is: in the step 6, reconfigurable processor carries out the detailed process of data processing according to configuration information and pending data
It is:
Step 61: theA data are loaded into unit, and 128bit is successively loaded into just every time from input first-in first-out register group
Begin the message data of 512 bits；The configuration information of configuration unit is read by the 1st read port operation row selector；According to matching
Confidence breath passes through theA arithmetic logic unit selection direct mode operation passes through 512bit message dataData are defeated
Unit is stored to general-purpose register out, be denoted as W0, W1 ..., W16；
Step 62: configuration flow figure a for (5p-3), 1≤p≤M；Pass through (5p-3) a read port operation row selector
The configuration information of configuration unit is read, (5p-3) a configuration flow figure reads message data Wj-3, Wj- in general-purpose register
5, Wj-6, Wj-8, Wj-9, Wj-11, Wj-12, Wj-13, Wj-16,0≤j < 68 and j are even number, theThe restructural battle array of row
In column operations rowA data are loaded into unit and are loaded into Wj-3, Wj-9, Wj-12, Wj-13, theA arithmetic element
Wj-3 is inputted, Wj-9 completes displacement and XOR operation,It is exportedTheA fortune
Calculate unit inputWj-16 completes XOR operation,It is exportedTheA arithmetic element inputPermutation function P1 is completed,It is exportedTheA arithmetic element input Wj-16 completes shift operation,
Exported (Wj-16 < < < 7)；TheA arithmetic element inputWithXOR operation is completed,?
To output TheA arithmetic element inputWithXOR operation is completed,It is exportedTheIn row reconfigurable arrays operation rowA data are loaded into unit and are loaded into Wj-6, theA arithmetic element inputWithXOR operation is completed,It is exported And pass throughData outputting unit is stored in general-purpose register；
TheThe of row reconfigurable arrays operation rowA data are loaded into unit and are loaded into Wj-2, Wj-8, Wj-11, Wj-
12, theA arithmetic element inputs Wj-2, and Wj-8 completes displacement and XOR operation,It is exportedTheA arithmetic element inputWj-15 completes XOR operation,It obtains
OutputTheA arithmetic element inputPermutation function P1 is completed,It is exportedTheA arithmetic element input Wj-12 completes to move
Bit arithmetic,Exported (Wj-12 < < < 7)；TheA arithmetic element inputWithComplete exclusive or
Operation,It is exported TheRow can
In restructuring array operation rowA arithmetic element inputWithXOR operation is completed,It obtains defeated
Out TheA data are loaded into unit and are loaded into
Wj-5, theA arithmetic element inputWithXOR operation is completed,It is exportedAnd pass throughData are defeated
Out in unit deposit general-purpose register: repeating step 62 until j=67；
Step 63: configuration flow figure a for (5p-2), 1≤p≤M；Pass through (5p-2) a read port operation row selector
Read the configuration information of configuration unit, message data Wk- in (5p-3) a reconfigurable arrays block reading general-purpose register
12, Wk-11, Wk-15, Wk-16,0≤k < 64 and k are even number；TheIn row reconfigurable arrays operation row
A data are loaded into unit and are loaded into Wk-16 and Wk-12, theA arithmetic element inputs Wk-16, and Wk-12 completes XOR operation,It is exportedTheWithA arithmetic element be it is straight-through,OutputAnd pass throughData outputting unit is stored in general-purpose register；
TheIn row reconfigurable arrays operation rowA data are loaded into unit and are loaded into Wk-15 and Wk-11, theA arithmetic element inputs Wk-15, and Wk-11 completes XOR operation,It is exportedTheA arithmetic element be it is straight-through,OutputAnd pass throughData outputting unit is stored in general-purpose register；Step 63 is repeated until k=63；
Step 64: configuration flow figure a for (5p-1), 1≤p≤M；(5p-3) and (5p-2) a reconfigurable arrays block
It is written to extension of message word group in general-purpose register；In (5p-1) a reconfigurable arrays blockThe restructural battle array of row
In column operations rowA data are loaded into unit from the cryptographic Hash ADE and constant Tj, 0≤j in general-purpose register
< 16；TheA arithmetic element be sequentially completed SS1 ← ((A < < < 12)+E+ ((Tj < < < j)) < < < 7,With SS2+D operation；
TheIn row reconfigurable arrays operation rowA data are loaded into unit from the Hash in general-purpose register
Value BC and extension of message word Wj and W 'j, 0≤j < 16；TheA arithmetic element be sequentially completed Boolean function FFj (A, B,
C), TT1 ← FFj (A, B, C)+D+SS2+W 'j, B < < < 9, SS1+Wj operation, theA output unit will successively export D '
=C, C '=B < < < 9, B '=A and A '=TT1 are written in general-purpose register at this block cryptographic Hash；
TheIn row reconfigurable arrays operation rowA data are loaded into unit from the Hash in general-purpose register
Value EFGH；TheA arithmetic element is sequentially completed Boolean function GGj (E, F, G), TT2 ← GGj (E, F, G)+H+SS1+
Wj leads directly to E, F, G operation；
TheIn row reconfigurable arrays operation rowA arithmetic element is sequentially completed Boolean function permutation function E
← P0 (TT2), F < < < 19 operations, theA output unit will successively export E '=E ← P0 (TT2), and F '=E, G '=F <
In < < 19 and H '=G write-in general-purpose register at this block cryptographic Hash；Step 64 is repeated to j=15；
Step 65: for the 5p configuration flow figure, 1≤p≤M；(5p-3) and (5p-2) a reconfigurable arrays block write-in
The extension of message word group into general-purpose register；In the 5p reconfigurable arrays blockIn row reconfigurable arrays operation row
?A data are loaded into unit from the cryptographic Hash ADE and constant Tj, 16≤j < 64 in general-purpose register；The
A arithmetic element be sequentially completed SS1 ← ((A < < < 12)+E+ ((Tj < < < j)) < < < 7,And SS2
+ D operation；
TheIn row reconfigurable arrays operation rowA data are loaded into unit from the cryptographic Hash in general-purpose register
BC and extension of message word Wj and W 'j, 16≤j < 64；TheA arithmetic element be sequentially completed Boolean function FFj (A, B, C),
TTl ← FFj (A, B, C)+D+SS2+W 'j, B < < < 9, SSl+Wj operation, theA output unit will successively export D '=C, C '
=B < < < 9, B '=A and A '=TTl are written in general-purpose register at this block cryptographic Hash；
TheIn row reconfigurable arrays operation rowA data are loaded into unit from the cryptographic Hash in general-purpose register
EFGH；TheA arithmetic element is sequentially completed Boolean function GGi (E, F, G), TT2 ← GGj (E, F, G)+H+SS1+Wj, directly
Logical E, F, G operation；
TheIn row reconfigurable arrays operation rowA arithmetic element is sequentially completed Boolean function permutation function E ← P0
(TT2), F < < < 19 operations, theA output unit will successively export E '=E ← P0 (TT2), F '=E, G '=F < < < 19 Hes
In H '=G write-in general-purpose register at this block cryptographic Hash；Step 65 is repeated until j=63；
Step 66: for the 5M+1 configuration flow figure, the 5M+1 configuration flow figure read the 5M configuration flow figure and
5M-5 configuration flow figure is written in general-purpose register in the 5M+1 reconfigurable arrays block of cryptographic HashRow can
In restructuring array operation rowA data are loaded into unit from the 5M configuration flow figure write-in general-purpose register
Cryptographic Hash ABCD,A arithmetic element is configured to direct mode operation；
TheIn row reconfigurable arrays operation rowA data are loaded into unit from the 5M-5 reconfigurable arrays
Cryptographic Hash A ', B ', C ' and D ' in block general-purpose register, theA arithmetic element is sequentially completedTheHash Value is sent into output first in, first out and posted by a data outputting unit
General-purpose register is written simultaneously in storage array；Step 66 is repeated to the identical operation of EFGH completion.
8. the alternative manner of the SM3 algorithm wheel iteration system based on coarseness reconstruction structure as claimed in claim 7, special
Sign is: the rule of P0 displacement is as follows in P1 and step 64 in the step 62:
Wherein, X is word.
9. the alternative manner of the SM3 algorithm wheel iteration system based on coarseness reconstruction structure as claimed in claim 7, special
Sign is: Boolean function FFi and the GGi rule in the step 64 and step 65 is as follows:
Wherein, X, Y, Z are word.
10. the alternative manner of the SM3 algorithm wheel iteration system based on coarseness reconstruction structure as claimed in claim 7,
Be characterized in that: the constant in the step 64 is as follows:
Wherein,Indicate exclusive or, ∧ indicate with ,~indicate it is non-, | indicate or.
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