CN111190369A - Vibration controller based on ZYNQ - Google Patents

Vibration controller based on ZYNQ Download PDF

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Publication number
CN111190369A
CN111190369A CN202010014320.8A CN202010014320A CN111190369A CN 111190369 A CN111190369 A CN 111190369A CN 202010014320 A CN202010014320 A CN 202010014320A CN 111190369 A CN111190369 A CN 111190369A
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module
zynq
communication
fpga
vibration
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CN202010014320.8A
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徐佳
史治国
陈积明
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Zhejiang University ZJU
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Zhejiang University ZJU
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    • GPHYSICS
    • G05CONTROLLING; REGULATING
    • G05BCONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B19/00Programme-control systems
    • G05B19/02Programme-control systems electric
    • G05B19/04Programme control other than numerical control, i.e. in sequence controllers or logic controllers
    • G05B19/042Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
    • G05B19/0423Input/output
    • GPHYSICS
    • G05CONTROLLING; REGULATING
    • G05BCONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B2219/00Program-control systems
    • G05B2219/20Pc systems
    • G05B2219/24Pc safety
    • G05B2219/24215Scada supervisory control and data acquisition

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Automation & Control Theory (AREA)
  • Measurement Of Mechanical Vibrations Or Ultrasonic Waves (AREA)

Abstract

The invention discloses a vibration controller based on ZYNQ, which is used for connecting a vibration table to reproduce expected vibration control movement and distributing each link in vibration control to different processing modules for corresponding processing and calculation. The vibration controller adopts a ZYNQ chip as a main control unit, the ZYNQ chip is divided into an FPGA part and an ARM part, and the two parts realize interconnection communication through an AXI bus. The vibration controller comprises a data acquisition module, an analog signal output module, a mathematical computation module, a signal processing module, a data storage module and a communication and management module, wherein the signal processing module and the mathematical computation module have strong computation and digital signal processing capabilities. The vibration controller provided by the invention has high control efficiency, and can provide high-performance real-time calculation and convenient control function.

Description

Vibration controller based on ZYNQ
Technical Field
The invention relates to a vibration controller based on ZYNQ, belongs to the field of vibration instruments, and is used for vibration simulation experiments and reliability experiments.
Background
The vibration controller is a hardware controller used for connecting and controlling the vibration table and simulating vibration motion, and is applied to simulation of a real vibration environment and structural reliability test. By simulating the product or equipment in a vibration environment, the reliability and stability of the product can be checked, and the product can be improved and optimized.
In the vibration controller system, the controller uses ADC and the like to collect signals of an external sensor, and the external sensor comprises a displacement sensor, an acceleration sensor and the like; the controller outputs a control signal using the DAC, the control signal driving the vibration table through the power amplifier. The controller uses Ethernet interface and upper computer communication and control instruction and data transmission, and the upper computer is the application program running on the PC, and displays and provides the operation interface through UI interface.
In the existing equipment, a controller mainly takes a DSP or an industrial personal computer as a control core to complete data acquisition, signal processing, control calculation, drive output and data communication with an upper computer. Most of the existing controllers are executed in sequence, and do not have the capacity of multi-channel synchronous parallel calculation and analysis processing, the real-time calculation capacity and speed of a DSP controller/industrial personal computer are limited, and the multi-channel synchronization cannot be realized, so that the requirements of some high-speed tests cannot be met.
The vibration test needs real-time control and coordination among multiple channels, part of the test needs multi-channel high-frequency control, parallel acquisition, mathematical computation and drive output among the multiple channels, phase coordination among the multiple channels and the like, the controller needs to have parallel computation and processing capacity, ZYNQ has an ARM and FPGA structure.
Disclosure of Invention
Aiming at the defects in the prior art, the invention provides a vibration controller based on ZYNQ, the controller divides the system structure into two parts of software and hardware, the software and the hardware are coordinated and processed, the controller has very strong performance, can provide multi-channel real-time synchronous data acquisition and signal processing capability and accurate coordination processing capability among channels, provides parallel real-time low-delay efficient calculation, drives the output capability through multi-channel real-time synchronous control, is convenient for the software operation of an upper computer, and realizes high-speed remote communication through a gigabit Ethernet.
The purpose of the invention is realized by the following technical scheme: a vibration controller based on ZYNQ comprises a data acquisition module, an analog signal output module, a mathematical calculation module, a signal processing module, a data storage module and a communication and management module; the ZYNQ is used as a main control chip and divided into an ARM part and an FPGA part, wherein a mathematical computation module, a signal processing module and a dual-port BRAM part in a data storage module are positioned in the FPGA part, and a communication and management module is positioned in the ARM part;
the data acquisition module, the mathematical computation module and the analog signal output module realize closed-loop control through the coordination of a state machine; the signal processing module is used for filtering the signals acquired by the data acquisition module before the signals enter the mathematical computation module; the mathematical computation module and the communication and management module realize instruction and data interaction through an AXI bus and a dual-port BRAM in the data storage module; the communication and management module realizes Ethernet communication with an upper computer, register configuration of the mathematical computation module and upper layer coordination control of all the modules.
Furthermore, the data acquisition module mainly comprises an AD converter and two SSI protocol interfaces, wherein two differential filters and a differential program control amplification input channel and six analog signal direct input channels are arranged at the front end of the AD converter; and the data acquisition of the AD converter, the amplification factor selection of the programmable control amplifier and the SSI data acquisition control are completed in the FPGA.
Furthermore, the analog signal output module is provided with eight paths of DA converters and an output amplifier, wherein two paths of DA converters are respectively connected to one end of a differential end of two paths of differential filters and differential program control amplification in the data acquisition module to provide reference voltage input by the amplifier, and the other six paths of DA converters are directly used for external analog output; and the data output control of the DA converter is finished in the FPGA.
Further, the data storage module comprises an on-chip dual-port BRAM in the FPGA in the ZYNQ and an off-chip DDR3 used for the memory when the ARM program runs.
Further, the dual-port BRAM comprises a ref BRAM and a res BRAM, the ref BRAM is used for storing a reference waveform signal of a mathematical computation module in vibration control, and the ref BRAM is positioned between the communication and management module and the mathematical computation module; the res BRAM is used for storing signals collected by the data collection module in vibration control, and is positioned among the data collection module, the mathematical computation module and the communication and management module.
Furthermore, the mathematical computation module is used for processing the signals collected by the data acquisition module and filtered by the signal processing module and the reference waveform signals stored in the data storage module to obtain computation results, and transmitting the computation results to the analog signal output module for outputting and driving the vibration table to move; algorithms for performing mathematical calculations include a PID control algorithm and a three parameter control algorithm; and the mathematical computation module completes computation in the FPGA.
Furthermore, data interaction is realized between the mathematical computation module and the communication and management module through a resBRAM in the data storage module, the mathematical computation module writes the collected data into the res BRAM, and informs the communication and management module to read through an AXI bus in an interrupt signal mode and transmit the read data to an upper computer through an Ethernet; the communication and management module writes control instructions into the registers of the mathematical computation module via the AXI bus.
Further, the communication and management module is completed in an ARM, register configuration on the FPGA side is completed through an AXI bus, whether the FPGA completes task execution or not is obtained through interruption, the gigabit Ethernet is used for completing communication with an upper computer, and an experimental result is transmitted back to the upper computer in real time to be displayed.
Furthermore, the signal processing module adopts ZYNQ FPGA as a core processor, an IIR digital filter is used for completing filtering of collected signals, the IIR digital filter is realized by second order, filter coefficients are dynamically configured through an upper computer, the upper computer sends the filter coefficients to the communication and management module through the Ethernet, the communication and management module writes the filter coefficients into the signal processing module through an AXI bus, and the filter coefficients use signed fixed point numbers.
Furthermore, the ZYNQ main control chip adopts a Xilinx company integrated dual-core ARM Cortex-A9, 444k programmable logic unit, 26.5Mb Block RAM, a ZYNQ-7000 series SoC of 2020DSP Slice, the model is XC7Z100-2FFG900I, and the highest working main frequency is 1 GHz; the ZYNQ main control chip is divided into an ARM module and an FPGA module, and the two modules are communicated with each other through an AXI bus.
The invention has the beneficial effects that: the vibration controller adopts ZYNQ as a main control chip, a main controller of the vibration controller is divided into a software part and a hardware part, and the software and the hardware are cooperatively processed. The software part is an ARM processor which completes communication with an upper computer, issuing of controller instructions, upper-layer control of the system and the like. The hardware part is an FPGA and is used for finishing the acquisition, processing and calculation of signals and the driving output of the controller, and the FPGA hardware part is used for finishing the coordination control, parallel calculation and real-time signal processing among a plurality of channels of the whole system. Due to the parallelism and the real-time performance of the FPGA, functions which cannot be realized by some software and performance which cannot be realized by the FPGA can be finished, and the ARM is used for increasing the easiness in configuration and the easiness in operation of the system, so that the performance and the quality of the whole controller are improved by combining the FPGA with the ARM.
Drawings
FIG. 1 is a block diagram of a vibration controller system according to the present invention;
FIG. 2 is a control block diagram of the vibration controller system of the present invention;
FIG. 3 is a hardware schematic of the vibration controller of the present invention;
FIG. 4 is a system control block diagram of the present invention;
fig. 5 is a block diagram of the closed loop control of the present invention.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, but the present invention may be practiced in other ways than those specifically described and will be readily apparent to those of ordinary skill in the art without departing from the spirit of the present invention, and therefore the present invention is not limited to the specific embodiments disclosed below.
As shown in fig. 1 to 3, the vibration controller based on ZYNQ provided by the present invention includes a data acquisition module, an analog signal output module, a mathematical computation module, a signal processing module, a data storage module, and a communication and management module.
The communication and management module sends real-time feedback acquisition signals to an upper computer through Ethernet, the upper computer sends control instructions and reference waveforms (namely expected waveforms) to the ZYNQ communication and management module through the Ethernet, the communication and management module writes the control instructions into a register of the mathematical computation module through an AXI bus and writes the reference waveforms into a dual-port ref BRAM of the data storage module. The communication and management module is realized by software, is positioned in an ARM hard core in ZYNQ, plays the upper control function of the whole system, and performs register configuration, interrupt signal identification, process control and the like of a hardware FPGA part.
The data acquisition module selects an FPGA in ZYNQ as a core processor, and uses a logic circuit to complete data acquisition, as shown in FIG. 3, the data acquisition module externally connected with ZYNQ mainly comprises eight channels of analog signal input consisting of two ADS7825, wherein the two channels have a differential low-pass filter and a program control amplification function consisting of PGA204 and AD526, and the other six channels are directly connected to the ADS7825 for sampling. The data acquisition module also comprises two SSI signal acquisition channels consisting of two MAX 490.
The analog signal output module adopts an FPGA in ZYNQ as a core processor, and is externally connected with a DAC and an amplifier to complete analog signal output. As shown in FIG. 3, two external DAC7644 of ZYNQ realize the digital signal conversion to analog signal, wherein two DAC7644 have eight output channels, DAC7644 output voltage range is-2.5V- +2.5V, after DAC7644 outputs, each channel is connected with 4 times gain negative feedback amplifier composed of LM358, thus realizing the range of output analog signal is-10V- + 10V. The analog signal output by the amplifier needs to be converted from a voltage signal to a current signal, so that the servo valve is driven. The DAC7644 is controlled to drive an FPGA in the ZYNQ, and the DAC7644 is controlled by a logic circuit to control the output of the analog voltage.
As shown in fig. 4, a software and hardware system Block diagram in a main control chip ZYNQ is provided, wherein the main control chip ZYNQ adopts xlinx corporation integrated dual core ARM Cortex-a9, 444k programmable logic unit, 26.5Mb Block RAM, and ZYNQ-7000 series SoC of DSP 2020 Slice, and has a model of XC7Z100-2FFG900I and a highest working main frequency of 1 GHz; the ZYNQ chip is divided into ARM (PS) and FPGA (PL) modules, and the two modules are communicated with each other through an AXI bus.
The mathematical computation module adopts FPGA in ZYNQ as a core processor and uses a logic circuit to complete mathematical computation. As shown in fig. 5, the mathematical computation module is configured to process the signal collected by the data collection module and filtered by the signal processing module and the reference signal in the data storage module ref BRAM to obtain a computation result, and transmit the computation result to the analog signal output module for output to drive the vibration table to move; algorithms for performing mathematical calculation comprise a PID control algorithm and a three-parameter control algorithm, and which algorithm is used is selected through an upper computer; in addition, the mathematical computation module also transmits data to the communication and management module to be transmitted to an upper computer for display in real time; meanwhile, the mathematical computation module also receives a control instruction of the communication and management module, so that the control of the vibrating table is completed.
The data interaction between the mathematical computation module and the communication and management module is realized through a res BRAM in the data storage module, the mathematical computation module writes collected data into the res BRAM, and informs the communication and management module to read through an AXI bus in a signal interruption mode and transmit the data to an upper computer through an Ethernet. The communication and management module also writes control instructions into the registers of the math calculation module via the AXI bus.
The signal processing module adopts ZYNQ FPGA as a core processor and is used for finishing filtering of collected signals, an IIR digital filter is used for finishing filtering of the collected signals, the IIR filter is realized through a digital logic circuit, in order to enable the output delay of the filter to be small, the IIR digital filter is realized in a second order, the required cut-off frequency of the filter is different according to different application scenes, and the coefficient of the filter is also different, so that the coefficient of the filter is dynamically configured through an upper computer, the upper computer sends the coefficient of the filter to a communication and management module through Ethernet, the communication and management module writes the coefficient of the filter into the signal processing module through an AXI bus to change the parameters such as the cut-off frequency of the filter, and the like, so that the purpose of dynamically adjusting the parameters of the filter is achieved, and the.
The above embodiments are only used for illustrating the design idea and features of the present invention, and the purpose of the present invention is to enable those skilled in the art to understand the content of the present invention and implement the present invention accordingly, and the protection scope of the present invention is not limited to the above embodiments. Therefore, all equivalent changes and modifications made in accordance with the principles and concepts disclosed herein are intended to be included within the scope of the present invention.

Claims (10)

1. A vibration controller based on ZYNQ is characterized by comprising a data acquisition module, an analog signal output module, a mathematical calculation module, a signal processing module, a data storage module and a communication and management module; the ZYNQ is used as a main control chip and divided into an ARM part and an FPGA part, wherein a mathematical computation module, a signal processing module and a dual-port BRAM part in a data storage module are positioned in the FPGA part, and a communication and management module is positioned in the ARM part;
the data acquisition module, the mathematical computation module and the analog signal output module realize closed-loop control through the coordination of a state machine; the signal processing module is used for filtering the signals acquired by the data acquisition module before the signals enter the mathematical computation module; the mathematical computation module and the communication and management module realize instruction and data interaction through an AXI bus and a dual-port BRAM in the data storage module; the communication and management module realizes Ethernet communication with an upper computer, register configuration of the mathematical computation module and upper layer coordination control of all the modules.
2. The vibration controller based on ZYNQ as claimed in claim 1, wherein the data acquisition module mainly consists of an AD converter and two SSI protocol interfaces, and two differential filters plus differential program-controlled amplification input channels and six analog signal direct input channels are provided at the front end of the AD converter; and the data acquisition of the AD converter, the amplification factor selection of the programmable control amplifier and the SSI data acquisition control are completed in the FPGA.
3. The vibration controller based on ZYNQ as claimed in claim 2, wherein the analog signal output module is provided with eight DA converters and an output amplifier, two of them are respectively connected to one end of the differential end of the two differential filters plus differential program control amplification in the data acquisition module to provide a reference voltage for the input of the amplifier, and the other six are directly used for external analog output; and the data output control of the DA converter is finished in the FPGA.
4. The ZYNQ-based vibration controller of claim 1, wherein the data storage module includes an on-chip dual port BRAM within FPGA in ZYNQ and an off-chip DDR3 for memory when ARM program runs.
5. The ZYNQ-based vibration controller of claim 1 wherein said dual port BRAM includes a ref BRAM for storing a reference waveform signal of a mathematical computation block in vibration control and a res BRAM between the communication and management block and the mathematical computation block; the res BRAM is used for storing signals collected by the data collection module in vibration control, and is positioned among the data collection module, the mathematical computation module and the communication and management module.
6. The vibration controller based on ZYNQ of claim 1, wherein the mathematical computation module is used to process the signal collected by the data collection module and filtered by the signal processing module and the reference waveform signal stored in the data storage module to obtain the computation result, and transmit the computation result to the analog signal output module for outputting to drive the vibration table to move; algorithms for performing mathematical calculations include a PID control algorithm and a three parameter control algorithm; and the mathematical computation module completes computation in the FPGA.
7. The vibration controller based on ZYNQ of claim 1, wherein the mathematical computation module and the communication and management module realize data interaction through res BRAM in the data storage module, the mathematical computation module writes the collected data into res BRAM, and informs the communication and management module to read through AXI bus and transmit to the upper computer through ethernet in the form of interrupt signal; the communication and management module writes control instructions into the registers of the mathematical computation module via the AXI bus.
8. The vibration controller based on ZYNQ as claimed in claim 1, characterized in that the communication and management module is implemented in ARM, the register configuration on FPGA side is implemented through AXI bus, the interrupt is used to obtain whether FPGA completes the task execution, the gigabit Ethernet is used to complete the communication with the upper computer, and the experimental result is transmitted back to the upper computer in real time for displaying.
9. The vibration controller based on ZYNQ as claimed in claim 1, characterized in that the signal processing module adopts FPGA of ZYNQ as core processor, IIR digital filter is used to complete the filtering of the collected signal, IIR digital filter adopts second order realization, the filter coefficient is dynamically configured by upper computer, the upper computer sends the filter coefficient to the communication and management module through Ethernet, the communication and management module writes the filter coefficient into the signal processing module through AXI bus, the filter coefficient uses signed fixed point number.
10. The vibration controller based on ZYNQ as claimed in claim 1, characterized in that the ZYNQ main control chip adopts Xilinx corporation integrated dual core ARM Cortex-A9, 444k programmable logic unit, 26.5Mb Block RAM, ZYNQ-7000 series SoC of 2020DSP Slice, model is XC7Z100-2FFG900I, and highest working main frequency bit is 1 GHz; the ZYNQ main control chip is divided into an ARM module and an FPGA module, and the two modules are communicated with each other through an AXI bus.
CN202010014320.8A 2020-01-07 2020-01-07 Vibration controller based on ZYNQ Pending CN111190369A (en)

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113447859A (en) * 2021-06-24 2021-09-28 北京航空航天大学 Magnetic field measurement real-time reading method based on quantum effect
CN113541719A (en) * 2021-06-16 2021-10-22 北京无线电测量研究所 ZYNQ-based open type multi-channel digital transceiving component and method
CN114326496A (en) * 2021-12-24 2022-04-12 铜权科技(嘉兴)有限公司 High-speed data acquisition instrument and acquisition method thereof
CN114942022A (en) * 2022-07-25 2022-08-26 中国人民解放军国防科技大学 Bionic polarized light compass integrated design and navigation information real-time processing method
CN116448452A (en) * 2023-04-13 2023-07-18 北京工业大学 Human vibration monitoring system based on ZYNQ multisensor cooperation

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Cited By (9)

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Publication number Priority date Publication date Assignee Title
CN113541719A (en) * 2021-06-16 2021-10-22 北京无线电测量研究所 ZYNQ-based open type multi-channel digital transceiving component and method
CN113447859A (en) * 2021-06-24 2021-09-28 北京航空航天大学 Magnetic field measurement real-time reading method based on quantum effect
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CN114942022A (en) * 2022-07-25 2022-08-26 中国人民解放军国防科技大学 Bionic polarized light compass integrated design and navigation information real-time processing method
CN114942022B (en) * 2022-07-25 2022-10-21 中国人民解放军国防科技大学 Bionic polarized light compass integrated design and navigation information real-time processing method
CN116448452A (en) * 2023-04-13 2023-07-18 北京工业大学 Human vibration monitoring system based on ZYNQ multisensor cooperation
CN116448452B (en) * 2023-04-13 2024-05-03 北京工业大学 Human vibration monitoring system based on ZYNQ multisensor cooperation

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Application publication date: 20200522