CN114185603B - Control method of intelligent accelerator card, server and intelligent accelerator card - Google Patents

Control method of intelligent accelerator card, server and intelligent accelerator card Download PDF

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Publication number
CN114185603B
CN114185603B CN202111316053.0A CN202111316053A CN114185603B CN 114185603 B CN114185603 B CN 114185603B CN 202111316053 A CN202111316053 A CN 202111316053A CN 114185603 B CN114185603 B CN 114185603B
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Prior art keywords
card
accelerator card
starting mode
intelligent
server
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CN114185603A (en
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张映俊
李实秋
孙刘洋
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Jiangsu Yuntian Lifei Technology Co ltd
Shenzhen Intellifusion Technologies Co Ltd
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Jiangsu Yuntian Lifei Technology Co ltd
Shenzhen Intellifusion Technologies Co Ltd
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Priority to CN202111316053.0A priority Critical patent/CN114185603B/en
Publication of CN114185603A publication Critical patent/CN114185603A/en
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/4401—Bootstrapping
    • G06F9/4411—Configuring for operating with peripheral devices; Loading of device drivers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/24—Resetting means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/102—Program control for peripheral devices where the programme performs an interfacing function, e.g. device driver
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0026—PCI express

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Security & Cryptography (AREA)
  • Hardware Redundancy (AREA)

Abstract

The application provides a control method of an intelligent accelerator card, a server and the intelligent accelerator card, which relate to the technical field of information, can conveniently and effectively manage a plurality of intelligent accelerator cards, get rid of the limitation of hardware pins of the server, and ensure the reliability and stability of the intelligent accelerator card. The method comprises the following steps: acquiring card control information, wherein the card control information comprises a card control instruction and a card version file; a first starting mode switching instruction is sent to the intelligent accelerator card, and the intelligent accelerator card is instructed to switch the starting mode to the PCIE starting mode through a preset register; when detecting that PCIE bus communication is normal, executing a card control instruction, and sending a card version file to an intelligent accelerator card through a PCIE bus, wherein the intelligent accelerator card is in communication connection with a server through the PCIE bus; and sending a second starting mode switching instruction to a preset register of the intelligent accelerator card to instruct the intelligent accelerator card to switch the starting mode to the storage starting mode through the preset register.

Description

Control method of intelligent accelerator card, server and intelligent accelerator card
Technical Field
The present disclosure relates to the field of information technologies, and in particular, to a method for controlling an intelligent accelerator card, a server, and an intelligent accelerator card.
Background
With the rapid development of search engines, cloud computing, internet retail, web 2.0, mobile devices, network games, etc., network traffic has reached an unprecedented level. The intelligent accelerator card can be directly inserted into all commercial servers or network equipment (such as VPN, UTM, IDS, flow control, load balancing, firewall, security audit, public opinion monitoring, signaling monitoring and the like), provides 10 times of I/O performance, has lower cost and is widely applied.
While smart accelerator cards are used on servers such as commercial x86 servers, it is generally desirable to support multiple card insertion and use. However, when managing and controlling the independent board card, some support of additional hardware pins, i.e. General-purpose input/output (GPIO) interfaces, of the server is required, some support of a system management bus is required, some additional expansion and external chip addition are required for controlling, resulting in complicated management and control and higher management cost.
Disclosure of Invention
The embodiment of the application provides a control method and device of an intelligent accelerator card, a server and the intelligent accelerator card, which can conveniently and effectively manage a plurality of intelligent accelerator cards, get rid of the limitation of hardware pins of the server and ensure the reliability and stability of the intelligent accelerator card.
In a first aspect, the present application provides a method for controlling an intelligent accelerator card, which is applied to a server, including: acquiring card control information, wherein the card control information comprises a card control instruction and a card version file; a first starting mode switching instruction is sent to the intelligent accelerator card, and the first starting mode switching instruction is used for indicating the intelligent accelerator card to switch a starting mode to a PCIE starting mode through a preset register; when detecting that PCIE bus communication is normal, executing a card control instruction, and sending a card version file to an intelligent accelerator card through a PCIE bus, wherein the intelligent accelerator card is in communication connection with a server through the PCIE bus; and sending a second starting mode switching instruction to a preset register of the intelligent accelerator card, wherein the second starting mode switching instruction is used for indicating the intelligent accelerator card to switch the starting mode to the storage starting mode through the preset register.
In the embodiment of the application, after the server acquires the card control information, the server controls the preset register of the intelligent accelerator card to realize the switching of the starting mode, switches the starting mode of the intelligent accelerator card into the PCIE starting mode, executes the card control instruction in the mode, and simultaneously transmits the card version file with larger data to the intelligent accelerator card through the PCIE bus, so that the intelligent accelerator card can be applied to different servers without being limited by the hardware interface of the server, and can also effectively realize the control and the control of the intelligent accelerator card through the assistance of the server under the condition of not depending on the GPIO interface of the server or the system management bus, and the reliability and the stability of the control of the intelligent accelerator card are ensured.
Specifically, the address of the predetermined register in the PCIE bus domain is determined by the PCIE base address allocated to the smart accelerator card by the server and the inbound mapping from the PCIE bus domain to the bus protocol predetermined domain of the smart accelerator card.
Preferably, after sending the first start mode switching instruction to the smart accelerator card, the method further includes:
and sending a reset instruction to a first reset register of the intelligent accelerator card.
In the embodiment of the application, after the server sends the first starting mode switching instruction to the intelligent accelerator card, the reset operation of the intelligent accelerator card is realized through the first reset register, so that the intelligent accelerator card is ensured to be truly switched to the PCIE starting mode, the occurrence of the problems of abnormal interruption, dead halt and the like can be reduced in the process of the intelligent accelerator card swiping or upgrading, the smooth completion of the swiping or upgrading operation is ensured, and the reliability and the stability of the intelligent accelerator card control are improved.
Preferably, after sending the second start mode switching instruction to the predetermined register of the smart accelerator card, the method includes:
and sending a reset instruction to a first reset register of the intelligent accelerator card.
In the embodiment of the application, after the server sends the second starting mode switching instruction to the preset register of the intelligent accelerator card, the server sends the resetting instruction to the first resetting register of the intelligent accelerator card, so as to ensure that the intelligent accelerator card can work normally after the smart accelerator card is subjected to the machine-brushing operation, the starting mode of the intelligent accelerator card is switched to the storage starting mode, the situation that the intelligent accelerator card is actually only changed in the value of the switching mode and is not actually switched to the storage starting mode is avoided, normal service of the intelligent accelerator card is ensured, and the reliability and stability of the intelligent accelerator card control are improved.
Preferably, when the smart accelerator card is further communicatively connected to the server through a system management bus, after the first start mode switching instruction is sent to the smart accelerator card, the method further includes:
when detecting that PCIE bus communication is abnormal, sending a preset command to the intelligent accelerator card through a system management bus, wherein the preset command is used for indicating the intelligent accelerator card to switch a starting mode to a PCIE starting mode and recovering PCIE communication through a second reset register;
and when the starting mode of the intelligent accelerator card is searched to be switched to the PCIE starting mode and PCIE communication is recovered to be normal, executing the card control instruction and sending a card version file to the intelligent accelerator card through a PCIE bus.
According to the method and the device, the system management bus sends the preset command to the intelligent accelerator card so as to recover PCIE communication and switch the starting mode of the intelligent accelerator card to the PCIE starting mode, so that management and control of the intelligent accelerator card can be realized under the condition of abnormal PCIE communication, and stability and reliability of control of the intelligent accelerator card are improved.
In a second aspect, the present application provides another method for controlling a smart accelerator card, applied to the smart accelerator card, including: receiving a first starting mode switching instruction sent by a server, and indicating a preset register to switch a starting mode to a PCIE starting mode according to the first starting mode switching instruction, wherein the intelligent accelerator card and the server are in communication connection through a PCIE bus; the receiving server sends the card version file and stores the card version file; and receiving a second starting mode switching instruction sent by the server, and indicating a preset register to switch the starting mode to the storage starting mode according to the first starting mode switching instruction.
In a third aspect, the present application provides a control device of a smart accelerator card, applied to a server, including:
the information acquisition unit is used for acquiring card control information, wherein the card control information comprises a card control instruction and a card version file;
the first starting mode switching instruction sending unit is used for sending a first starting mode switching instruction to the intelligent accelerator card, and the first starting mode switching instruction is used for indicating the intelligent accelerator card to switch the starting mode to the PCIE starting mode through a preset register;
the first card control unit is used for executing a card control instruction when detecting that PCIE bus communication is normal, sending a card version file to the intelligent accelerator card through the PCIE bus, and connecting the intelligent accelerator card with the server through the PCIE bus communication;
the second starting mode switching instruction sending unit is used for sending a second starting mode switching instruction to a preset register of the intelligent accelerator card, and the second starting mode switching instruction is used for instructing the intelligent accelerator card to switch the starting mode to the storage starting mode through the preset register.
In a fourth aspect, the present application provides another control device for a smart accelerator card, applied to the smart accelerator card, including:
the first starting mode switching instruction receiving and processing unit is used for receiving a first starting mode switching instruction sent by the server and indicating a preset register to switch the starting mode to the PCIE starting mode according to the first starting mode switching instruction;
A first card version file receiving unit for receiving a card version file transmitted by the server and storing the card version file;
the second starting mode switching instruction receiving and processing unit is used for receiving a second starting mode switching instruction sent by the server and indicating a preset register to switch the starting mode to the storage starting mode according to the first starting mode switching instruction.
In a fifth aspect, the present application provides a server comprising a processor, a memory and a computer program stored in the memory and executable on the processor, the processor implementing the method according to the first aspect or any of the alternatives of the first aspect when executing the computer program.
In a sixth aspect, the present application provides a smart accelerator card comprising a processor, a memory and a computer program stored in the memory and executable on the processor, the processor implementing the method according to the second aspect or any alternative of the second aspect when executing the computer program.
In a seventh aspect, the present application provides a computer readable storage medium storing a computer program which when executed by a processor implements a method as described in the first aspect, any optional manner of the first aspect, the second aspect or any optional manner of the second aspect.
In an eighth aspect, embodiments of the present application provide a computer program product, which when executed on a control device of a smart accelerator card, causes a server to perform the steps of the control method of a smart accelerator card described in the first aspect, or causes a smart accelerator card to perform the steps of the control method of a smart accelerator card described in the second aspect.
It will be appreciated that the advantages of the second to eighth aspects may be found in the relevant description of the first aspect, and are not repeated here.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required for the embodiments or the description of the prior art will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a flow chart of a control method of a smart accelerator card according to an embodiment of the present application;
FIG. 2 is an interactive schematic diagram of a smart accelerator card control provided in an embodiment of the present application;
FIG. 3 is a flowchart of another method for controlling a smart accelerator card according to an embodiment of the present disclosure;
fig. 4 is a flow chart of another control method of the smart accelerator card according to the embodiment of the present application;
FIG. 5 is an interactive schematic diagram of control of another smart accelerator card provided by an embodiment of the present application;
FIG. 6 is a flowchart of another method for controlling a smart accelerator card according to an embodiment of the present disclosure;
fig. 7 is a schematic structural diagram of a control device of a smart accelerator card according to an embodiment of the present application;
fig. 8 is a schematic structural diagram of a control device of a smart accelerator card according to an embodiment of the present application;
fig. 9 is a schematic structural diagram of a server according to an embodiment of the present application;
fig. 10 is a schematic structural diagram of a smart accelerator card according to an embodiment of the present application.
Detailed Description
In the following description, for purposes of explanation and not limitation, specific details are set forth, such as particular system configurations, techniques, etc. in order to provide a thorough understanding of the embodiments of the present application. It will be apparent, however, to one skilled in the art that the present application may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present application with unnecessary detail.
It should be understood that the term "and/or" as used in this specification and the appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes such combinations. In addition, in the description of the present application and the appended claims, the terms "first," "second," "third," and the like are used merely to distinguish between descriptions and are not to be construed as indicating or implying relative importance.
It should also be appreciated that references to "one embodiment" or "some embodiments" or the like described in this specification mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in one or more embodiments of the present application. Thus, appearances of the phrases "in one embodiment," "in some embodiments," "in other embodiments," and the like in the specification are not necessarily all referring to the same embodiment, but mean "one or more but not all embodiments" unless expressly specified otherwise. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless expressly specified otherwise.
Example 1
The server mentioned in the first embodiment is a system without an embedded management microcontroller, and has no redundant GPIO interface and smart accelerator card for connection and control, and only has a high-speed serial computer expansion bus standard (peripheral component interconnect express, PCIE) interface. In this case, if the server needs to support the adaptation of multiple smart accelerator cards, it is difficult for the user to perform independent management control such as machine-brushing, upgrading, exception management, etc. on the multiple smart accelerator cards later.
By the control method of the intelligent accelerator card, the limit of the number of the GPIO interfaces of the server is not relied on, and any one or more intelligent accelerator cards in the plurality of intelligent accelerator cards can be controlled, such as machine swiping and upgrading, at the server side.
In the embodiment of the application, in order to realize the access of the server to the smart accelerator card, a predetermined register pcie_host_bootmode is provided in the smart accelerator card, where an address of the predetermined register in a PCIE bus domain is allocated to a PCIE base address of the smart accelerator card by the server, and an inbound bound mapping of a bus protocol of the PCIE bus domain to the smart accelerator card, such as (Advanced eXtensible Interface, AXI) domain, is determined together, for example, the predetermined register is configured to be mapped to a predetermined space, such as a PCIE BAR0 space, so that the predetermined register can be accessed by the server HOST.
In some embodiments of the present application, an address mapping module is disposed in the smart accelerator card, where the address mapping module is configured to set address mapping from a PCIE bus domain address to a predetermined domain of the smart accelerator card, such as an AXI domain. A first RESET register pcie_hot_reset is configured on the address domain of the predetermined domain, and through the first RESET register pcie_hot_reset, the startup mode of the intelligent accelerator card may be switched to a PCIE startup mode or a storage startup mode, so as to implement control over the intelligent accelerator card.
In the embodiment of the application, the server can initiate the reset action by accessing the interface to operate the first reset register, and the reset operation of the intelligent accelerator card is realized through the initiated reset action.
When the inbound mapping is configured, the PCIE bus domain address of the predetermined register may be determined according to the configured inbound mapping.
Specifically, after the device driver of the smart accelerator card maps the PCIE bus domain address of the predetermined register to the CPU virtual address space, the smart accelerator card may be accessed by the server through an access interface provided by the smart accelerator card.
Referring to fig. 1 and fig. 2, fig. 1 is a flow chart of a control method of an intelligent accelerator card according to an embodiment of the present application, where the method is applied to a server; fig. 2 is an interaction schematic diagram of control of the smart accelerator card provided in the embodiment of the present application, and a detailed description of a control method of the smart accelerator card provided in fig. 1 is described with reference to fig. 2, which is specifically as follows:
Step S101, card control information is acquired, where the card control information includes a card control instruction and a card version file.
In the embodiment of the application, the card control information is used for instructing the server to manage and control any one or more of a plurality of smart accelerator cards, including but not limited to smart accelerator card swiping, smart accelerator card upgrading, smart accelerator card abnormality management and the like.
The card control information comprises a card control instruction and a card version file, and the card control instruction comprises a machine-swiping instruction, an upgrading instruction, an abnormal recovery instruction and the like. The card version file includes a swipe version file, an upgrade version file, and the like.
In order to confirm which smart accelerator card is managed and controlled, the card control information further includes a card identifier of the smart accelerator card, which may be a device address of the smart accelerator card, or the like.
In some embodiments of the present application, the card control information is information indicating that the server swipes one of the plurality of smart accelerator cards.
In other embodiments of the present application, the card control information is information indicating that the server performs an upgrade operation on one of the plurality of smart accelerator cards.
When a user performs a card swiping operation or an upgrade operation on the smart accelerator card on the server side, the server acquires corresponding card control information, and detects relevant information stored on the server side and used for performing the control operation on the smart accelerator card, such as a card swiping version file or an upgrade version file of the smart accelerator card.
In other embodiments of the present application, the card control information is information indicating that the server performs a reset operation on one of the plurality of smart accelerator cards. When the intelligent accelerator card acquires a reset operation instruction, for example, when an abnormality occurs in a certain intelligent accelerator card and needs to be reset, the intelligent accelerator card sends the reset operation instruction to a first reset register of the intelligent accelerator card to instruct the intelligent accelerator card to complete the reset operation.
The card control information may be generated after a related instruction input by the user, such as a machine swipe or upgrade, or may be automatically generated after the server detects that the smart accelerator card is abnormal, which is not limited herein.
Step S102, a first starting mode switching instruction is sent to the intelligent accelerator card, wherein the first starting mode switching instruction is used for indicating the intelligent accelerator card to switch a starting mode to a PCIE starting mode through a preset register.
In this embodiment of the present application, the first start mode switching instruction may be generated after the server writes a specified value, such as 1, to the predetermined register pcie_host_bootmode. And after a preset register of the intelligent accelerator card receives the first starting mode switching instruction, the pin controller is informed to switch the starting mode to the PCIE starting mode.
In practical applications, smart accelerator cards are typically activated by storing a start-up pattern. However, when an abnormality occurs in a software version stored in the smart accelerator card or the smart accelerator card fails, the smart accelerator card needs to be started in a storage starting mode to finish a machine-swiping operation or an upgrading operation, if the smart accelerator card is started in a storage starting mode, problems such as abnormal interruption and dead halt may occur in the machine-swiping or upgrading process of the smart accelerator card, and smooth completion of the machine-swiping or upgrading operation cannot be ensured.
In the embodiment of the application, after the server acquires the card control information, the server sends the first starting mode switching instruction to the preset register of the intelligent accelerator card through the PCIE bus, so that after the intelligent accelerator card receives the first starting mode switching instruction, the starting mode of the intelligent accelerator card is switched from the storage starting mode to the PCIE starting mode, so that the intelligent accelerator card can receive the card control information transmitted by the PCIE bus, the purpose of controlling the intelligent accelerator card on the server is achieved, and the control of each intelligent accelerator card can be achieved under the condition of not depending on hardware pins of the server such as GPIO interfaces/system management buses, such as independent machine brushing, upgrading, abnormal resetting management and the like.
In practical application, after receiving the first starting mode switching instruction, the smart accelerator card may only change the instruction value of the starting mode, in fact, the starting mode of the smart accelerator card is not really converted from the storage starting mode to the PCIE starting mode, that is, PCIE bus connection is not normally reset, and at this time, the smart accelerator card and the server cannot be connected through PCIE bus communication. In this case, in order to ensure that the startup mode of the smart accelerator card is switched to the PCIE startup mode, the server is required to send a RESET instruction to the first RESET register pcie_hot-RESET of the smart accelerator card, so as to ensure that the startup mode of the smart accelerator card is switched to the PCIE startup mode, that is, the purpose of sending the RESET instruction is to ensure that the startup mode of the smart accelerator card is the PCIE startup mode when the smart accelerator card is swiped, so that the situation that the smart accelerator card actually only changes the value of the switching mode and does not actually switch to the PCIE startup mode is avoided, and reliability and stability of control of the smart accelerator card are ensured.
After receiving the reset instruction, the first reset register initiates a reset operation to the intelligent accelerator card, and resets all modules except the preset register, namely the preset register prohibits execution of the first reset instruction, so that the problem that the intelligent accelerator card cannot be controlled at the side of the server after the preset register is reset is avoided.
Step S103, when detecting that PCIE bus communication is normal, executing a card control instruction, and sending a card version file to the intelligent accelerator card through the PCIE bus, wherein the intelligent accelerator card is in communication connection with the server through the PCIE bus.
In the embodiment of the application, after sending the first starting mode switching instruction to the preset register of the intelligent accelerator card, the server detects whether PCIE bus communication is normal or not so as to ensure whether the card version file can be sent to the intelligent accelerator card through the PCIE bus, and when the PCIE bus communication is normal, the server executes the card control instruction and sends the card version file to the intelligent accelerator card through the PCIE bus so as to manage and control the intelligent accelerator card. For example, when the server detects that PCIE bus communication is normal, the startup script executes a swiping instruction or an upgrade instruction, and transmits the swiping version file or the upgrade version file to a memory of a corresponding smart accelerator card, such as an embedded memory (Embedded Multi Media Card, EMMC), through a PCIE bus domain address.
It should be noted that, when executing the card control management instruction, the start mode of the pin controller BOOTMODE of the intelligent accelerator card needs to be a PCIE start mode, so that the card version file can be transmitted to the intelligent accelerator card through the PCIE bus, and abnormal situations such as crash, blocking and the like of the intelligent accelerator card when the server executes the card control instruction such as the machine-swiping instruction, the upgrading instruction and the like are avoided, and stability and reliability of controlling the intelligent accelerator card are ensured.
Step S104, a second starting mode switching instruction is sent to a preset register of the intelligent accelerator card, and the second starting mode switching instruction is used for indicating the intelligent accelerator card to switch the starting mode to the storage starting mode through the preset register.
In this embodiment of the present application, after the server executes the card control instruction and sends the card version file to the smart accelerator card through the PCIE bus, control and control of the smart accelerator card are completed, for example, a machine-swiping operation or an upgrade operation of the smart accelerator card is completed, and the subsequent smart accelerator card may perform related work with the machine-swiping or the upgraded version. However, in the PCIE start mode, the version file of the smart accelerator card on the server side is transmitted to the smart accelerator card through the PCIE bus, so that the update of the version file of the smart accelerator card is implemented, and the operation of swiping or upgrading is completed.
In order to ensure that the smart accelerator card can work normally after the operation of swiping or upgrading is completed, the start mode of the smart accelerator card needs to be switched to a storage start mode, so that the smart accelerator card can be started from the storage of the smart accelerator card, such as EMMC, to perform normal service.
In some embodiments of the present application, after sending the second startup mode switch instruction to the predetermined register of the smart accelerator card, a reset instruction is sent to the first reset register of the smart accelerator card to ensure that the startup mode of the smart accelerator card has been switched to the storage startup mode.
In practical applications, after receiving the second starting mode switching instruction, the smart accelerator card may only change the instruction value of the starting mode, and in fact, the starting mode of the smart accelerator card is not really converted from the PCIE starting mode to the storage starting mode, that is, the storage EMMC connection is not normally reset. At this time, the server is required to send a reset instruction to the first reset register of the smart accelerator card to confirm that the starting mode of the smart accelerator card has been switched to the storage starting mode, that is, the purpose of sending the reset instruction is to ensure that the smart accelerator card can work normally after the smart accelerator card is swiped, and the starting mode of the smart accelerator card is switched to the storage starting mode by the reset instruction, so that the situation that the smart accelerator card is actually only changed in value and is not actually switched to the storage starting mode is avoided, normal service of the smart accelerator card is ensured, and reliability and stability of controlling the smart accelerator card are improved.
After receiving the reset instruction, the first reset register initiates a reset operation to the intelligent accelerator card, and resets all modules except the preset register, namely the preset register prohibits execution of the reset instruction, so that the problem that the intelligent accelerator card cannot be controlled on the side of the server after the preset register is reset is avoided.
In a specific embodiment of the present application, after obtaining a power-on command, the server sends a first starting mode switching command to a predetermined register of the smart accelerator card, and the smart accelerator card instructs the predetermined register to switch the starting mode to the PCIE starting mode according to the first starting mode switching command. The server sends a reset instruction to a first reset register of the intelligent accelerator card, and resets the intelligent accelerator card so as to ensure that the intelligent accelerator card works in a PCIE starting mode. And when the server detects that PCIE communication is normal, executing a flashing instruction, and transmitting the flashing version file stored on the server side to the storage of the intelligent accelerator card through the PCIE bus. After the file of the machine-swiping version is transmitted to the storage of the intelligent accelerator card, the server sends a second starting mode switching instruction to the intelligent accelerator card to instruct the intelligent accelerator card to switch the starting mode to the storage starting mode, and the machine-swiping operation of the intelligent accelerator card is completed, so that the intelligent accelerator card can perform normal business.
In another specific embodiment of the present application, after obtaining the upgrade instruction, the server sends a first start mode switching instruction to a predetermined register of the smart accelerator card, and the smart accelerator card instructs the predetermined register to switch the start mode to the PCIE start mode according to the first start mode switching instruction. The server sends a reset instruction to a first reset register of the intelligent accelerator card, and resets the intelligent accelerator card so as to ensure that the intelligent accelerator card works in a PCIE starting mode. And when the server detects that PCIE communication is normal, executing an upgrade instruction, and transmitting the upgrade version file stored on the server side to the storage of the intelligent accelerator card through the PCIE bus. After the upgrade version file is transmitted to the storage of the intelligent accelerator card, the server sends a second starting mode switching instruction to the intelligent accelerator card to instruct the intelligent accelerator card to switch the starting mode to the storage starting mode, and upgrade operation of the intelligent accelerator card is completed, so that the intelligent accelerator card can perform normal service.
In the embodiment of the application, the card control information is obtained, and the card control information comprises a card control instruction and a card version file; a first starting mode switching instruction is sent to the intelligent accelerator card, and the first starting mode switching instruction is used for indicating the intelligent accelerator card to switch a starting mode to a PCIE starting mode through a preset register; when PCIE communication is detected to be normal, executing a card control instruction, and sending a card version file to the intelligent accelerator card through a PCIE bus; the second starting mode switching instruction is sent to a preset register of the intelligent accelerator card, and is used for indicating the intelligent accelerator card to switch the starting mode to the storage starting mode through the preset register, so that a plurality of intelligent accelerator cards can be conveniently and effectively managed, the intelligent accelerator cards can be applied to different servers without limitation to hardware interfaces of the servers, control and control of the intelligent accelerator cards can be effectively realized through assistance of the servers without depending on GPIO interfaces of the servers or system management buses, and reliability and stability of the intelligent accelerator cards are guaranteed.
Referring to fig. 3, fig. 3 is a flow chart of another control method of a smart accelerator card according to an embodiment of the present application, where the method is applied to the smart accelerator card; the control method of the smart accelerator card provided in fig. 1 is described in detail with reference to fig. 2, and specifically includes the following steps:
step 301, a first start mode switching instruction sent by the server is received, and a predetermined register is instructed to switch the start mode to a PCIE start mode according to the first start mode switching instruction, and the smart accelerator card and the server are connected through PCIE bus communication.
In this embodiment of the present application, when a predetermined register of the smart accelerator card receives a first start mode switching instruction sent by the server, the pin controller BOOTMODE in the smart accelerator card is instructed to switch the start mode to the PCIE start mode.
Please refer to the related description in the embodiment of fig. 1 for the related information of the predetermined register and PCIE start mode, and the detailed description is omitted here.
After step S301, the smart accelerator card further receives a RESET instruction sent by the server, and instructs the first RESET register pcie_hot_reset to perform a RESET operation on the smart accelerator card.
Step S302, a card version file sent by a server is received and stored.
In the embodiment of the application, after receiving the card version file sent by the server, the smart accelerator card stores the card version file into the EMMC of the smart accelerator card, so as to finish operations such as smart accelerator card swiping, smart accelerator card upgrading and the like.
Step S303, a second starting mode switching instruction sent by the server is received, and a preset register is instructed to switch the starting mode to the storage starting mode according to the second starting mode switching instruction.
In the embodiment of the application, after the intelligent accelerator card receives the second starting mode switching instruction sent by the server, the preset register is instructed to switch the starting mode to the storage starting mode, so that the intelligent accelerator card can perform normal service.
In the embodiment of the application, the instruction and the file sent by the server can be received by the intelligent accelerator card through the preset register inside the intelligent accelerator card, so that the management and the control can be realized on any one of the intelligent accelerator cards without adding an additional GPIO interface of the server, and the normal service of other intelligent accelerator cards is not influenced.
Example two
The server mentioned in the embodiment of the application is provided with an embedded management microcontroller and a system management bus, besides a standard PCIE interface, the embedded management microcontroller can be connected with a corresponding intelligent acceleration card through the system management bus, and an MCU chip arranged in the intelligent acceleration card can analyze a system management bus message so as to realize communication with the server, so that the server can manage and control the intelligent acceleration card, such as operations of abnormality diagnosis, upgrading and the like. Even under the condition of abnormal PCIE communication, the communication and handshake between the intelligent accelerator card and the server can be realized through the system management bus, so that the control of the intelligent accelerator card under the condition of abnormal PCIE communication is ensured.
In the embodiment of the application, in order to realize the access of the server to the smart accelerator card, a predetermined register pcie_host_bootmode is provided in the smart accelerator card, where an address of the predetermined register in a PCIE bus domain is allocated to a PCIE base address of the smart accelerator card by the server, and an inbound bound mapping of a bus protocol of the PCIE bus domain to the smart accelerator card, such as (Advanced eXtensible Interface, AXI) domain, is determined together, for example, the predetermined register is configured to be mapped to a predetermined space, such as a PCIE BAR0 space, so that the predetermined register can be accessed by the server HOST.
In some embodiments of the present application, an address mapping module is disposed in the smart accelerator card, where the address mapping module is configured to set address mapping from a PCIE bus domain address to a predetermined domain of the smart accelerator card, such as an AXI domain. A first RESET register pcie_hot_reset is configured on the address domain of the predetermined domain, and through the first RESET register pcie_hot_reset, the startup mode of the intelligent accelerator card may be switched to a PCIE startup mode or a storage startup mode, so as to implement control over the intelligent accelerator card.
In the embodiment of the application, the server can initiate the reset action by accessing the interface to operate the first reset register, and the reset operation of the intelligent accelerator card is realized through the initiated reset action.
When the inbound mapping is configured, the PCIE bus domain address of the predetermined register may be determined according to the configured inbound mapping.
Referring to fig. 4 and fig. 5, fig. 4 is a flowchart illustrating another control method of an intelligent accelerator card according to an embodiment of the present application, where the method is applied to a server; fig. 5 is an interaction schematic diagram of another control of the smart accelerator card provided in the embodiment of the present application, and a detailed description of a control method of the smart accelerator card provided in fig. 4 is described with reference to fig. 5, which is specifically as follows:
in step S401, card control information is acquired, where the card control information includes a card control instruction and a card version file.
Step S402, a first start mode switching instruction is sent to the smart accelerator card, where the first start mode switching instruction is used to instruct the smart accelerator card to switch the start mode to the PCIE start mode through a predetermined register.
Step S403, when detecting that the PCIE bus communication is abnormal, sending a preset command to the smart accelerator card through the system management bus, where the preset command is used to instruct the smart accelerator card to switch the start mode to the PCIE start mode, and resume PCIE communication through the second reset register.
In the embodiment of the present application, under the condition that PCIE bus communication is abnormal, after receiving a preset command, the smart accelerator card analyzes the preset command through the built-in MCU chip, and performs a response operation according to the preset command, notifies the board management soft control DBMSC unit on the side of the smart accelerator card to switch the start mode to the PCIE start mode, and notifies the second reset register to perform a reset operation, so as to resume PCIE bus communication.
Note that, the preset command may be preset, or may be automatically generated when detecting an abnormal PCIE bus communication, which is not limited herein.
It should be further noted that, in the embodiment of the present application, the PCIE is controlled under the condition that the PCIE bus can normally communicate, and when PCIE bus communication cannot be recovered to normal, it is possible that a PCIE interface fails, and in this case, the intelligent accelerator card cannot be controlled any more, and the PCIE interface or PCIE line with the failure needs to be replaced.
In this embodiment of the present application, the second reset register is a register in the smart accelerator card that is used for resetting the smart accelerator card, and the second reset register may reset all modules of the smart accelerator card including the PCIE register, so that the smart accelerator card resumes PCIE communication under normal conditions of the PCIE interface and the PCIE line.
In step S404, when it is queried that the start mode of the smart accelerator card has been switched to the PCIE start mode and PCIE communication resumes, a card control instruction is executed, and a card version file is sent to the smart accelerator card through the PCIE bus.
In the embodiment of the application, the server inquires whether the starting mode of the intelligent accelerator card is switched to the PCIE starting mode through the SMBus bus, and whether PCIE communication is restored to normal. When the starting mode of the intelligent accelerator card is searched to be switched to the PCIE starting mode and PCIE communication is recovered to be normal, the server executes a card control instruction and sends a card version file to the intelligent accelerator card through the PCIE bus so as to realize management and control of the intelligent accelerator card.
After the server sends the card version file to the intelligent accelerator card through the PCIE bus, the server may send a second start mode switching instruction to the intelligent accelerator card through the system management bus or the PCIE bus, to instruct the intelligent accelerator card to switch the start mode to the storage start mode through a predetermined register.
In this embodiment of the present application, after the server executes the card control instruction and sends the card version file to the smart accelerator card through the PCIE bus, control and control of the smart accelerator card are completed, for example, a machine-swiping operation or an upgrade operation of the smart accelerator card is completed, and the subsequent smart accelerator card may perform related work with the machine-swiping or the upgraded version. However, in the PCIE startup mode, the version file of the smart accelerator card on the server side is transmitted to the smart accelerator card through the PCIE bus, so that in order to ensure that the smart accelerator card can normally work after finishing the operation of swiping a machine or the operation of upgrading, the startup mode of the smart accelerator card needs to be switched to the storage startup mode, so that the smart accelerator card can be started from the storage of the smart accelerator card, such as EMMC, to perform normal service.
In some embodiments of the present application, after sending the second startup mode switching instruction to the predetermined register of the smart accelerator card, a reset instruction is sent to the first reset register of the smart accelerator card, so as to switch the startup mode of the smart accelerator card to the storage startup mode.
In practical applications, after receiving the second starting mode switching instruction, the smart accelerator card may only change the instruction value of the starting mode, and in fact, the starting mode of the smart accelerator card is not really converted from the PCIE starting mode to the storage starting mode, that is, the EMMC connection is not normally reset. At this time, the server is required to send a reset instruction to the first reset register of the smart accelerator card to ensure that the start mode of the smart accelerator card is switched to the storage start mode, that is, the purpose of sending the second reset instruction is to ensure that the smart accelerator card can work normally after the smart accelerator card is swiped, so that the situation that the smart accelerator card actually only changes the value of the switching mode and is not actually switched to the storage start mode is avoided.
After receiving the second reset instruction, the first reset register initiates a reset operation to the intelligent accelerator card, and resets all modules except the preset register, namely the preset register prohibits execution of the second reset instruction, so that the control and the control of the intelligent accelerator card on the side of the server cannot be realized after the preset register is reset.
It should be noted that each smart accelerator card has a unique address (e.g., slave address), and can only receive a preset command containing the address. If the addresses in the preset commands between the intelligent accelerator cards conflict, unique addresses can be dynamically allocated to the intelligent accelerator cards through a system management bus address resolution protocol.
In some embodiments of the present application, the server may also implement health management and control of the smart accelerator card, such as managing and controlling the temperature, frequency, voltage, fan status, etc. of the smart accelerator card.
In some embodiments of the present application, the server obtains health monitoring information of the smart accelerator card through the system management bus. When the health monitoring information contains information of abnormal health state of the intelligent accelerator card, such as that the temperature of a certain intelligent accelerator card is very high and is close to an unhealthy state, the intelligent accelerator card with the abnormal health state is monitored through a board card management soft control HBMSC unit of the server; when the health value of the intelligent accelerator card in abnormal health state exceeds a preset threshold, namely the temperature of the intelligent accelerator card is higher than the preset temperature threshold, the health monitoring information is packaged into a temperature message, the corresponding intelligent accelerator card is notified through a system management bus, so that after the intelligent accelerator card analyzes the temperature message, a board card management soft control DBMSC unit of the intelligent accelerator card is notified to perform abnormal elimination management, such as cooling, control frequency, nuclear number, or control of an external fan level, and the like, and after the health value is lower than the preset threshold, namely the requirement of the health state is met, abnormal elimination notification information is sent to a server, and the server updates the health monitoring information according to the received abnormal elimination notification information.
Referring to fig. 6, fig. 6 is a flowchart of another control method of a smart accelerator card according to an embodiment of the present application, where the method is applied to the smart accelerator card; the control method of the smart accelerator card provided in fig. 6 is described in detail with reference to fig. 5, and specifically includes the following steps:
in step S601, a first start mode switching instruction sent by the server is received, and a predetermined register is instructed to switch the start mode to the PCIE start mode according to the first start mode switching instruction.
In some embodiments of the present application, after step S601, the smart accelerator card further receives a first reset instruction sent by the server, and instructs the first reset register to perform a reset operation on the smart accelerator card.
Step S602, receiving a preset command sent by the server, switching the start mode to the PCIE start mode according to the preset command, and recovering PCIE communication through the second reset register.
In the embodiment of the application, after receiving the preset command sent by the server, the smart accelerator card analyzes the preset command, responds correspondingly according to the analysis result, notifies the preset register to switch the starting mode to the PCIE starting mode, and resumes PCIE communication through the second reset register.
Step S603, the card version file sent by the server is received and stored.
Step S604, a second starting mode switching instruction sent by the server is received, and a preset register is instructed to switch the starting mode to the storage starting mode according to the second starting mode switching instruction.
Note that, the related parts not described in the second embodiment are identical to the related description in the first embodiment, and are not described here again.
It should be understood that the sequence number of each step in the foregoing embodiment does not mean that the execution sequence of each process should be determined by the function and the internal logic of each process, and should not limit the implementation process of the embodiment of the present application in any way.
Based on the control method of the smart accelerator card provided by the above embodiment, the embodiment of the present application further provides an embodiment of a device for implementing the above embodiment of the method.
Referring to fig. 7, fig. 7 is a schematic diagram of a control device of a smart accelerator card according to an embodiment of the present application. The units included are for performing the steps in the corresponding embodiment of fig. 1. Refer specifically to the description of the corresponding embodiment in fig. 1. For convenience of explanation, only the portions related to the present embodiment are shown. Referring to fig. 7, the control device 7 of the smart accelerator card includes:
An information acquisition unit 71 for acquiring card control information including a card control instruction and a card version file;
a first startup mode switching instruction sending unit 72, configured to send a first startup mode switching instruction to the smart accelerator card, where the first startup mode switching instruction is configured to instruct the smart accelerator card to switch the startup mode to the PCIE startup mode through a predetermined register;
the first card control unit 73 is configured to execute a card control instruction when detecting that PCIE bus communication is normal, and send a card version file to the intelligent accelerator card through the PCIE bus, where the intelligent accelerator card is connected with the server through PCIE bus communication;
and a second start mode switching instruction sending unit 74, configured to send a second start mode switching instruction to a predetermined register of the smart accelerator card, where the second start mode switching instruction is configured to instruct the smart accelerator card to switch the start mode to the storage start mode through the predetermined register.
Specifically, the address of the predetermined register in the PCIE bus domain is determined by the PCIE base address allocated to the smart accelerator card by the server and the inbound mapping from the PCIE bus domain to the bus protocol predetermined domain of the smart accelerator card.
Preferably, the control device 7 of the smart accelerator card further comprises:
And the first reset instruction sending unit is used for sending a reset instruction to a first reset register of the intelligent accelerator card after sending the first starting mode switching instruction to the intelligent accelerator card.
Preferably, the control device 7 of the smart accelerator card further comprises:
and the second reset instruction sending unit is used for sending a reset instruction to the first reset register of the intelligent accelerator card after sending the second starting mode switching instruction to the intelligent accelerator card.
Preferably, the predetermined register prohibits execution of the first reset instruction and the second reset instruction.
Preferably, the control device 7 of the smart accelerator card further comprises:
the first PCIE communication abnormality management unit is used for sending a preset command to the intelligent accelerator card through the system management bus when PCIE bus communication abnormality is detected, wherein the preset command is used for indicating the intelligent accelerator card to switch a starting mode to a PCIE starting mode and recovering PCIE communication through the second reset register;
and the second card control unit is used for executing a card control instruction when the starting mode of the intelligent accelerator card is inquired to be switched to the PCIE starting mode and PCIE communication is recovered to be normal, and sending a card version file to the intelligent accelerator card through the PCIE bus.
Referring to fig. 8, fig. 8 is a schematic diagram of another control device for a smart accelerator card according to an embodiment of the present application. The units included are for performing the steps in the corresponding embodiment of fig. 3. Refer specifically to the description of the corresponding embodiment in fig. 3. For convenience of explanation, only the portions related to the present embodiment are shown. Referring to fig. 8, the control device 8 of the smart accelerator card includes:
the first starting mode switching instruction receiving and processing unit 81 is configured to receive a first starting mode switching instruction sent by the server, instruct a predetermined register to switch the starting mode to a PCIE starting mode according to the first starting mode switching instruction, and connect the smart accelerator card and the server through PCIE bus communication;
a first card version file receiving unit 82 for receiving a card version file transmitted from the server and storing the card version file;
the second start mode switching instruction receiving and processing unit 83 is configured to receive a second start mode switching instruction sent by the server, and instruct the predetermined register to switch the start mode to the storage start mode according to the second start mode switching instruction.
Preferably, the control device 8 of the smart accelerator card further comprises:
The second PCIE communication anomaly management unit is used for receiving a preset command sent by the server, switching the starting mode to a PCIE starting mode according to the preset command, and recovering PCIE communication through a second reset register;
a second card version file receiving unit for receiving the card version file sent by the server and storing the card version file;
and the third starting mode switching instruction receiving and processing unit is used for receiving a second starting mode switching instruction sent by the server and indicating a preset register to switch the starting mode to the storage starting mode according to the second starting mode switching instruction.
It should be noted that, because the content of information interaction and execution process between the modules is based on the same concept as the method embodiment of the present application, specific functions and technical effects thereof may be referred to in the method embodiment section, and details are not repeated herein.
Fig. 9 is a schematic diagram of a server provided in an embodiment of the present application. As shown in fig. 9, the server 9 of this embodiment includes: a processor 90, a memory 91 and a computer program 92, such as a speech recognition program, stored in the memory 91 and executable on the processor 90. The steps of the above-described embodiments of the control method of each smart accelerator card are implemented when the processor 90 executes the computer program 92, such as steps S101-S104 shown in fig. 1. Alternatively, the processor 90, when executing the computer program 92, performs the functions of the modules/units of the apparatus embodiments described above, such as the functions of the units 71-74 shown in fig. 7.
By way of example, the computer program 92 may be partitioned into one or more modules/units, which are stored in the memory 91 and executed by the processor 90 to complete the present application. One or more of the modules/units may be a series of computer program instruction segments capable of performing a specific function, which instruction segments are used to describe the execution of the computer program 92 in the server 9. For example, the computer program 92 may be divided into an information obtaining unit 71, a first start mode switching instruction sending unit 72, a first card control unit 73, and a second start mode switching instruction sending unit 74, and specific functions of each unit are described in the corresponding embodiment with reference to fig. 1, which is not repeated herein.
The server may include, but is not limited to, a processor 90, a memory 91. It will be appreciated by those skilled in the art that fig. 9 is merely an example of the server 9 and is not limiting of the server 9, and may include more or fewer components than shown, or may combine certain components, or different components, e.g., the server may also include input-output devices, network access devices, buses, etc.
The processor 90 may be a central processing unit (Central Processing Unit, CPU), other general purpose processor, digital signal processor (Digital Signal Processor, DSP), application specific integrated circuit (Application Specific Integrated Circuit, ASIC), off-the-shelf programmable gate array (Field-Programmable Gate Array, FPGA) or other programmable logic device, discrete gate or transistor logic device, discrete hardware components, or the like. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.
The memory 91 may be an internal storage unit of the server 9, such as a hard disk or a memory of the server 9. The memory 91 may also be an external storage device of the server 9, such as a plug-in hard disk, a Smart Media Card (SMC), a Secure Digital (SD) Card, a Flash memory Card (Flash Card) or the like, which are provided on the server 9. Further, the memory 91 may also include both an internal storage unit of the server 9 and an external storage device. The memory 91 is used to store computer programs and other programs and data required by the server. The memory 91 may also be used to temporarily store data that has been output or is to be output.
Fig. 10 is a schematic diagram of a smart accelerator card according to an embodiment of the present application. As shown in fig. 10, the smart accelerator card 10 of this embodiment includes: a processor 100, a memory 101, and a computer program 102, such as a speech recognition program, stored in the memory 101 and executable on the processor 100. The steps of the above-described embodiments of the control method of each smart accelerator card are implemented when the processor 100 executes the computer program 102, for example, steps S301 to S303 shown in fig. 3. Alternatively, processor 100, when executing computer program 102, performs the functions of the modules/units of the apparatus embodiments described above, such as the functions of units 81-83 shown in fig. 8.
By way of example, the computer program 102 may be partitioned into one or more modules/units that are stored in the memory 101 and executed by the processor 100 to complete the present application. One or more of the modules/units may be a series of computer program instruction segments capable of performing a specific function for describing the execution of the computer program 102 in the smart accelerator card 10. For example, the computer program 102 may be divided into a first start mode switching command receiving and processing unit 81, a first card version file receiving unit 82, and a second start mode switching command receiving and processing unit 83, and the specific functions of each unit are described in the corresponding embodiment of fig. 1, and are not repeated herein.
Smart accelerator card 10 may include, but is not limited to, a processor 100, a memory 101. It will be appreciated by those skilled in the art that fig. 10 is merely an example of a smart accelerator card 10 and is not intended to be limiting of the smart accelerator card 10, and may include more or fewer components than shown, or may combine certain components, or different components, e.g., the smart accelerator card may also include input-output devices, network access devices, buses, etc.
The processor 100 may be a central processing unit (Central Processing Unit, CPU), other general purpose processors, digital signal processors (Digital Signal Processor, DSP), application specific integrated circuits (Application Specific Integrated Circuit, ASIC), off-the-shelf programmable gate arrays (Field-Programmable Gate Array, FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, or the like. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.
The memory 101 may be an internal storage unit of the smart accelerator card 10, such as a hard disk or a memory of the smart accelerator card 10. The memory 101 is used to store computer programs and other programs and data required by the smart accelerator card. The memory 101 may also be used to temporarily store data that has been output or is to be output.
The embodiment of the application also provides a computer readable storage medium, wherein the computer readable storage medium stores a computer program, and the control method of the intelligent accelerator card can be realized when the computer program is executed by a processor.
The embodiment of the application provides a computer program product, which enables the control method of the smart accelerator card described in the above fig. 1 to be realized when the computer program product runs on a server, or enables the control method of the smart accelerator card described in the above fig. 3 to be realized when the computer program product runs on the smart accelerator card.
It will be apparent to those skilled in the art that, for convenience and brevity of description, only the above-described division of the functional units and modules is illustrated, and in practical application, the above-described functional distribution may be performed by different functional units and modules according to needs, i.e. the internal structure of the apparatus is divided into different functional units or modules to perform all or part of the above-described functions. The functional units and modules in the embodiment may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit, where the integrated units may be implemented in a form of hardware or a form of a software functional unit. In addition, specific names of the functional units and modules are only for convenience of distinguishing from each other, and are not used for limiting the protection scope of the present application. The specific working process of the units and modules in the above system may refer to the corresponding process in the foregoing method embodiment, which is not described herein again.
In the foregoing embodiments, the descriptions of the embodiments are emphasized, and in part, not described or illustrated in any particular embodiment, reference is made to the related descriptions of other embodiments.
Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.
The above embodiments are only for illustrating the technical solution of the present application, and are not limiting; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present application, and are intended to be included in the scope of the present application.

Claims (7)

1. The control method of the intelligent accelerator card is applied to a server and is characterized by comprising the following steps:
Acquiring card control information, wherein the card control information comprises a card control instruction and a card version file, and the card control information is used for indicating a server to manage and control any one or more of a plurality of intelligent acceleration cards;
a first starting mode switching instruction is sent to the intelligent accelerator card, and the first starting mode switching instruction is used for indicating the intelligent accelerator card to switch a starting mode to a PCIE starting mode through a preset register;
when detecting that PCIE bus communication is normal, executing the card control instruction, and sending a card version file to the intelligent accelerator card through the PCIE bus, wherein the intelligent accelerator card is in communication connection with the server through the PCIE bus;
a second starting mode switching instruction is sent to a preset register of the intelligent accelerator card, and the second starting mode switching instruction is used for indicating the intelligent accelerator card to switch a starting mode to a storage starting mode through the preset register;
after the first start mode switching instruction is sent to the intelligent accelerator card, the method further comprises the following steps: sending a reset instruction to a first reset register of the intelligent accelerator card so as to enable the first reset register to initiate reset operation to the intelligent accelerator card, and resetting all modules except the preset register so as to ensure that a starting mode of the intelligent accelerator card is switched to a PCIE starting mode;
After the second start mode switching instruction is sent to the predetermined register of the smart accelerator card, the method comprises the following steps: and sending a reset instruction to a first reset register of the intelligent accelerator card so as to enable the first reset register to initiate a reset operation to the intelligent accelerator card, and carrying out the reset operation on all modules except the preset register so as to ensure that the starting mode of the intelligent accelerator card is switched to a storage starting mode.
2. The method of claim 1, wherein the address of the predetermined register in the PCIE bus domain is determined by a PCIE base address allocated to the smart accelerator card by the server and an inbound mapping of the PCIE bus domain to a bus protocol predetermined domain of the smart accelerator card.
3. The method for controlling a smart accelerator card according to claim 1, further comprising, after said sending a first start mode switching instruction to said smart accelerator card, when said smart accelerator card is further communicatively connected to said server via a system management bus:
when detecting that PCIE bus communication is abnormal, sending a preset command to the intelligent accelerator card through a system management bus, wherein the preset command is used for indicating the intelligent accelerator card to switch a starting mode to a PCIE starting mode and recovering PCIE communication through a second reset register; the second reset register is a register in the intelligent accelerator card, which is used for resetting the intelligent accelerator card, and the second reset register can reset all modules of the intelligent accelerator card, including a PCIE register, so that the intelligent accelerator card resumes PCIE communication under the conditions that a PCIE interface and a PCIE line are normal;
And when the starting mode of the intelligent accelerator card is searched to be switched to the PCIE starting mode and PCIE communication is recovered to be normal, executing the card control instruction and sending a card version file to the intelligent accelerator card through a PCIE bus.
4. The control method of the intelligent accelerator card is applied to the intelligent accelerator card and is characterized by comprising the following steps:
receiving a first starting mode switching instruction sent by a server, and indicating a preset register to switch a starting mode to a PCIE starting mode according to the first starting mode switching instruction, wherein the intelligent accelerator card and the server are in communication connection through a PCIE bus;
receiving a card version file sent by the server and storing the card version file; the card version file is obtained by the server according to card control information, the card control information comprises a card control instruction and a card version file, the card control information is used for indicating the server to manage and control any one or more of a plurality of intelligent acceleration cards, and the card version file is sent to the intelligent acceleration cards by the server through the PCIE bus; wherein, the receiving the card version file sent by the server includes: when the server detects that the PCIE bus communication is normal, executing the card control instruction, and sending the card version file to the intelligent accelerator card through the PCIE bus;
Receiving a second starting mode switching instruction sent by the server, and indicating the preset register to switch the starting mode to a storage starting mode according to the second starting mode switching instruction;
after receiving the first starting mode switching instruction sent by the server, the method further comprises the following steps: the first reset register receives a first reset instruction; the first reset instruction is used for enabling the first reset register to initiate reset operation to the intelligent accelerator card, and resetting all modules except the preset register so as to ensure that the starting mode of the intelligent accelerator card is switched to a PCIE starting mode;
after receiving the second starting mode switching instruction sent by the server, the method further comprises the following steps: the first reset register receives a second reset instruction; the second reset instruction is used for enabling the first reset register to initiate reset operation to the intelligent accelerator card, and resetting all modules except the preset register so as to ensure that the starting mode of the intelligent accelerator card is switched to a storage starting mode.
5. A server comprising a processor, a memory and a computer program stored in the memory and executable on the processor, the processor implementing the method of any one of claims 1 to 3 when the computer program is executed.
6. A smart accelerator card comprising a processor, a memory, and a computer program stored in the memory and executable on the processor, the processor implementing the method of claim 4 when the computer program is executed.
7. A computer readable storage medium storing a computer program, characterized in that the computer program when executed by a processor implements the method according to any one of claims 1 to 4.
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Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1195951A2 (en) * 2000-08-10 2002-04-10 Alcatel Method and apparatus for maintaining data communication during a line card soft reset operation
CN102012791A (en) * 2010-10-15 2011-04-13 中国人民解放军国防科学技术大学 Flash based PCIE (peripheral component interface express) board for data storage
CN105279133A (en) * 2015-10-20 2016-01-27 电子科技大学 VPX parallel DSP signal processing board card based on SoC online reconstruction
CN108519892A (en) * 2018-03-27 2018-09-11 广州视源电子科技股份有限公司 Start-up mode selection circuit and electronic equipment
CN108958989A (en) * 2017-06-06 2018-12-07 北京猎户星空科技有限公司 A kind of system failure recovery method and device
CN110399220A (en) * 2019-07-19 2019-11-01 苏州浪潮智能科技有限公司 A kind of management method and relevant apparatus of FPGA accelerator card
CN110780932A (en) * 2019-09-26 2020-02-11 苏州浪潮智能科技有限公司 Working mode switching method and device of PCIE switching chip
CN111008102A (en) * 2019-10-18 2020-04-14 苏州浪潮智能科技有限公司 FPGA accelerator card high-speed interface SI test control device, system and method
CN111338862A (en) * 2020-02-16 2020-06-26 苏州浪潮智能科技有限公司 GPU mode switching stability test method, system, terminal and storage medium
CN111338700A (en) * 2020-02-24 2020-06-26 杭州迪普科技股份有限公司 Method and device for loading FPGA version and storage medium
US10996969B1 (en) * 2017-11-28 2021-05-04 Amazon Technologies, Inc. Controlling access by a network interface

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3488701B2 (en) * 2001-05-25 2004-01-19 株式会社東芝 Wireless card and wireless device
JP4602047B2 (en) * 2004-10-29 2010-12-22 ルネサスエレクトロニクス株式会社 Information processing device
US7779242B2 (en) * 2005-12-22 2010-08-17 International Business Machines Corporation Data processing system component startup mode controls
US20180276161A1 (en) * 2017-03-27 2018-09-27 Sk Hynix Memory Solutions Inc. PCIe VIRTUAL SWITCHES AND AN OPERATING METHOD THEREOF

Patent Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1195951A2 (en) * 2000-08-10 2002-04-10 Alcatel Method and apparatus for maintaining data communication during a line card soft reset operation
CN102012791A (en) * 2010-10-15 2011-04-13 中国人民解放军国防科学技术大学 Flash based PCIE (peripheral component interface express) board for data storage
CN105279133A (en) * 2015-10-20 2016-01-27 电子科技大学 VPX parallel DSP signal processing board card based on SoC online reconstruction
CN108958989A (en) * 2017-06-06 2018-12-07 北京猎户星空科技有限公司 A kind of system failure recovery method and device
US10996969B1 (en) * 2017-11-28 2021-05-04 Amazon Technologies, Inc. Controlling access by a network interface
CN108519892A (en) * 2018-03-27 2018-09-11 广州视源电子科技股份有限公司 Start-up mode selection circuit and electronic equipment
CN110399220A (en) * 2019-07-19 2019-11-01 苏州浪潮智能科技有限公司 A kind of management method and relevant apparatus of FPGA accelerator card
CN110780932A (en) * 2019-09-26 2020-02-11 苏州浪潮智能科技有限公司 Working mode switching method and device of PCIE switching chip
CN111008102A (en) * 2019-10-18 2020-04-14 苏州浪潮智能科技有限公司 FPGA accelerator card high-speed interface SI test control device, system and method
CN111338862A (en) * 2020-02-16 2020-06-26 苏州浪潮智能科技有限公司 GPU mode switching stability test method, system, terminal and storage medium
CN111338700A (en) * 2020-02-24 2020-06-26 杭州迪普科技股份有限公司 Method and device for loading FPGA version and storage medium

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
基于FPGA的网络安全加速卡研究与设计;明幼林;信息科技(第4期);全文 *

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