CN114185603A - Control method of intelligent accelerator card, server and intelligent accelerator card - Google Patents

Control method of intelligent accelerator card, server and intelligent accelerator card Download PDF

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Publication number
CN114185603A
CN114185603A CN202111316053.0A CN202111316053A CN114185603A CN 114185603 A CN114185603 A CN 114185603A CN 202111316053 A CN202111316053 A CN 202111316053A CN 114185603 A CN114185603 A CN 114185603A
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China
Prior art keywords
accelerator card
card
smart
server
starting mode
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Granted
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CN202111316053.0A
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Chinese (zh)
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CN114185603B (en
Inventor
张映俊
李实秋
孙刘洋
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Jiangsu Yuntian Lifei Technology Co ltd
Shenzhen Intellifusion Technologies Co Ltd
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Jiangsu Yuntian Lifei Technology Co ltd
Shenzhen Intellifusion Technologies Co Ltd
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Priority to CN202111316053.0A priority Critical patent/CN114185603B/en
Publication of CN114185603A publication Critical patent/CN114185603A/en
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/4401—Bootstrapping
    • G06F9/4411—Configuring for operating with peripheral devices; Loading of device drivers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/24—Resetting means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/102—Program control for peripheral devices where the programme performs an interfacing function, e.g. device driver
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0026—PCI express

Abstract

The application provides a control method of an intelligent accelerator card, a server and the intelligent accelerator card, relates to the technical field of information, can conveniently and effectively manage a plurality of intelligent accelerator cards, breaks away from the limitation of hardware pins of the server, and ensures the reliability and stability of the intelligent accelerator card. The method comprises the following steps: acquiring card control information, wherein the card control information comprises a card control instruction and a card version file; sending a first starting mode switching instruction to the intelligent accelerator card, and indicating the intelligent accelerator card to switch the starting mode to the PCIE starting mode through a preset register; when detecting that the PCIE bus communication is normal, executing a card control command, and sending a card version file to the intelligent accelerator card through the PCIE bus, wherein the intelligent accelerator card is in communication connection with the server through the PCIE bus; and sending a second starting mode switching instruction to a preset register of the intelligent accelerator card, and instructing the intelligent accelerator card to switch the starting mode to the storage starting mode through the preset register.

Description

Control method of intelligent accelerator card, server and intelligent accelerator card
Technical Field
The present application relates to the field of information technologies, and in particular, to a method for controlling an intelligent accelerator card, a server, and an intelligent accelerator card.
Background
With the rapid development of search engines, cloud computing, internet retail, Web 2.0, mobile devices, network games, and the like, network traffic is reaching unprecedented levels. The smart accelerator card can be directly inserted into all commercial servers or network devices (such as VPN, UTM, IDS, flow control, load balancing, firewall, security audit, public opinion monitoring, signaling monitoring and the like), provides 10 times of I/O performance, has lower cost and is widely applied.
When the smart accelerator card is used with a server, such as a commercial x86 server, it is generally required that multi-card insertion and use can be supported. However, when the independent board card is managed and controlled, some of the independent board cards need an additional hardware pin of the server, that is, a General-purpose input/output (GPIO) interface, some of the independent board cards need to support a system management bus, and some of the independent board cards need to be additionally extended to add an external chip for control, which results in high complexity of management and control and high management cost.
Disclosure of Invention
The embodiment of the application provides a control method and device for an intelligent accelerator card, a server and the intelligent accelerator card, which can conveniently and effectively manage a plurality of intelligent accelerator cards, get rid of the limitation of hardware pins of the server and ensure the reliability and stability of the intelligent accelerator card.
In a first aspect, the present application provides a method for controlling a smart accelerator card, which is applied to a server and includes: acquiring card control information, wherein the card control information comprises a card control instruction and a card version file; sending a first starting mode switching instruction to the intelligent accelerator card, wherein the first starting mode switching instruction is used for indicating the intelligent accelerator card to switch the starting mode to the PCIE starting mode through a preset register; when detecting that the PCIE bus communication is normal, executing a card control command, and sending a card version file to the intelligent accelerator card through the PCIE bus, wherein the intelligent accelerator card is in communication connection with the server through the PCIE bus; and sending a second starting mode switching instruction to a preset register of the intelligent accelerator card, wherein the second starting mode switching instruction is used for instructing the intelligent accelerator card to switch the starting mode to the storage starting mode through the preset register.
In the embodiment of the application, after the server acquires the card control information, the server controls the predetermined register of the smart accelerator card to realize the switching of the start mode, switches the start mode of the smart accelerator card to the PCIE start mode, executes the card control instruction in the mode, and transmits the card version file with larger data to the smart accelerator card through the PCIE bus, so that the smart accelerator card can be applied to different servers without being limited by hardware interfaces of the servers, and can also effectively realize the control and the control of the smart accelerator card through the assistance of the servers without depending on GPIO interfaces of the servers or system management buses, and ensure the reliability and the stability of the control of the smart accelerator card.
Specifically, the address of the predetermined register in the PCIE bus domain is determined by the PCIE base address allocated to the smart accelerator card by the server and the inbound mapping from the PCIE bus domain to the bus protocol predetermined domain of the smart accelerator card.
Preferably, after sending the first start mode switching instruction to the smart accelerator card, the method further includes:
and sending a reset instruction to a first reset register of the intelligent accelerator card.
In the embodiment of the application, after the server sends the first start mode switching instruction to the smart accelerator card, the reset operation on the smart accelerator card is realized through the first reset register, so as to ensure that the smart accelerator card is really switched to the PCIE start mode, thereby reducing the occurrence of abnormal interruption, crash and other problems in the process of swiping or upgrading the smart accelerator card, ensuring the smooth completion of the swiping or upgrading operation, and improving the reliability and stability of the control on the smart accelerator card.
Preferably, after sending the second start mode switching instruction to the predetermined register of the smart accelerator card, the method includes:
and sending a reset instruction to a first reset register of the intelligent accelerator card.
In the embodiment of the application, after the server sends the second start mode switching instruction to the predetermined register of the smart accelerator card, the server sends the reset instruction to the first reset register of the smart accelerator card, so as to ensure that the smart accelerator card can normally work after the smart accelerator card is booted, the start mode of the smart accelerator card is switched to the storage start mode, thereby avoiding the situation that the smart accelerator card actually only changes the value of the switching mode but does not really switch to the storage start mode, ensuring that the smart accelerator card can perform normal service, and improving the reliability and stability of control over the smart accelerator card.
Preferably, when the smart accelerator card is further communicatively connected to the server through a system management bus, after the sending of the first start mode switching instruction to the smart accelerator card, the method further includes:
when detecting that the PCIE bus communication is abnormal, sending a preset command to the intelligent accelerator card through a system management bus, wherein the preset command is used for indicating the intelligent accelerator card to switch a starting mode to a PCIE starting mode and recovering the PCIE communication through a second reset register;
and when the starting mode of the intelligent accelerator card is inquired to be switched to the PCIE starting mode and the PCIE communication is recovered to be normal, executing the card control command and sending a card version file to the intelligent accelerator card through the PCIE bus.
According to the embodiment of the application, the system management bus sends the preset command to the intelligent accelerator card to recover the PCIE communication and switch the starting mode of the intelligent accelerator card to the PCIE starting mode, so that the intelligent accelerator card can be managed and controlled under the condition that the PCIE communication is abnormal, and the stability and the reliability of controlling the intelligent accelerator card are improved.
In a second aspect, the present application provides another control method for a smart accelerator card, which is applied to the smart accelerator card, and includes: receiving a first starting mode switching instruction sent by a server, and indicating a predetermined register to switch a starting mode to a PCIE starting mode according to the first starting mode switching instruction, wherein the intelligent accelerator card is in communication connection with the server through a PCIE bus; receiving a card version file sent by a server and storing the card version file; and receiving a second starting mode switching instruction sent by the server, and indicating a preset register to switch the starting mode to the storage starting mode according to the first starting mode switching instruction.
In a third aspect, the present application provides a control device for a smart accelerator card, which is applied to a server, and includes:
an information acquisition unit for acquiring card control information including a card control instruction and a card version file;
the first starting mode switching instruction sending unit is used for sending a first starting mode switching instruction to the intelligent accelerator card, and the first starting mode switching instruction is used for indicating the intelligent accelerator card to switch the starting mode to the PCIE starting mode through a preset register;
the first card control unit is used for executing a card control command when detecting that the PCIE bus communication is normal, and sending a card version file to the intelligent accelerator card through the PCIE bus, and the intelligent accelerator card is in communication connection with the server through the PCIE bus;
and the second starting mode switching instruction sending unit is used for sending a second starting mode switching instruction to a preset register of the intelligent accelerator card, and the second starting mode switching instruction is used for instructing the intelligent accelerator card to switch the starting mode to the storage starting mode through the preset register.
In a fourth aspect, the present application provides another control apparatus for a smart accelerator card, which is applied to the smart accelerator card, and includes:
the first starting mode switching instruction receiving and processing unit is used for receiving a first starting mode switching instruction sent by the server and indicating the predetermined register to switch the starting mode to the PCIE starting mode according to the first starting mode switching instruction;
the first card version file receiving unit is used for receiving the card version file sent by the server and storing the card version file;
and the second starting mode switching instruction receiving and processing unit is used for receiving a second starting mode switching instruction sent by the server and indicating the preset register to switch the starting mode to the storage starting mode according to the first starting mode switching instruction.
In a fifth aspect, the present application provides a server comprising a processor, a memory, and a computer program stored in the memory and executable on the processor, the processor implementing the method according to the first aspect or any alternative of the first aspect when executing the computer program.
In a sixth aspect, the present application provides a smart accelerator card comprising a processor, a memory, and a computer program stored in the memory and executable on the processor, the processor implementing the method according to the second aspect or any alternative of the second aspect when executing the computer program.
In a seventh aspect, the present application provides a computer readable storage medium storing a computer program which, when executed by a processor, implements the method of the first aspect, any of the alternatives of the first aspect, the second aspect or any of the alternatives of the second aspect.
In an eighth aspect, embodiments of the present application provide a computer program product, which, when running on a control device of a smart accelerator card, causes a server to execute the steps of the control method of the smart accelerator card according to the first aspect, or causes the smart accelerator card to execute the steps of the control method of the smart accelerator card according to the second aspect.
It is understood that the beneficial effects of the second aspect to the eighth aspect can be referred to the related description of the first aspect, and are not described herein again.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments or the prior art descriptions will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive exercise.
Fig. 1 is a schematic flowchart of a control method of a smart accelerator card according to an embodiment of the present application;
FIG. 2 is an interaction diagram illustrating control of a smart accelerator card according to an embodiment of the present disclosure;
fig. 3 is a schematic flowchart of another control method for a smart accelerator card according to an embodiment of the present application;
fig. 4 is a schematic flowchart of another control method for a smart accelerator card according to an embodiment of the present application;
FIG. 5 is an interaction diagram of another smart accelerator card control provided by an embodiment of the present application;
fig. 6 is a schematic flowchart of another control method for a smart accelerator card according to an embodiment of the present application;
fig. 7 is a schematic structural diagram of a control device of a smart accelerator card according to an embodiment of the present application;
fig. 8 is a schematic structural diagram of a control device of a smart accelerator card according to an embodiment of the present application;
fig. 9 is a schematic structural diagram of a server provided in an embodiment of the present application;
fig. 10 is a schematic structural diagram of a smart accelerator card according to an embodiment of the present application.
Detailed Description
In the following description, for purposes of explanation and not limitation, specific details are set forth, such as particular system structures, techniques, etc. in order to provide a thorough understanding of the embodiments of the present application. It will be apparent, however, to one skilled in the art that the present application may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present application with unnecessary detail.
It should be understood that the term "and/or" as used in this specification and the appended claims refers to and includes any and all possible combinations of one or more of the associated listed items. Furthermore, in the description of the present application and the appended claims, the terms "first," "second," "third," and the like are used for distinguishing between descriptions and not necessarily for describing or implying relative importance.
It should also be appreciated that reference throughout this specification to "one embodiment" or "some embodiments," or the like, means that a particular feature, structure, or characteristic described in connection with the embodiment is included in one or more embodiments of the present application. Thus, appearances of the phrases "in one embodiment," "in some embodiments," "in other embodiments," or the like, in various places throughout this specification are not necessarily all referring to the same embodiment, but rather "one or more but not all embodiments" unless specifically stated otherwise. The terms "comprising," "including," "having," and variations thereof mean "including, but not limited to," unless expressly specified otherwise.
Example one
In the first embodiment, the server is not provided with an embedded management microcontroller, and is not provided with a redundant GPIO interface and a smart accelerator card for connection and control, and only has a high-speed serial component interconnect express (PCIE) interface. In this case, if the server needs to support the adaptation of multiple smart accelerator cards, it is difficult for the user to perform subsequent independent management control on the multiple smart accelerator cards, such as machine flushing, upgrading, exception management, and the like.
By the control method of the intelligent accelerator card, the limitation of the number of GPIO interfaces of the server is not relied on, and the control of any one or more intelligent accelerator cards in the plurality of intelligent accelerator cards, such as machine swiping and upgrading, can be completed on the server side.
In this embodiment of the present application, in order to implement access of a server to a smart accelerator card, a predetermined register PCIE _ HOST _ BOOTMODE is set in the smart accelerator card, where an address of the predetermined register in a PCIE bus domain is determined jointly by a PCIE base address allocated to the smart accelerator card by the server, and an inbound mapping of a bus protocol from the PCIE bus domain to the smart accelerator card, such as an Advanced eXtensible Interface (AXI) domain, for example, the predetermined register is configured to be mapped to a predetermined space, such as a PCIE BAR0 space, so as to be accessible by the server HOST.
In some embodiments of the present application, an address mapping module is disposed in the smart accelerator card, and the address mapping module is configured to set an address mapping from a PCIE bus domain address to a predetermined domain of the smart accelerator card, such as an AXI domain. And a first RESET register PCIE _ HOT _ RESET is configured on the address field of the predetermined field, and the starting mode of the intelligent accelerator card can be switched into a PCIE starting mode or a storage starting mode through the first RESET register PCIE _ HOT _ RESET so as to realize the control of the intelligent accelerator card.
In the embodiment of the application, the server may operate the first reset register through the access interface, initiate a reset action, and implement the reset operation of the smart accelerator card through the initiated reset action.
When the inbound mapping is configured, the PCIE bus domain address of the predetermined register may be determined according to the configured inbound mapping.
Specifically, after the device driver of the smart accelerator card maps the PCIE bus domain address of the predetermined register to the CPU virtual address space, the smart accelerator card may be accessed by the server through the access interface provided by the smart accelerator card.
Referring to fig. 1 and fig. 2, fig. 1 is a schematic flowchart illustrating a control method of a smart accelerator card according to an embodiment of the present application, where the method is applied to a server; fig. 2 is an interaction schematic diagram of control of a smart accelerator card according to an embodiment of the present application, and details of a control method of the smart accelerator card provided in fig. 1 are described with reference to fig. 2, specifically as follows:
step S101, card control information is obtained, wherein the card control information comprises a card control instruction and a card version file.
In the embodiment of the present application, the card control information is used to instruct the server to manage and control any one or more of the plurality of smart acceleration cards, including but not limited to smart acceleration card swiping, smart acceleration card upgrading, smart acceleration card exception management, and the like.
The card control information comprises a card control instruction and a card version file, and the card control instruction comprises a machine swiping instruction, an upgrading instruction, an abnormal recovery instruction and the like. The card version file includes a swipe version file, an upgrade version file, and the like.
In order to confirm which smart accelerator card is managed and controlled, the card control information further includes a card identifier of the smart accelerator card, and the card identifier may be a device address of the smart accelerator card.
In some embodiments of the present application, the card control information is information instructing the server to perform a swipe operation on one of the plurality of smart acceleration cards.
In other embodiments of the present application, the card control information is information instructing the server to perform an upgrade operation on one of the plurality of smart acceleration cards.
When a user performs a swipe operation or an upgrade operation on the smart accelerator card at the side of the server, the server acquires corresponding card control information and detects related information stored at the side of the server for performing the control operation on the smart accelerator card, such as a swipe version file or an upgrade version file of the smart accelerator card.
In other embodiments of the present application, the card control information is information instructing the server to perform a reset operation on one of the plurality of smart acceleration cards. When the smart accelerator card obtains a reset operation instruction, for example, when a certain smart accelerator card is abnormal and needs to be reset, the smart accelerator card sends the reset operation instruction to a first reset register of the smart accelerator card to instruct the smart accelerator card to complete the reset operation.
The card control information may be generated by a related instruction input by the user, such as a swipe of a machine and an upgrade, or may be automatically generated by the server after detecting that the smart acceleration card is abnormal, which is not specifically limited herein.
Step S102, sending a first start mode switching instruction to the smart accelerator card, where the first start mode switching instruction is used to instruct the smart accelerator card to switch the start mode to the PCIE start mode through a predetermined register.
In this embodiment of the application, the first starting mode switching instruction may be generated after the user writes a specified value, such as 1, into the predetermined register PCIE _ HOST _ BOOTMODE at the server. And when a preset register of the intelligent accelerator card receives a first starting mode switching instruction, informing the pin controller of switching the starting mode to the PCIE starting mode.
In practical applications, the smart accelerator card is generally activated by a memory activation mode. However, when the software version stored in the intelligent acceleration card is abnormal or the intelligent acceleration card is in failure, when the smart acceleration card needs to be started in the storage starting mode to complete the swiping operation or the upgrading operation, if the smart acceleration card is started in the storage starting mode, in the process of swiping the smart accelerator card or upgrading, problems of abnormal interruption, crash and the like may occur, the smooth completion of the swiping or upgrading operation cannot be ensured, in order to avoid this problem, in the embodiment of the present application, the start mode of the smart accelerator card is switched to the PCIE start mode through the first start mode switching instruction, so that when the smart accelerator card is in the PCIE start mode, and the software version used for swiping or upgrading is transmitted to the intelligent accelerator card from the server through the PCIE bus, so that the reliability and the stability of the swiping or upgrading of the intelligent accelerator card are ensured.
In the embodiment of the present application, after the server obtains the card control information, the server sends the first start mode switching instruction to the predetermined register of the smart accelerator card through the PCIE bus, so that the smart accelerator card switches the start mode of the smart accelerator card from the storage start mode to the PCIE start mode after receiving the first start mode switching instruction, so that the smart accelerator card can receive the card control information transmitted by the PCIE bus, thereby achieving the purpose of controlling the smart accelerator card on the server.
In practical application, after receiving the first start mode switching instruction, the smart accelerator card may only change the instruction value of the start mode, and actually, the start mode of the smart accelerator card is not really converted from the storage start mode to the PCIE start mode, that is, the PCIE bus connection is not normally reset, and at this time, the smart accelerator card and the server cannot be communicatively connected through the PCIE bus. At this time, in order to ensure that the start mode of the smart accelerator card is switched to the PCIE start mode, the server needs to send a RESET instruction to the first RESET register PCIE _ HOT-RESET of the smart accelerator card to ensure that the start mode of the smart accelerator card is switched to the PCIE start mode, that is, the purpose of sending the RESET instruction is to ensure that the start mode of the smart accelerator card is the PCIE start mode when the smart accelerator card is booted, which avoids a situation that the smart accelerator card actually changes only a value of the switching mode and does not really switch to the PCIE start mode, and ensures reliability and stability of control over the smart accelerator card.
After receiving the reset instruction, the first reset register initiates a reset operation to the smart accelerator card, and performs the reset operation on all modules except the predetermined register, that is, the predetermined register prohibits the execution of the first reset instruction, thereby avoiding that the control on the smart accelerator card cannot be realized on the side of the server after the reset operation is performed on the predetermined register.
Step S103, when detecting that the PCIE bus communication is normal, execute a card control instruction, and send a card version file to the smart accelerator card through the PCIE bus, where the smart accelerator card is in communication connection with the server through the PCIE bus.
In the embodiment of the application, after sending the first start mode switching instruction to the predetermined register of the smart accelerator card, the server detects whether the PCIE bus communication is normal to ensure whether the card version file can be sent to the smart accelerator card through the PCIE bus, and when the PCIE bus communication is normal, executes the card control instruction and sends the card version file to the smart accelerator card through the PCIE bus to manage and control the smart accelerator card. For example, when the server detects that the PCIE bus communication is normal, the server starts a script to execute a flashing command or an upgrading command, and transmits a flashing version file or an upgrading version file to a memory of the corresponding smart accelerator Card, such as an Embedded memory (EMMC), through the PCIE bus domain address.
It should be noted that, when executing the card control management instruction, the start mode of the BOOTMODE of the pin controller of the smart accelerator card needs to be the PCIE start mode, so that the card version file can be transmitted to the smart accelerator card through the PCIE bus, and abnormal situations such as a crash, a card pause, and the like of the smart accelerator card when the server executes the card control instruction such as a swipe instruction, an upgrade instruction, and the like are avoided, thereby ensuring the stability and reliability of controlling the smart accelerator card.
Step S104, sending a second starting mode switching instruction to a preset register of the intelligent accelerator card, wherein the second starting mode switching instruction is used for instructing the intelligent accelerator card to switch the starting mode to the storage starting mode through the preset register.
In the embodiment of the present application, after the server executes the card control instruction and sends the card version file to the smart accelerator card through the PCIE bus, the server completes control and control of the smart accelerator card, for example, completes a swipe operation or an upgrade operation of the smart accelerator card, and the subsequent smart accelerator card can perform related work with the swipe or upgraded version. However, in the PCIE start mode, the version file of the smart accelerator card on the side of the server is transmitted to the smart accelerator card through the PCIE bus, so that the card version file of the smart accelerator card is updated, and the swipe operation or the upgrade operation is completed.
In order to ensure that the smart accelerator card can work normally after completing the operation of swiping a computer or upgrading the computer, the start mode of the smart accelerator card needs to be switched to the storage start mode, so that the smart accelerator card can be started from the storage of the smart accelerator card, such as the EMMC, to perform normal services.
In some embodiments of the present application, after sending the second start-up mode switching instruction to the predetermined register of the smart accelerator card, a reset instruction is sent to the first reset register of the smart accelerator card to ensure that the start-up mode of the smart accelerator card has been switched to the storage start-up mode.
In practical applications, after receiving the second start mode switching instruction, the smart accelerator card may change only the instruction value of the start mode, and actually, the start mode of the smart accelerator card is not really converted from the PCIE start mode to the storage start mode, that is, the storage EMMC connection is not normally reset. At this time, the server is required to send a reset instruction to the first reset register of the smart accelerator card to confirm that the start mode of the smart accelerator card has been switched to the storage start mode, that is, the reset instruction is sent to ensure that the smart accelerator card can normally operate after the smart accelerator card is booted, the start mode of the smart accelerator card is switched to the storage start mode through the reset instruction, so that the situation that the smart accelerator card actually changes only the value of the switching mode and does not really switch to the storage start mode is avoided, the smart accelerator card can perform normal service, and the reliability and stability of controlling the smart accelerator card are improved.
After receiving the reset instruction, the first reset register initiates a reset operation to the smart accelerator card, and performs the reset operation on all modules except the predetermined register, that is, the predetermined register prohibits the execution of the reset instruction, thereby avoiding that the control of the smart accelerator card cannot be realized on the side of the server after the reset operation is performed on the predetermined register.
In a specific embodiment of the present application, after obtaining the flashing instruction, the server sends a first start mode switching instruction to a predetermined register of the smart accelerator card, and the smart accelerator card instructs the predetermined register to switch the start mode to the PCIE start mode according to the first start mode switching instruction. The server sends a reset instruction to a first reset register of the intelligent accelerator card, and resets the intelligent accelerator card to ensure that the intelligent accelerator card works in a PCIE starting mode. When detecting that the PCIE communication is normal, the server executes a flashing instruction, and transmits a flashing version file stored at the server side to the storage of the intelligent accelerator card through the PCIE bus. After the version file of the smart accelerator card is transmitted to the smart accelerator card for storage, the server sends a second starting mode switching instruction to the smart accelerator card to instruct the smart accelerator card to switch the starting mode to the storage starting mode, so that the smart accelerator card can complete the operation of swiping the smart accelerator card, and the smart accelerator card can perform normal business.
In another specific embodiment of the present application, after obtaining the upgrade instruction, the server sends a first start mode switching instruction to a predetermined register of the smart accelerator card, and the smart accelerator card instructs the predetermined register to switch the start mode to the PCIE start mode according to the first start mode switching instruction. The server sends a reset instruction to a first reset register of the intelligent accelerator card, and resets the intelligent accelerator card to ensure that the intelligent accelerator card works in a PCIE starting mode. And when detecting that the PCIE communication is normal, the server executes an upgrading instruction and transmits an upgrading version file stored at the server side to the storage of the intelligent accelerator card through the PCIE bus. After the upgrade version file is transmitted to the intelligent accelerator card for storage, the server sends a second starting mode switching instruction to the intelligent accelerator card to indicate the intelligent accelerator card to switch the starting mode to the storage starting mode, so that the upgrade operation of the intelligent accelerator card is completed, and the intelligent accelerator card can perform normal services.
In the embodiment of the application, the card control information is acquired and comprises a card control instruction and a card version file; sending a first starting mode switching instruction to the intelligent accelerator card, wherein the first starting mode switching instruction is used for indicating the intelligent accelerator card to switch the starting mode to the PCIE starting mode through a preset register; when detecting that the PCIE communication is normal, executing a card control command, and sending a card version file to the intelligent accelerator card through the PCIE bus; the intelligent accelerator card control method comprises the steps of sending a second starting mode switching instruction to a preset register of the intelligent accelerator card, wherein the second starting mode switching instruction is used for indicating the intelligent accelerator card to switch a starting mode to a storage starting mode through the preset register, so that a plurality of intelligent accelerator cards can be conveniently and effectively managed, the intelligent accelerator card can be applied to different servers, hardware interfaces of the servers are not limited, GPIO interfaces or system management buses which do not depend on the servers can be used, the intelligent accelerator card can be effectively controlled and controlled with the assistance of the servers, and the reliability and stability of the intelligent accelerator card are guaranteed.
Referring to fig. 3, fig. 3 is a schematic flowchart illustrating another control method for a smart accelerator card according to an embodiment of the present application, where the method is applied to a smart accelerator card; the control method of the smart accelerator card provided in fig. 1 is described in detail with reference to fig. 2, specifically as follows:
step S301, receiving a first start mode switching instruction sent by the server, and instructing, according to the first start mode switching instruction, the predetermined register to switch the start mode to the PCIE start mode, where the smart accelerator card and the server are communicatively connected through a PCIE bus.
In this embodiment of the application, when receiving a first start mode switching instruction sent by a server, a predetermined register of an intelligent accelerator card instructs a pin controller BOOTMODE in the intelligent accelerator card to switch a start mode to a PCIE start mode.
Please refer to the relevant description in the embodiment of fig. 1 for the information about the predetermined register and the PCIE activation mode, which is not described herein again.
After step S301, the smart accelerator card further receives a RESET instruction sent by the server, and instructs the first RESET register PCIE _ HOT _ RESET to perform a RESET operation on the smart accelerator card.
Step S302, receiving the card version file sent by the server, and storing the card version file.
In the embodiment of the application, after receiving the card version file sent by the server, the smart accelerator card stores the card version file into the EMMC of the smart accelerator card, so as to complete operations such as swiping the smart accelerator card, upgrading the smart accelerator card, and the like.
Step S303, receiving a second start mode switching instruction sent by the server, and instructing the predetermined register to switch the start mode to the storage start mode according to the second start mode switching instruction.
In the embodiment of the application, after receiving the second start mode switching instruction sent by the server, the smart accelerator card instructs the predetermined register to switch the start mode to the storage start mode, so that the smart accelerator card can perform normal services.
In the embodiment of the application, the intelligent accelerator card can receive the instruction and the file sent by the server through the preset register in the intelligent accelerator card, so that any one of the intelligent accelerator cards can be managed and controlled without adding an additional GPIO (general purpose input/output) interface of the server, and meanwhile, the normal service of other intelligent accelerator cards is not influenced.
Example two
The server mentioned in the embodiment of the application is provided with an embedded management microcontroller and a system management bus, except for a standard PCIE interface, the server can be connected with a corresponding intelligent accelerator card through the system management bus, and an MCU chip arranged in the intelligent accelerator card can analyze a system management bus message so as to realize communication with the server, so that the server can manage and control the intelligent accelerator card, such as abnormal diagnosis, upgrading and other operations. Even under the condition of PCIE communication abnormity, the communication and handshake between the intelligent accelerator card and the server can be realized through the system management bus, and the control on the intelligent accelerator card can be also realized under the condition of PCIE communication abnormity.
In this embodiment of the present application, in order to implement access of a server to a smart accelerator card, a predetermined register PCIE _ HOST _ BOOTMODE is set in the smart accelerator card, where an address of the predetermined register in a PCIE bus domain is determined jointly by a PCIE base address allocated to the smart accelerator card by the server, and an inbound mapping of a bus protocol from the PCIE bus domain to the smart accelerator card, such as an Advanced eXtensible Interface (AXI) domain, for example, the predetermined register is configured to be mapped to a predetermined space, such as a PCIE BAR0 space, so as to be accessible by the server HOST.
In some embodiments of the present application, an address mapping module is disposed in the smart accelerator card, and the address mapping module is configured to set an address mapping from a PCIE bus domain address to a predetermined domain of the smart accelerator card, such as an AXI domain. And a first RESET register PCIE _ HOT _ RESET is configured on the address field of the predetermined field, and the starting mode of the intelligent accelerator card can be switched into a PCIE starting mode or a storage starting mode through the first RESET register PCIE _ HOT _ RESET so as to realize the control of the intelligent accelerator card.
In the embodiment of the application, the server may operate the first reset register through the access interface, initiate a reset action, and implement the reset operation of the smart accelerator card through the initiated reset action.
When the inbound mapping is configured, the PCIE bus domain address of the predetermined register may be determined according to the configured inbound mapping.
Referring to fig. 4 and fig. 5, fig. 4 is a schematic flowchart illustrating another control method for a smart accelerator card according to an embodiment of the present application, where the method is applied to a server; fig. 5 is an interaction schematic diagram of another control method of a smart accelerator card according to an embodiment of the present application, and the detailed description is made in conjunction with fig. 5 for a control method of the smart accelerator card provided in fig. 4, specifically as follows:
step S401, card control information is obtained, and the card control information comprises a card control instruction and a card version file.
Step S402, sending a first start mode switching instruction to the smart accelerator card, where the first start mode switching instruction is used to instruct the smart accelerator card to switch the start mode to the PCIE start mode through a predetermined register.
Step S403, when detecting that the PCIE bus communication is abnormal, sending a preset command to the smart accelerator card through the system management bus, where the preset command is used to instruct the smart accelerator card to switch the start mode to the PCIE start mode, and recovering the PCIE communication through the second reset register.
In the embodiment of the application, when PCIE bus communication is abnormal, the intelligent accelerator card parses the preset command through the built-in MCU chip after receiving the preset command, and performs response operation according to the preset command, notifies the board management soft control DBMSC unit on the side of the intelligent accelerator card to switch the start mode to the PCIE start mode, and notifies the second reset register to perform reset operation, so as to recover PCIE bus communication.
It should be noted that the preset command may be preset, or may be automatically generated when detecting a PCIE bus communication abnormality, which is not specifically limited herein.
It should be further noted that, in the embodiment of the present application, control over PCIE is implemented in a case that a PCIE bus can communicate normally, and when PCIE bus communication cannot be recovered to normal, a failure may occur in a PCIE interface.
In this embodiment of the present application, the second reset register is a register in the smart accelerator card, which is used for resetting the smart accelerator card, and the second reset register may reset all modules of the smart accelerator card, including the PCIE register, so that the smart accelerator card recovers PCIE communication when the PCIE interface and the PCIE line are normal.
Step S404, when the startup mode of the smart accelerator card is queried to be switched to the PCIE startup mode and the PCIE communication is recovered to normal, execute the card control instruction, and send the card version file to the smart accelerator card through the PCIE bus.
In the embodiment of the application, the server queries whether the starting mode of the intelligent accelerator card is switched to the PCIE starting mode through the SMBus bus, and whether PCIE communication is recovered to be normal. When the starting mode of the intelligent accelerator card is inquired to be switched to the PCIE starting mode and the PCIE communication is recovered to be normal, the server executes a card control command and sends a card version file to the intelligent accelerator card through the PCIE bus so as to realize the management and control of the intelligent accelerator card.
After the server sends the card version file to the intelligent accelerator card through the PCIE bus, the server can send a second starting mode switching instruction to the intelligent accelerator card through the system management bus or the PCIE bus, and the intelligent accelerator card is instructed to switch the starting mode to the storage starting mode through a preset register.
In the embodiment of the present application, after the server executes the card control instruction and sends the card version file to the smart accelerator card through the PCIE bus, the server completes control and control of the smart accelerator card, for example, completes a swipe operation or an upgrade operation of the smart accelerator card, and the subsequent smart accelerator card can perform related work with the swipe or upgraded version. However, in the PCIE start mode, the version file of the smart accelerator card on the side of the server is transmitted to the smart accelerator card through the PCIE bus, and in order to ensure that the smart accelerator card can normally work after completing the swipe operation or the upgrade operation, the start mode of the smart accelerator card needs to be switched to the storage start mode, so that the smart accelerator card can start from the storage of the smart accelerator card, such as the EMMC, to perform normal services.
In some embodiments of the present application, after sending the second start-up mode switching instruction to the predetermined register of the smart accelerator card, sending a reset instruction to the first reset register of the smart accelerator card to switch the start-up mode of the smart accelerator card to the storage start-up mode.
In practical applications, after receiving the second start mode switching instruction, the smart accelerator card may change only the instruction value of the start mode, and actually, the start mode of the smart accelerator card is not really converted from the PCIE start mode to the storage start mode, that is, the EMMC connection is not normally reset. At this time, the server is required to send a reset instruction to the first reset register of the smart accelerator card to ensure that the start mode of the smart accelerator card has been switched to the storage start mode, that is, the purpose of sending the second reset instruction is to ensure that the smart accelerator card can normally operate after the smart accelerator card is booted, and the start mode of the smart accelerator card is switched to the storage start mode, so as to avoid a situation that the smart accelerator card actually changes only the value of the switching mode and does not really switch to the storage start mode.
After receiving the second reset instruction, the first reset register initiates a reset operation to the smart accelerator card, and resets all modules except the predetermined register, that is, the predetermined register prohibits execution of the second reset instruction, thereby avoiding that the control and control of the smart accelerator card cannot be realized on the side of the server after the reset operation is performed on the predetermined register.
It should be noted that each smart accelerator card has a unique address (e.g., a slave address), and can only receive a preset command containing the address. If the addresses in the preset commands among the intelligent accelerator cards conflict, the unique addresses can be dynamically distributed to the intelligent accelerator cards through a system management bus address resolution protocol.
In some embodiments of the present application, the server may further implement health management and control of the smart acceleration card, such as management and control of temperature, frequency, voltage, fan status, and the like of the smart acceleration card.
In some embodiments of the present application, the server obtains the health monitoring information of the smart accelerator card through a system management bus. When the health monitoring information includes information that the intelligent accelerator card has an abnormal health state, for example, when the temperature of a certain intelligent accelerator card is very high and is close to an unhealthy state, the intelligent accelerator card having the abnormal health state is monitored by the HBMSC unit through board management software of the server; when the health value of the intelligent accelerator card in the abnormal health state exceeds a preset threshold value, namely the temperature of the intelligent accelerator card is higher than the preset temperature threshold value, the health monitoring information is packaged into a temperature message, the corresponding intelligent accelerator card is notified through a system management bus, so that after the intelligent accelerator card analyzes the temperature message, a board management soft control DBMSC unit of the intelligent accelerator card is notified to perform abnormal elimination management, such as cooling, control frequency, core number, or control of external fan grade and the like, after the health value is lower than the preset threshold value, namely the requirement of the health state is met, abnormal elimination notification information is sent to a server, and the server updates the health monitoring information according to the received abnormal elimination notification information.
Referring to fig. 6, fig. 6 is a schematic flowchart illustrating another control method for a smart accelerator card according to an embodiment of the present application, where the method is applied to a smart accelerator card; the control method of the smart accelerator card provided in fig. 6 is described in detail with reference to fig. 5, which is as follows:
step S601, receiving a first start mode switching instruction sent by the server, and instructing the predetermined register to switch the start mode to the PCIE start mode according to the first start mode switching instruction.
In some embodiments of the present application, after step S601, the smart acceleration card further receives a first reset instruction sent by the server, instructing the first reset register to perform a reset operation on the smart acceleration card.
Step S602, receiving a preset command sent by the server, switching the start mode to the PCIE start mode according to the preset command, and resuming PCIE communication through the second reset register.
In the embodiment of the application, the smart accelerator card receives the preset command sent by the server, analyzes the preset command, responds correspondingly according to the analysis result, notifies the predetermined register to switch the starting mode to the PCIE starting mode, and resumes PCIE communication through the second reset register.
Step S603, receiving the card version file sent by the server, and storing the card version file.
Step S604, receiving a second start mode switching instruction sent by the server, and instructing the predetermined register to switch the start mode to the storage start mode according to the second start mode switching instruction.
It should be noted that relevant portions in the second embodiment that are not described are the same as the relevant portions in the first embodiment, and are not described again here.
It should be understood that, the sequence numbers of the steps in the foregoing embodiments do not imply an execution sequence, and the execution sequence of each process should be determined by its function and inherent logic, and should not constitute any limitation to the implementation process of the embodiments of the present application.
Based on the control method of the smart accelerator card provided by the above embodiment, the embodiment of the present application further provides an embodiment of an apparatus for implementing the above method embodiment.
Referring to fig. 7, fig. 7 is a schematic diagram of a control device of a smart accelerator card according to an embodiment of the present application. The units are included for performing the steps in the corresponding embodiment of fig. 1. Please refer to fig. 1 for the related description of the corresponding embodiment. For convenience of explanation, only the portions related to the present embodiment are shown. Referring to fig. 7, the control device 7 of the smart accelerator card includes:
an information acquisition unit 71 for acquiring card control information including a card control instruction and a card version file;
a first start mode switching instruction sending unit 72, configured to send a first start mode switching instruction to the smart accelerator card, where the first start mode switching instruction is used to instruct the smart accelerator card to switch a start mode to a PCIE start mode through a predetermined register;
the first card control unit 73 is configured to execute a card control instruction when it is detected that the PCIE bus communication is normal, and send a card version file to the smart accelerator card through the PCIE bus, where the smart accelerator card is in communication connection with the server through the PCIE bus;
a second start mode switching instruction sending unit 74, configured to send a second start mode switching instruction to a predetermined register of the smart accelerator card, where the second start mode switching instruction is used to instruct the smart accelerator card to switch the start mode to the storage start mode through the predetermined register.
Specifically, the address of the predetermined register in the PCIE bus domain is determined by the PCIE base address allocated to the smart accelerator card by the server and the inbound mapping from the PCIE bus domain to the bus protocol predetermined domain of the smart accelerator card.
Preferably, the control device 7 of the smart accelerator card further includes:
and the first reset instruction sending unit is used for sending a reset instruction to a first reset register of the intelligent accelerator card after sending the first starting mode switching instruction to the intelligent accelerator card.
Preferably, the control device 7 of the smart accelerator card further includes:
and the second reset instruction sending unit is used for sending a reset instruction to the first reset register of the intelligent accelerator card after sending the second starting mode switching instruction to the intelligent accelerator card.
Preferably, the predetermined register prohibits execution of the first reset instruction and the second reset instruction.
Preferably, the control device 7 of the smart accelerator card further includes:
the first PCIE communication abnormity management unit is used for sending a preset command to the intelligent accelerator card through the system management bus when detecting that the PCIE bus communication is abnormal, wherein the preset command is used for indicating the intelligent accelerator card to switch the starting mode to the PCIE starting mode and recovering the PCIE communication through the second reset register;
and the second card control unit is used for executing a card control command and sending the card version file to the intelligent accelerator card through the PCIE bus when the starting mode of the intelligent accelerator card is inquired to be switched to the PCIE starting mode and the PCIE communication is recovered to be normal.
Referring to fig. 8, fig. 8 is a schematic diagram of another control device for a smart accelerator card according to an embodiment of the present application. The units are included for performing the steps in the corresponding embodiment of fig. 3. Please refer to the related description of the embodiment in fig. 3. For convenience of explanation, only the portions related to the present embodiment are shown. Referring to fig. 8, the control device 8 of the smart accelerator card includes:
the first starting mode switching instruction receiving and processing unit 81 is configured to receive a first starting mode switching instruction sent by the server, instruct the predetermined register to switch the starting mode to the PCIE starting mode according to the first starting mode switching instruction, and communicatively connect the smart accelerator card and the server through a PCIE bus;
a first card version file receiving unit 82, configured to receive a card version file sent by a server, and store the card version file;
the second starting mode switching instruction receiving and processing unit 83 is configured to receive a second starting mode switching instruction sent by the server, and instruct the predetermined register to switch the starting mode to the storage starting mode according to the second starting mode switching instruction.
Preferably, the control device 8 of the smart accelerator card further includes:
the second PCIE communication abnormity management unit is used for receiving a preset command sent by the server, switching the starting mode to the PCIE starting mode according to the preset command and recovering the PCIE communication through a second reset register;
the second card version file receiving unit is used for receiving the card version file sent by the server and storing the card version file;
and the third starting mode switching instruction receiving and processing unit is used for receiving a second starting mode switching instruction sent by the server and indicating the preset register to switch the starting mode to the storage starting mode according to the second starting mode switching instruction.
It should be noted that, because the contents of information interaction, execution process, and the like between the modules are based on the same concept as that of the embodiment of the method of the present application, specific functions and technical effects thereof may be specifically referred to a part of the embodiment of the method, and details are not described here.
Fig. 9 is a schematic diagram of a server provided in an embodiment of the present application. As shown in fig. 9, the server 9 of this embodiment includes: a processor 90, a memory 91, and a computer program 92, such as a speech recognition program, stored in the memory 91 and operable on the processor 90. The processor 90, when executing the computer program 92, implements the steps in the various smart accelerator card control method embodiments described above, such as steps S101-S104 shown in fig. 1. Alternatively, the processor 90, when executing the computer program 92, implements the functionality of the various modules/units in the various device embodiments described above, such as the functionality of the units 71-74 shown in FIG. 7.
Illustratively, the computer program 92 may be partitioned into one or more modules/units, which are stored in the memory 91 and executed by the processor 90 to accomplish the present application. One or more of the modules/units may be a series of computer program instruction segments capable of performing specific functions, which are used to describe the execution of the computer program 92 in the server 9. For example, the computer program 92 may be divided into an information obtaining unit 71, a first start mode switching instruction sending unit 72, a first card control unit 73, and a second start mode switching instruction sending unit 74, and specific functions of each unit refer to relevant descriptions in the embodiment corresponding to fig. 1, which are not described herein again.
The server may include, but is not limited to, a processor 90, a memory 91. Those skilled in the art will appreciate that fig. 9 is merely an example of a server 9 and does not constitute a limitation of server 9 and may include more or fewer components than shown, or some components in combination, or different components, e.g., the server may also include input-output devices, network access devices, buses, etc.
The Processor 90 may be a Central Processing Unit (CPU), other general purpose Processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field-Programmable Gate Array (FPGA) or other Programmable logic device, discrete Gate or transistor logic, discrete hardware components, etc. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.
The storage 91 may be an internal storage unit of the server 9, such as a hard disk or a memory of the server 9. The memory 91 may also be an external storage device of the server 9, such as a plug-in hard disk, a Smart Media Card (SMC), a Secure Digital (SD) Card, a Flash memory Card (Flash Card), or the like provided on the server 9. Further, the memory 91 may also include both an internal storage unit of the server 9 and an external storage device. The memory 91 is used for storing computer programs and other programs and data required by the server. The memory 91 may also be used to temporarily store data that has been output or is to be output.
Fig. 10 is a schematic diagram of a smart accelerator card provided in an embodiment of the present application. As shown in fig. 10, the smart accelerator card 10 of this embodiment includes: a processor 100, a memory 101, and a computer program 102, such as a speech recognition program, stored in the memory 101 and operable on the processor 100. The processor 100, when executing the computer program 102, implements the steps in the above-described respective control method embodiments of the smart accelerator card, such as the steps S301-S303 shown in fig. 3. Alternatively, the processor 100, when executing the computer program 102, implements the functionality of the various modules/units in the various device embodiments described above, such as the functionality of the units 81-83 shown in FIG. 8.
Illustratively, the computer program 102 may be partitioned into one or more modules/units, which are stored in the memory 101 and executed by the processor 100 to accomplish the present application. One or more of the modules/units may be a series of computer program instruction segments capable of performing specific functions, which are used to describe the execution of the computer program 102 in the smart accelerator card 10. For example, the computer program 102 may be divided into a first start mode switching instruction receiving and processing unit 81, a first card version file receiving unit 82, and a second start mode switching instruction receiving and processing unit 83, and specific functions of each unit are described with reference to the relevant description in the embodiment corresponding to fig. 1, which is not repeated herein.
The smart accelerator card 10 may include, but is not limited to, a processor 100, a memory 101. Those skilled in the art will appreciate that FIG. 10 is merely an example of a smart accelerator card 10 and is not intended to limit the smart accelerator card 10 and may include more or less components than those shown, or some components in combination, or different components, for example, the smart accelerator card may also include input output devices, network access devices, buses, etc.
The Processor 100 may be a Central Processing Unit (CPU), other general purpose Processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), an off-the-shelf Programmable Gate Array (FPGA) or other Programmable logic device, discrete Gate or transistor logic, discrete hardware components, etc. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.
The memory 101 may be an internal storage unit of the smart accelerator card 10, such as a hard disk or a memory of the smart accelerator card 10. The memory 101 is used for storing computer programs and other programs and data required by the smart accelerator card. The memory 101 may also be used to temporarily store data that has been output or is to be output.
The embodiment of the application also provides a computer readable storage medium, a computer program is stored in the computer readable storage medium, and the control method of the intelligent accelerator card can be realized when the computer program is executed by a processor.
The embodiment of the present application provides a computer program product, which when running on a server, enables the server to implement the control method of the smart acceleration card described in the above-mentioned fig. 1 when executed, or enables the server to implement the control method of the smart acceleration card described in the above-mentioned fig. 3 when executed on the smart acceleration card.
It will be apparent to those skilled in the art that, for convenience and brevity of description, only the above-mentioned division of the functional units and modules is illustrated, and in practical applications, the above-mentioned function distribution may be performed by different functional units and modules according to needs, that is, the internal structure of the apparatus is divided into different functional units or modules, so as to perform all or part of the functions described above. Each functional unit and module in the embodiments may be integrated in one processing unit, or each unit may exist alone physically, or two or more units are integrated in one unit, and the integrated unit may be implemented in a form of hardware, or in a form of software functional unit. In addition, specific names of the functional units and modules are only for convenience of distinguishing from each other, and are not used for limiting the protection scope of the present application. The specific working processes of the units and modules in the system may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.
In the above embodiments, the descriptions of the respective embodiments have respective emphasis, and reference may be made to the related descriptions of other embodiments for parts that are not described or illustrated in a certain embodiment.
Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.
The above-mentioned embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present application and are intended to be included within the scope of the present application.

Claims (10)

1. A control method of an intelligent accelerator card is applied to a server and is characterized by comprising the following steps:
obtaining card control information, wherein the card control information comprises a card control instruction and a card version file;
sending a first starting mode switching instruction to the intelligent accelerator card, wherein the first starting mode switching instruction is used for instructing the intelligent accelerator card to switch a starting mode to a PCIE starting mode through a preset register;
when detecting that the PCIE bus communication is normal, executing the card control command, and sending a card version file to the intelligent accelerator card through the PCIE bus, wherein the intelligent accelerator card is in communication connection with the server through the PCIE bus;
and sending a second starting mode switching instruction to a preset register of the intelligent accelerator card, wherein the second starting mode switching instruction is used for instructing the intelligent accelerator card to switch the starting mode to the storage starting mode through the preset register.
2. The method as claimed in claim 1, wherein the address of the predetermined register in the PCIE bus domain is determined by the PCIE base address allocated to the smart accelerator card by the server and the inbound mapping from the PCIE bus domain to the bus protocol predetermined domain of the smart accelerator card.
3. The control method of the smart accelerator card according to claim 1 or 2, wherein after the sending of the first start mode switching instruction to the smart accelerator card, the method further comprises:
and sending a reset instruction to a first reset register of the intelligent accelerator card.
4. The control method of the smart accelerator card according to claim 3, wherein after the sending of the second start mode switching instruction to the predetermined register of the smart accelerator card, the method comprises:
and sending a reset instruction to a first reset register of the intelligent accelerator card.
5. The control method of a smart accelerator card according to claim 4, wherein the predetermined register prohibits execution of the reset instruction.
6. The method for controlling a smart accelerator card according to claim 1, wherein when the smart accelerator card is further communicatively connected to the server via a system management bus, after the sending of the first start mode switching instruction to the smart accelerator card, the method further comprises:
when detecting that the PCIE bus communication is abnormal, sending a preset command to the intelligent accelerator card through a system management bus, wherein the preset command is used for indicating the intelligent accelerator card to switch a starting mode to a PCIE starting mode and recovering the PCIE communication through a second reset register;
and when the starting mode of the intelligent accelerator card is inquired to be switched to the PCIE starting mode and the PCIE communication is recovered to be normal, executing the card control command and sending a card version file to the intelligent accelerator card through the PCIE bus.
7. A control method of an intelligent accelerator card is applied to the intelligent accelerator card and is characterized by comprising the following steps:
receiving a first starting mode switching instruction sent by a server, and indicating a predetermined register to switch a starting mode to a PCIE starting mode according to the first starting mode switching instruction, wherein the intelligent accelerator card is in communication connection with the server through a PCIE bus;
receiving a card version file sent by the server and storing the card version file;
and receiving a second starting mode switching instruction sent by the server, and instructing the preset register to switch the starting mode to the storage starting mode according to the second starting mode switching instruction.
8. A server comprising a processor, a memory, and a computer program stored in the memory and executable on the processor, the processor implementing the method of any one of claims 1 to 6 when executing the computer program.
9. A smart accelerator card comprising a processor, a memory, and a computer program stored in the memory and executable on the processor, the processor implementing the method of claim 7 when executing the computer program.
10. A computer-readable storage medium, in which a computer program is stored which, when being executed by a processor, carries out the method according to any one of claims 1 to 7.
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