CN115167935A

CN115167935A - Software dynamic function reconstruction information processing method based on domestic DSP

Info

Publication number: CN115167935A
Application number: CN202210713837.5A
Authority: CN
Inventors: 史学鹏; 董澍; 李凤伟; 张愉娇
Original assignee: Beijing Ai Sihang Technology Service Co ltd
Current assignee: Beijing Ai Sihang Technology Service Co ltd
Priority date: 2022-06-22
Filing date: 2022-06-22
Publication date: 2022-10-11

Abstract

The invention relates to the technical field of embedded and data processing, in particular to a software dynamic function reconstruction information processing method based on a domestic DSP (digital signal processor), and provides a solution for the problem of conflict between software multifunctional requirements and hardware resource overhead in the existing embedded information processing system. The method includes a DSP processor and a data storage device. The DSP processor is internally designed with a reconfiguration control module, has the capability of dynamically reconfiguring software functions, determines the structure of the function module according to different tasks on the basis of stable and unchangeable control system framework, allocates the structure to the processor core in real time, and completes dynamic loading and unloading of application software and time-sharing multiplexing of hardware resources, thereby achieving optimal configuration of resources.

Description

Software dynamic function reconstruction information processing method based on domestic DSP

Technical Field

The invention relates to the technical field of embedded and data processing, in particular to a software dynamic function reconfiguration information processing method based on a domestic DSP.

Background

With the continuous richness of application scenes of airborne and missile-borne embedded information processing systems, the service logic of the embedded information processing systems is increased, the improvement of system efficiency and the increased hardware resource overhead cannot be effectively balanced by simply increasing the number of the same kind of processors for the conversion of external environments and specific task requirements.

Disclosure of Invention

The invention provides a software dynamic function reconstruction information processing method based on a domestic DSP (digital signal processor), aiming at the problem of conflict between software multifunctional requirements and hardware resource overhead in the existing embedded information processing system.

In order to solve the technical problems, the invention adopts the technical scheme that:

a software dynamic function reconstruction information processing method based on a domestic DSP comprises a monitoring module, an application module, a reconstruction control module and data storage equipment. The monitoring module is a basic framework of the information processing software system and is used for completing system state supervision before application program loading or after application program unloading. The application module is an application component selected according to an external instruction and used for completing a corresponding task. The reconstruction control module is used for receiving a reconstruction instruction of the external system host, reading and analyzing a corresponding reconstruction data file and a configuration file, unloading and loading the software function of the DSP processor, and completing time-sharing multiplexing of system resources according to tasks. The data storage device comprises a nonvolatile memory Flash and a large-capacity storage medium DDR which are respectively used for program solidification and data caching. The system is provided with a set of upper computer software for instruction interaction and data issuing.

According to the software dynamic function reconfiguration information processing method based on the DSP, a dynamic reconfiguration controller is designed in the DSP according to the DSP and a data storage device, the task running states of a plurality of cores in the DSP are controlled, and the cores realize inter-core communication through a shared memory and semaphore.

The invention has the advantages that: the invention can realize the dynamic loading and unloading of application software according to different application scenes or task requirements under a set of stable basic control framework, completes the time-sharing multiplexing of system resources, achieves the flexible reconfiguration design of functions, ensures that the system functions are easy to expand, and can quickly complete the function addition for new function requirements in the future.

Drawings

FIG. 1 is an overall block diagram of the present invention

FIG. 2 is a schematic diagram of the DSP dynamic reconfiguration process of the present invention

Detailed Description

The present invention will be described in further detail with reference to the following detailed description and accompanying drawings. The overall block diagram of the invention of fig. 1 includes a DSP processor and a data storage device. The DSP information processing system includes: the monitoring module, the application module and the reconstruction control module are communicated with the outside through an EMIF and SRIO high-speed interface. Data storage devices include Flash and DDR storage devices. Wherein:

and the monitoring module is used for finishing system state monitoring before the application program is loaded or after the application program is unloaded.

And the application module is used for completing corresponding tasks according to the application components selected by the external instruction.

And the reconstruction control module is used for receiving a reconstruction instruction of the external system host, reading and analyzing the corresponding reconstruction data file and the configuration file, and completing the unloading and loading of the software function of the DSP processor.

And the non-volatile memory Flash is used for storing the monitoring program and the application component after the power failure of the equipment and reading and operating after the next system power-on.

And the large-capacity storage medium DDR is used for caching key data in the operation process.

The DSP chip adopted in the specific example adopts a FT-M6678 domestic DSP chip of Galaxy Feiteng company. The high-speed interface is connected with a system host through a CPS1848 switching chip by using SRIO on the chip to carry out data interaction, the communication rate adopts a 3.125GHz4x mode, and the transaction type uses NWRITE and Doorbell. The low-speed interface is connected with an external RS-422 through an FPGA by using EMIF on a chip, the width 16bit of the CE0 space memory is configured, and a WE gating mode is adopted. The data cache uses 4 pieces of DDR3, the model is MT41K256M16HA-125IT, the cache capacity reaches 512MB, and the size of the data cache is met. And the program is solidified by using FLASH, the FLASH adopts Shenzhen national micro SH25QU256HX chip and is connected with the DSP through an SPI interface, and the capacity is 32MB. FIG. 2 is a flow chart of a DSP information processing system dynamic reconfiguration work. After a system is powered on, a DSP board card is cold started, all peripheral equipment enters a default state to start boot initialization work, boot codes RBL (ROM boot loader) stored in a solidified ROM in a DSP processor are automatically read at first, then a loading mode is read according to DEVSTAT register information, the peripheral equipment is restarted, and all peripheral equipment clocks required to be used in the boot process are enabled. And in the SPI Flash starting mode, the RBL loads a monitoring program mirror image from the mounting Flash to the DSP memory through an SPI interface and skips to a program entry address to run a program. After the program starts to run, peripheral initialization and system self-test are firstly carried out. After receiving the reconstruction instruction, firstly analyzing the reconstruction instruction, selecting an application component to be updated or added, loading the received updated file image to a corresponding data buffer area, solidifying the image to a corresponding address of Flash, and finishing reconstruction. After reconstruction is completed or when a reconstruction instruction is not received, the system analyzes according to the received external task instruction, reads an application component corresponding to the task from Flash, loads the application component into a data buffer area, analyzes information such as entry addresses of core programs in the application component according to the Boot Parameter Table of the image file, triggers interruption of the IPC by the 0 core, starts the running of the slave core program, and finally completes program skipping of the 0 core. And after the function execution of each core application component is finished, the 0 core jumps to the monitoring program entry address to restore the operation of the monitoring module, and the rest of the cores jump to the reset starting address (0 x20B 00000) to finish the unloading of the application program.

Claims

1. A software dynamic function reconfiguration information processing method based on a domestic DSP is characterized by comprising a DSP processor and an external data storage device, wherein the DSP processor internally comprises a monitoring module, an application module and a reconfiguration control module;

the monitoring module is a basic framework of the information processing system and is used for completing system state supervision before application program loading or after application program unloading.

The application module is an application component selected according to an external instruction and used for completing a corresponding task.

The reconstruction control module is used for receiving a reconstruction instruction of the external system host, reading and analyzing a corresponding reconstruction data file and a configuration file, and completing the unloading and loading of the software function of the DSP processor.

The external data storage device is used for program solidification and data caching.

2. The method for processing software dynamic function reconfiguration information according to claim 1, wherein a dynamic reconfiguration controller is designed inside a DSP processor to control the task running states of a plurality of cores inside the DSP, inter-core communication is realized between cores through shared memory and semaphore, and system functions are easy to expand.

3. The method for processing software dynamic function reconfiguration information according to claim 1, wherein the monitoring module automatically boots for the first time after the device is powered on through an internal RBL, and after receiving a reconfiguration instruction, the reconfiguration control module boots the system for the second time according to an application component stored in Flash, and jumps to an application program entry address running program.