CN106055405B

CN106055405B - Memory sharing processor based on programmable microcode and reconstruction method thereof

Info

Publication number: CN106055405B
Application number: CN201610340406.3A
Authority: CN
Inventors: 邹卓; 马宁; 环宇翔; 郑立荣
Original assignee: Silicon Charm Information Technology (shanghai) Co Ltd
Current assignee: Silicon Charm Information Technology (shanghai) Co Ltd
Priority date: 2016-04-20
Filing date: 2016-05-23
Publication date: 2020-03-24
Anticipated expiration: 2036-05-23
Also published as: CN106055405A

Abstract

The invention discloses a memory sharing processor based on programmable microcode, which comprises a Register (ROM), a readable and writable memory (RAM) and a decoder for memory management configuration, wherein the Register (ROM) of the processor stores general microcode instructions, the readable and writable memory (RAM) of the processor shares and stores an application program and customized microcode instructions, and the size of the space occupied by the application program and the customized microcode instructions in the readable and writable memory (ROM) is distributed and adjusted according to needs. The step of utilizing the processor to carry out memory reconstruction mainly comprises the steps of utilizing a decoder to carry out a managing and distributing unit on the RAM again, configuring the unit and loading a micro-code instruction combination into the RAM. The invention distributes the memory size and the program memory size required by the microcode according to the requirement by sharing the microcode memory and the memory of the application program, thereby greatly improving the application efficiency of the RAM.

Description

Memory sharing processor based on programmable microcode and reconstruction method thereof

Technical Field

The invention belongs to the technical field of processor design, in particular to a memory sharing processor based on programmable microcode and a reconstruction method thereof, aiming at the design and optimization of memory allocation and efficient operation of a processor stored with the programmable microcode.

Background

Microcode refers to an abstraction layer of the hardware structure of a processor, which generally resides in the high-speed memory of the processor and can directly control the logic resources of the processor to ensure the normal operation of the initial startup state of the processor. Since microcode is usually designed in embedded processors and systems on chip (SoC) and resides in core logic, it has the advantages of direct control of processor logic operation, high energy efficiency, low power consumption, and high code density. Processors embedded with micro-codes are widely applied to intelligent products such as internet of things, sensor networks and industrial control, which have strict requirements on energy consumption, cost and performance. The microcode instruction is generally stored in a ROM (read only memory) of the processor, that is, when the chip is designed, manufactured and generated, the microcode instruction is solidified in the processor to be started and run; there are also some microcode instructions stored in the processor RAM (readable and writable memory), but these are usually some customizable operation commands, or microcode upgrade update instruction sets, which store more errant instructions to implement the correction of code errors in ROM.

The existing internet of things and mobile internet are evolving towards specialization and customization in intelligent control application, and the intelligent network processor faces shorter and shorter time-to-market periods (time-to-market), more and more embedded processors carry out bottom-layer logic reconstruction on the traditional general processor by using programmable microcode, and carry out special microcode customization according to the application specificity, namely the reconfigurable processor design based on the programmable microcode is formed. The processor loads different microcode program combinations through analysis of application programs and resource consumption, so that the efficiency and the performance of processing different tasks by the processor are improved. In order to implement reconfigurability of the processor, memory allocation needs to be performed in the processor according to different microcode program (microprogram) conditions, and RAM space of the processor is reserved for the processor according to the fact that the processor runs a microcode instruction set combination which executes the most number under bad conditions. Taking an IM3000/FC3180 embedded processor as an example, the processor is reserved for the reconfigurable microcode program memory to account for more than 30% of the storage capacity of a chip. However, when the processor works for different applications or tasks, the demand for the memory of the microcode program varies greatly, and when the processor can accommodate the external code program with less memory capacity, the fixed reservation of 30% of the memory will result in the waste of the valuable memory of the processor, and also cause the reduction of the memory utilization rate of the microcode program. FIG. 1 is a diagram illustrating the allocation of a conventional microcode program in a processor memory. As shown, in the chip processor, 40K of space is always reserved in the RAM for storing the configurable microcode. In fact, when there are fewer microcode commands to be configured, 40KB of space is wasted, and these memory cells cannot be used by the application; when the application is complex, 40KB of space is more strained. How to design a new processor memory reconstruction reduces the waste of the memory and improves the memory use efficiency, which is an urgent problem to be solved by the processor design.

Disclosure of Invention

The invention aims to solve the defect of low utilization efficiency of a microcode memory of a reconfigurable processor based on a programmable microcode, and the memory size required by the microcode and the memory size of an application program are distributed as required by adopting a method of sharing the microcode memory and the application program memory.

In order to achieve the technical purpose, the invention adopts the technical scheme that: a memory sharing processor based on programmable microcode comprises a read-only memory (ROM), a read-write memory (RAM), a decoder for memory management configuration and an I/O management unit, wherein the read-only memory (ROM) of the processor stores general microcode instructions, the read-write memory (RAM) of the processor stores application programs and customized microcode instructions in a shared mode, and the space occupied by the application programs and the customized microcode instructions in the read-write memory (RAM) is distributed and adjusted according to needs.

The decoder and the I/O management unit are configurable modules, and configure parameters thereof through a specially designed memory manager, where the configuration parameters include memory size for an application program or microcode and respective address ranges (in block units), the decoder performs corresponding decoding work by distinguishing microcode addresses from program addresses, and the I/O management unit is responsible for reading the microcode and the application program stored in the RAM.

The input/output interface of the RAM connects the read data correctly to the control bus and the data bus via the I/O management unit. The control bus and the data bus are connected with the logic unit of the chip, and the instruction data transmitted on the bus controls the logic unit of the chip.

In the processor based on the programmable microcode, the readable and writable storage unit is used for storing the programmable microcode instruction set, and the system can load different microcode instruction sets according to different applications; the processor statically or dynamically allocates the size of the microcode memory and the size of the program memory according to different application scenes; after the processor is powered on or in operation, self-analysis is carried out according to a peripheral instruction or an application scene, and memory space for microcode and an application program is allocated; the size of the allocated space and the block address configure the memory allocation management unit by using the memory allocation register. The memory allocation management unit carries out address decoding on the micro-code address and the program address so as to adapt to the reconfigurable memory function unit and the memory output interface and correctly output the control word or the program of the corresponding data output micro-code.

The method for reconstructing the memory by using the memory sharing processor based on the programmable microcode comprises the following steps: (1) after starting up or in operation, self-checking whether the current universal microcode meets the requirements; (2) if the requirement is met, the memory reconstruction is not carried out; if the requirements are not met, the microcode instruction is initialized again after the current state is saved; (3) selecting a new combination of microcode instructions; (4) a decoder is used for managing the RAM again and allocating the units, and the units are configured; (5) loading a microcode instruction combination into RAM; (6) and restarting the operation. The decoder in step (4) allocates memory size and address range (block as unit) to the application program and the microcode as required, and then performs corresponding decoding work by distinguishing the microcode address and the program address, and reads the microcode and the application program stored in the RAM.

The technical scheme of this application's main effect lies in: (1) the processor is reconstructed through the programmable microcode, so that different application scenes and services are optimized, and the operation efficiency is improved; (2) dynamic optimization on demand is realized by selecting different microcode instruction combinations; (3) the core advantage is that the dynamic allocation of the microcode memory space and the program memory space is realized through the dynamic management of the RAM, and the application efficiency of the RAM is greatly improved.

Drawings

FIG. 1 is a diagram of the allocation of a conventional microcode program in processor memory (for example, IM3000/FC 3180);

FIG. 2 is a schematic diagram illustrating the allocation of microcode programs in the memory of a processor according to the present invention;

FIG. 3 is a decoder managing microcode/applications in processor memory;

FIG. 4 is a flow chart of processor memory reconfiguration according to the present application;

FIG. 5 is a schematic diagram of memory usage of a FC3180/IM3000 processor according to the present disclosure;

fig. 6 is a schematic diagram of memory address allocation of the FC3180/IM3000 processor according to the present invention:

Detailed Description

For more clear explanation of the technical solution of the present application, the following description is made with reference to the accompanying drawings and specific examples: as shown in fig. 1, the memory sharing processor based on programmable microcode of the present application includes a read-only memory (ROM), a read-write memory (RAM), and a decoder and an I/O management unit for memory management configuration, where the read-only memory (ROM) of the processor stores general microcode instructions, the read-write memory (RAM) of the processor stores application programs and customized microcode instructions in a shared manner, and the size of the space occupied by the application programs and the customized microcode instructions in the read-write memory (RAM) is allocated and adjusted as needed. It can be seen that the application and the customized microcode share 128K of memory space, and the proportion of the memory occupied by them is adjusted and changed as required, thereby improving the utilization efficiency of the memory. Fig. 3 shows a process of managing the microcode/application program in the memory of the processor by the decoder, as shown in fig. 3, the decoder is a configurable module, the configuration parameters include the memory size for the application program or the microcode and their respective address ranges (in block), and the decoder performs corresponding decoding work by distinguishing the microcode address from the program address, and reads the microcode and the application program stored in the RAM. And then the read data is correctly connected to the control bus and the data bus through the management unit. FIG. 4 is a flow chart of memory reconfiguration for a processor, the process steps of which are: (1) after starting up or during running, self-checking whether the current universal microcode meets the requirements; (2) if the requirement is met, the memory reconstruction is not carried out; if the requirements are not met, the microcode instruction is initialized again after the current state is saved; (3) selecting a new combination of microcode instructions; (4) a decoder is used for managing the RAM again and allocating the units, and the units are configured; (5) loading a microcode instruction combination into RAM; (6) and restarting the operation. Fig. 5 and 6 illustrate memory usage and address allocation states for an FC3180/IM3000 processor incorporating memory sharing functionality. An 80-bit (10Bytes) microcode control word and an 8-bit (1byte) program bus are used, and a 128kB SRAM is used as a shared memory. The 128kBSRAM takes 16kB as one block, the total number is 8 blocks, and the width of each block is 16-byte (128bits)/word (namely, each block has 1k X16 bytes). The use of each block of memory is defined by the configuration registers MCMR [0:7] of the memory allocation management unit. In the left diagram of fig. 5, when one of the memories is used for microcode, the first 10bytes ═ 80bits are used for storing microcode, the last 6bytes are blank (the microcode can have any width according to different processor control buses), and the right diagram is the case where all memories are used for storing microcode. The three columns in FIG. 6 correspond to: all contents of MCMR [0:8] ═ 0 are used for applications, MCMR [0:8] ═ 16 blocks 0-3(0-3Block) are used for microcode, others are used for applications and MCMR [0:8] ═ 256 memory is used for microcode memory and address allocation.

The above description is only a preferred embodiment of the present invention, and should not be taken as limiting the scope of the invention, which is intended to cover any modifications, equivalents, and simple improvements made in the spirit of the present invention.

Claims

1. A memory sharing processor based on programmable microcode comprises a read-only memory ROM, a read-write memory RAM, a decoder for memory management configuration and an I/O management unit, and is characterized in that the read-only memory ROM of the processor stores general microcode instructions, the read-write memory RAM of the processor shares and stores application programs and customized microcode instructions, and the space occupied by the application programs and the customized microcode instructions in the read-write memory RAM can be distributed and adjusted according to needs; the decoder and the I/O management unit are configurable modules, parameters of the I/O management unit are configured through a storage manager, the parameters comprise the memory size used for an application program or a microcode and respective address ranges of the memory size and the address ranges, the address ranges take block as a unit, the decoder performs corresponding decoding work by distinguishing microcode addresses and program addresses, and the I/O management unit is responsible for reading the microcode and the application program stored in the RAM.

2. The memory sharing processor based on programmable microcode of claim 1, wherein the input/output interface of the memory RAM is capable of transferring the read data to the control bus and the data bus via the I/O management unit.

3. The memory sharing processor based on programmable microcode of claim 2, wherein the control bus and the data bus are connected to the chip logic unit, and the instruction data transmitted on the bus controls the chip logic unit.

4. The method for performing memory reconfiguration using a programmable microcode-based memory sharing processor of claim 1, wherein the memory reconfiguration step is: (1) after starting up or receiving related instructions, self-checking whether the current universal micro-code meets the requirements; (2) if the requirement is met, the memory reconstruction is not carried out; if the requirements are not met, the microcode instruction is initialized again after the current state is saved; (3) selecting a new combination of microcode instructions; (4) a decoder is used for managing and allocating the units again for the RAM, and the units are configured; (5) loading the micro-code instruction combination into a read-write memory RAM; (6) and restarting the operation.

5. The method according to claim 4, wherein the decoder in step (4) allocates memory size and address range to the application program and the microcode as required, and the address range takes block as a unit, and performs corresponding decoding work by distinguishing the microcode address from the program address, so as to read the microcode and the application program stored in the RAM.