CN111124499B - Processor compatible with multi-instruction system and operation method thereof - Google Patents
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- CN111124499B CN111124499B CN201911157061.8A CN201911157061A CN111124499B CN 111124499 B CN111124499 B CN 111124499B CN 201911157061 A CN201911157061 A CN 201911157061A CN 111124499 B CN111124499 B CN 111124499B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3824—Operand accessing
- G06F9/383—Operand prefetching
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
- G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
- G06F9/384—Register renaming
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3867—Concurrent instruction execution, e.g. pipeline, look ahead using instruction pipelines
- G06F9/3869—Implementation aspects, e.g. pipeline latches; pipeline synchronisation and clocking
Abstract
The invention provides a processor compatible with a multi-instruction system and an operation method thereof, wherein the processor comprises the following steps: the programmable decoding component is used for decoding the instruction to be executed into a micro-operation code according to a preprogrammed instruction system; the execution component is used for executing the micro operation code by reading and writing the data cache to obtain an execution result; and the write-back and submission component is used for finishing the execution of the instruction after the execution result is written back and submitted. The invention can efficiently realize that the same processor is compatible with a plurality of different instruction systems with lower hardware cost.
Description
Technical Field
The present invention relates to the field of processor (CPU) design, and more particularly, to a processor compatible with a multiple instruction system and an operating method thereof.
Background
Existing processors are all implemented by full hardware, and generally adopt a pipeline structure, as shown in fig. 1, including main components such as instruction fetching, decoding, register renaming, dispatching, transmitting, executing, write-back, and committing. The instruction fetching component reads an instruction from the instruction cache, and forms a subsequent component executable micro-operation code after decoding and register renaming, the execution component executes the micro-operation code and may read and write the data cache, and the dispatching is to store the instruction micro-operation after decoding and register renaming into an emission queue to wait for emission; the transmission is to select the instruction micro-operation satisfying the execution condition from the transmission queue to the execution unit for execution. The dispatch unit and the issue unit share an instruction micro-operation issue queue. The write-back and submission component completes the write-back of the data and ends the execution of the instruction, wherein the write-back is to write back a result generated by the execution of the instruction micro-operation to the register. Commit is a confirmation that the result of the instruction's write back to the register has been validated and will not be cancelled. In an out-of-order execution processor pipeline, operations that an instruction micro-operation does before the commit stage (including the writeback stage) are likely to be speculative and are likely to be cancelled because of speculative errors. The commit phase is a confirmation phase from out of order back to order. Only really executed instructions will reach the commit phase.
Existing processors implement a specific instruction system in hardware, such as an X86 instruction system, an ARM instruction system, and an MIPS instruction system. In order to maintain the compatibility of previous software, the same processor is usually compatible with subsystems of different time periods of the same instruction system, such as an X86-64 instruction system and an IA32 instruction system (32-bit X86 instructions), and an ARM64 instruction system and an ARM32 instruction system.
The current processors can only realize one appointed instruction system, such as an X86 instruction system realized by an X86 processor, an ARM instruction system realized by an ARM processor, an MIPS instruction system realized by an MIPS processor, a RISCV instruction system realized by an RISCV processor, and the like; or subsystems compatible with different time versions of the same instruction system, such as an X86-64 instruction system and an IA32 instruction system (32-bit X86 instruction), and an ARM64 instruction system and an ARM32 instruction system. However, the same processor is not hardware compatible with different instruction systems, such as an X86 processor cannot hardware execute the MIPS instruction system or the ARM instruction system, and vice versa. The compatibility with different instruction systems can only be realized by adopting a software binary translation mode and running virtual machine software simulating other instruction systems on a native processor, so that the efficiency is very low.
Disclosure of Invention
The invention aims to solve the defect that the same processor can be efficiently compatible with a plurality of different instruction systems, and provides a design method and a system of a processor compatible with a multi-instruction system based on a software programmable decoding component.
Specifically, the present invention provides a processor compatible with multiple instruction systems, comprising:
the programmable decoding component is used for decoding the instruction to be executed into a micro-operation code according to a preprogrammed instruction system;
the execution component is used for executing the micro operation code by reading and writing the data cache to obtain an execution result;
and the write-back and submission component is used for finishing the execution of the instruction after the execution result is written back and submitted.
The processor compatible with the multi-instruction system further comprises:
and the micro-operation code cache is used for storing the micro-operation codes generated by decoding of the programmable decoding component for subsequent reading and execution of the execution component.
The processor compatible with the multi-instruction system comprises the following instruction systems: an X86 instruction system or an ARM instruction system or a MIPS instruction system or other instruction systems.
The processor compatible with the multiple instruction system, wherein the programmable decoding unit comprises: the device comprises an instruction cache interface, an execution component, a decoding program cache, a decoding data cache, a micro-operation code cache interface and a subsequent pipeline synchronization interface;
the instruction cache interface is used for connecting and accessing an instruction cache of the processor;
the decoding program cache is used for storing the decoding program of the current instruction system;
the decoding data buffer is used for temporarily storing data generated or operated by a decoding program;
the micro-operation code cache interface is used for connecting and accessing the micro-operation code cache;
the subsequent pipeline synchronous interface is used for receiving a feedback signal of a subsequent pipeline component;
the execution unit is used for executing the decoding program in the decoding program cache, finishing the decoding of the fetched instruction and the register renaming operation through the instruction cache interface fetching, generating the micro-operation code, writing the micro-operation code into the cache through the micro-operation code cache interface, simultaneously reading the signal or the message of the subsequent pipeline synchronous interface, and updating the execution path of the decoding program according to the synchronous signal or the message, thereby changing the instruction flow execution path of the whole processor.
The invention also provides a processor operation method compatible with the multi-instruction system, which comprises the following steps:
step 1, decoding an instruction to be executed into a micro-operation code through a programmable decoding component according to a preprogrammed instruction system;
step 2, reading and writing data cache through an execution component, and executing the micro operation code to obtain an execution result;
and 3, after the execution result is written back and submitted by the write-back and submission component, finishing the execution of the instruction.
The processor operation method compatible with the multi-instruction system, wherein the step 1 further comprises:
the micro-operation code generated by decoding of the programmable decoding component is stored through the micro-operation code cache for the subsequent execution component to read and execute.
The processor operation method compatible with the multi-instruction system is as follows: an X86 instruction system or an ARM instruction system or a MIPS instruction system or other instruction systems.
The method for operating a processor compatible with a multi-instruction system comprises the following steps: the device comprises an instruction cache interface, an execution component, a decoding program cache, a decoding data cache, a micro-operation code cache interface and a subsequent pipeline synchronization interface;
the instruction cache interface is used for connecting and accessing an instruction cache of the processor;
the decoding program cache is used for storing the decoding program of the current instruction system;
the decoding data buffer is used for temporarily storing data generated or operated by a decoding program;
the micro-operation code cache interface is used for connecting and accessing the micro-operation code cache;
the subsequent pipeline synchronous interface is used for receiving a feedback signal of a subsequent pipeline component;
the execution unit is used for executing the decoding program in the decoding program cache, finishing the decoding of the fetched instruction and the register renaming operation through the instruction cache interface fetching instruction, generating the micro-operation code, writing the micro-operation code into the cache through the micro-operation code cache interface, simultaneously reading the signal or the message of the subsequent pipeline synchronous interface, and updating the execution path of the decoding program according to the synchronous signal or the message, thereby changing the instruction stream execution path of the whole processor.
According to the scheme, the invention has the advantages that:
because the fetch, decode, register rename and other parts occupy little resources in modern processors, the use of a special decode processor instead of the above three parts does not increase too much hardware resource overhead. Meanwhile, the capacity of the micro-operation code cache can be controlled in a smaller range. The micro-operation code cache isolates the decoding processor from the subsequent pipeline component, so that the execution of the subsequent component is only related to the access of the micro-operation code cache, and the execution efficiency of the subsequent execution component can be effectively maintained. Therefore, the invention can efficiently realize that the same processor is compatible with a plurality of different instruction systems with less hardware cost.
Drawings
FIG. 1 is a diagram of a prior art pipeline-based micro-architecture of a processor;
FIG. 2 is a schematic diagram of a processor design of the present invention;
FIG. 3 is a functional diagram of a decoding processor according to the present invention.
Detailed Description
The micro-architecture and the function of the processors of the existing different instruction systems are very similar. As shown in fig. 1, all the components adopt a pipeline structure, functions of each part of the pipeline are the same and different, and the largest difference is a decoding component. The decoding parts of different processors realize the instruction decoding of different instruction systems, which are different from each other. Since the decode units are hardware implemented, they cannot be dynamically altered, which results in the processor implementing a given instruction system not being hardware compatible with other instruction systems. However, if the decoding component is implemented in a software programmable manner, the processor of another instruction system can be switched to without influencing the execution efficiency of the processor as long as the decoding software of the software decoding component is updated.
The invention comprises the following key points:
the key point 1 is that a decoding component based on software programming is realized by adopting a special processor (hereinafter called a decoding processor), replaces the instruction fetching, decoding and register renaming components of the existing processor, and can realize the compatibility to a multi-instruction system by replacing a decoding program;
the key point 2, the decoding processor has its own program buffer, data buffer and executive component, can realize the fetch of multiple instruction systems, decode and register renaming through the way of software programming, produce the micro-operation code that the subsequent assembly line part can carry out;
the key point 3, the decoding processor interacts with the subsequent assembly line component through a micro-operation code cache, and the micro-operation code generated by the instruction decoding is stored in the micro-operation code cache for the subsequent assembly line component to read and execute;
and 4, the subsequent pipeline part transmits a feedback signal to the decoding processor through a synchronization mechanism, so that the decoding processor can change the instruction stream to be executed in time and manage the micro-operation code cache. For example, after a branch instruction or a function call instruction is executed, the execution order of the original instruction stream is changed, and a jump is required to another instruction address to start the execution of a new instruction stream. This information must be communicated to the decode processor in time, via the synchronization mechanism, to fetch instructions starting at the new instruction address, otherwise the decode processor will continue to execute along the original instruction stream.
In order to make the aforementioned features and effects of the present invention more comprehensible, embodiments accompanied with figures are described in detail below.
FIG. 2 is a schematic diagram of a multiple instruction system compatible processor design employing a software translation processor. Compared with fig. 1, the fetch unit, decode unit and register renaming unit in the original processor are replaced by a special decode processor. And a micro-operation code buffer is added between the decoding processor and the transmitting part at the back end of the pipeline.
Fig. 3 is a functional diagram of a decoding processor, which mainly includes six parts: the system comprises an instruction cache interface, an execution unit, a decoding program cache, a decoding data cache, a micro-operation code cache interface and a subsequent pipeline synchronization interface. The instruction cache interface is connected with and accesses an instruction cache of the processor, the decoding program cache stores a decoding program of a current instruction system, the decoding data cache is used for temporarily storing data generated or operated by the decoding program, the micro-operation code cache interface is connected with and accesses the micro-operation code cache, and the subsequent pipeline synchronization interface receives a feedback signal of a subsequent pipeline component. The execution part executes the decoding program in the decoding program cache, fetches the instruction through the instruction cache interface, completes the decoding of the fetched instruction and the register renaming operation, generates a micro-operation code, writes the micro-operation code into the cache through the micro-operation code cache interface, simultaneously reads the signal or the message of the subsequent pipeline synchronous interface, and updates the execution path of the decoding program according to the synchronous signal or the message, thereby changing the instruction flow execution path of the whole processor.
The following are method examples corresponding to the above system examples, and this embodiment mode can be implemented in cooperation with the above embodiment modes. The related technical details mentioned in the above embodiments are still valid in this embodiment, and are not described herein again in order to reduce repetition. Accordingly, the related-art details mentioned in the present embodiment can also be applied to the above-described embodiments.
The invention also provides a processor operation method compatible with the multi-instruction system, which comprises the following steps:
step 1, decoding an instruction to be executed into a micro-operation code according to a pre-programmed instruction system through a programmable decoding component;
step 2, reading and writing data cache through an execution component, and executing the micro operation code to obtain an execution result;
and 3, after the execution result is written back and submitted by the writing back and submitting component, finishing the execution of the instruction.
The processor operation method compatible with the multi-instruction system, wherein the step 1 further comprises:
the micro-operation code generated by the decoding of the programmable decoding component is stored by the micro-operation code cache for the subsequent execution component to read and execute.
The processor operation method compatible with the multi-instruction system is as follows: an X86 instruction system or an ARM instruction system or a MIPS instruction system or other instruction systems.
The method for operating a processor compatible with a multi-instruction system comprises the following steps: the system comprises an instruction cache interface, an execution component, a decoding program cache, a decoding data cache, a micro-operation code cache interface and a subsequent pipeline synchronization interface;
the instruction cache interface is used for connecting and accessing an instruction cache of the processor;
the decoding program cache is used for storing the decoding program of the current instruction system;
the decoding data buffer is used for temporarily storing data generated or operated by a decoding program;
the micro-operation code cache interface is used for connecting and accessing the micro-operation code cache;
the subsequent pipeline synchronous interface is used for receiving a feedback signal of a subsequent pipeline component;
the execution unit is used for executing the decoding program in the decoding program cache, finishing the decoding of the fetched instruction and the register renaming operation through the instruction cache interface fetching, generating the micro-operation code, writing the micro-operation code into the cache through the micro-operation code cache interface, simultaneously reading the signal or the message of the subsequent pipeline synchronous interface, and updating the execution path of the decoding program according to the synchronous signal or the message, thereby changing the instruction flow execution path of the whole processor.
Claims (6)
1. A multi-instruction system compatible processor, comprising:
the programmable decoding component is used for decoding the instruction to be executed into a micro-operation code according to a preprogrammed instruction system;
the execution component is used for executing the micro operation code by reading and writing the data cache to obtain an execution result;
write back and submit the part, is used for writing back and submitting the result of this execution, finish the execution of this order;
the programmable decoding component includes: the system comprises an instruction cache interface, an execution component, a decoding program cache, a decoding data cache, a micro-operation code cache interface and a subsequent pipeline synchronization interface;
the instruction cache interface is used for connecting and accessing an instruction cache of the processor;
the decoding program cache is used for storing the decoding program of the current instruction system;
the decoding data buffer is used for temporarily storing data generated or operated by the decoding program;
the micro-operation code cache interface is used for connecting and accessing the micro-operation code cache;
the subsequent pipeline synchronous interface is used for receiving a feedback signal of a subsequent pipeline component;
the execution unit is used for executing the decoding program in the decoding program cache, finishing the decoding of the fetched instruction and the register renaming operation through the instruction cache interface fetching, generating the micro-operation code, writing the micro-operation code into the cache through the micro-operation code cache interface, simultaneously reading the signal or the message of the subsequent pipeline synchronous interface, and updating the execution path of the decoding program according to the synchronous signal or the message, thereby changing the instruction flow execution path of the whole processor.
2. The multiple instruction system compatible processor of claim 1, further comprising:
and the micro-operation code cache is used for storing the micro-operation codes generated by decoding of the programmable decoding component for subsequent reading and execution of the execution component.
3. The multiple instruction system compatible processor of claim 1, wherein the instruction system is: an X86 instruction system or an ARM instruction system or a MIPS instruction system or a RISCV instruction system.
4. A method for operating a processor compatible with multiple instruction systems, comprising:
step 1, decoding an instruction to be executed into a micro-operation code according to a pre-programmed instruction system through a programmable decoding component;
step 2, reading and writing data cache through an execution component, and executing the micro operation code to obtain an execution result;
step 3, after the execution result is written back and submitted by the write-back and submission component, the execution of the instruction is finished;
the programmable decoding unit includes: the device comprises an instruction cache interface, an execution component, a decoding program cache, a decoding data cache, a micro-operation code cache interface and a subsequent pipeline synchronization interface;
the instruction cache interface is used for connecting and accessing an instruction cache of the processor;
the decoding program cache is used for storing the decoding program of the current instruction system;
the decoding data buffer is used for temporarily storing data generated or operated by a decoding program;
the micro-operation code cache interface is used for connecting and accessing the micro-operation code cache;
the subsequent pipeline synchronous interface is used for receiving a feedback signal of a subsequent pipeline component;
the execution unit is used for executing the decoding program in the decoding program cache, finishing the decoding of the fetched instruction and the register renaming operation through the instruction cache interface fetching, generating the micro-operation code, writing the micro-operation code into the cache through the micro-operation code cache interface, simultaneously reading the signal or the message of the subsequent pipeline synchronous interface, and updating the execution path of the decoding program according to the synchronous signal or the message, thereby changing the instruction flow execution path of the whole processor.
5. The method of claim 4, wherein step 1 further comprises:
the micro-operation code generated by decoding of the programmable decoding component is stored through the micro-operation code cache for the subsequent execution component to read and execute.
6. The method as claimed in claim 4, wherein the instruction system is: an X86 instruction system or an ARM instruction system or a MIPS instruction system or a RISCV instruction system.
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| US9710277B2 (en) * | 2010-09-24 | 2017-07-18 | Intel Corporation | Processor power management based on class and content of instructions |
| CN103150146B (en) * | 2013-01-31 | 2015-11-25 | 西安电子科技大学 | Based on ASIP and its implementation of scalable processors framework |
| US10089114B2 (en) * | 2016-03-30 | 2018-10-02 | Qualcomm Incorporated | Multiple instruction issuance with parallel inter-group and intra-group picking |
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| CN1959694A (en) * | 2006-12-04 | 2007-05-09 | 中国科学院计算技术研究所 | Programmable security processor |
| CN106055405A (en) * | 2016-04-20 | 2016-10-26 | 矽魅信息科技（上海）有限公司 | Memory sharing processor based on programmable microcodes and reconstruction method for same |
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