CN111913822B - Inter-core communication mode based on AMP architecture - Google Patents
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Abstract
The invention discloses an inter-core communication mode based on an AMP architecture, which comprises the following steps: dividing a multi-core communication system into an application layer, a drive layer and a logic layer; configuring a circuit of a logic layer, and carrying out multi-core communication initialization configuration to obtain a configured multi-core communication system; starting a main core in the configured multi-core communication system, monitoring network information in an application layer through the main core, and constructing a main core management mechanism and a slave core management mechanism; and calling a driving layer interface to establish a communication request between the master core and the slave core according to a master-slave core management mechanism, and starting communication between the master core and the slave core. The invention provides an inter-core communication mode based on an AMP (amplifier) framework, which reduces the inconsistency of data interaction interfaces between different operating systems, has short response time and avoids the problem of data loss.
Description
Technical Field
The invention belongs to the technical field of communication control, and particularly relates to an inter-core communication mode based on an AMP architecture.
Background
In recent years, the integration of the number of CPU cores on one chip has reached thousands due to the rapid development of semiconductor technology. Embedded mobile devices are indispensable in work and life interaction, frequently activate among industries, and also occupy an important position in the market. However, the increase rate of the performance of the chip using only a single core starts to slow down, and although the performance can be improved by improving the main frequency of the single-core processor and increasing the parallelism of the instruction level, the increase of the main frequency of the CPU also means that the power consumption of the chip needs to be increased, and the peak value of the power consumption of the modern general-purpose processor is already up to hundreds of watts. Therefore, the multi-nuclear technology gradually enters the human vision
The embedded processor is developed from a single core to a multi-core, and the process of isomorphism development to isomerism meets the requirements of different fields. For the current multi-core environment, the technologies of inter-core communication, task scheduling, cache consistency, inter-core synchronization and mutual exclusion, inter-core interrupt processing mechanism and the like of the processor are very important. However, the multi-core parallel embedded architecture simply adopting the SMP architecture cannot give play to the respective characteristics of each CPU, and the operating system communication interaction interfaces used by each CPU are also different, which results in an excessively complex inter-core communication mechanism.
Disclosure of Invention
Aiming at the defects in the prior art, the inter-core communication mode based on the AMP architecture solves the problem that an inter-core communication mechanism in the prior art is complex.
In order to achieve the purpose of the invention, the invention adopts the technical scheme that: an inter-core communication mode based on AMP architecture comprises the following steps:
s1, dividing a multi-core communication system into an application layer, a driving layer and a logic layer;
s2, configuring a circuit of a logic layer, and performing multi-core communication initialization configuration to obtain a configured multi-core communication system;
s3, starting a main core in the configured multi-core communication system, monitoring network information in an application layer through the main core, and constructing a main core and auxiliary core management mechanism;
and S4, calling a driving layer interface to establish a communication request between the master core and the slave core according to a master-slave core management mechanism, and starting communication between the master core and the slave core.
Further, the application layer in step S1 is configured to provide a network data interaction interface, perform TCP reliable network communication, provide a data packing processing or instruction parsing interface according to a communication protocol, obtain a device driver descriptor, and perform inter-core data interaction and data sharing by using a driver layer interface;
the driving layer in the step S1 is configured to perform data read-write operation on a specific address or a register according to a hardware address provided by the logic layer, and provide a bottom layer operation interface for the application layer;
the logic layer in step S1 is used to design an interrupt signal generation circuit, configure a system clock, and share a memory address, so as to provide a physical link connection for multi-core communication management.
Further, the step S2 includes the following sub-steps:
s21, configuring a circuit of a logic layer, initializing a register, reading a BOOT mode of the multi-core communication system, and acquiring a BOOT.bin file on an SD card in the multi-core communication system;
s22, transmitting the BOOT. Bin file obtained in the step S21 to a DDR memory, judging whether a bit file exists in the DDR memory, if so, loading the bit file into the FPGA, and entering the step S23, otherwise, directly entering the step S23;
and S23, judging whether the elf file exists or not, if so, loading the elf file into a corresponding memory address space to obtain the configured multi-core communication system, otherwise, not operating to obtain the configured multi-core communication system.
Further, the master-slave management mechanism in step S3 includes a master core management mechanism and a slave core management mechanism.
Further, the master core management mechanism is specifically:
a1, starting a main core CPU0, and initializing a Linux system through the main core CPU0;
a2, enabling the Linux system to start working, creating a TCP network communication object through a main core CPU0, and adding the TCP network communication object into a thread pool to obtain a network communication thread;
a3, monitoring a network state through a network communication thread, judging whether a connection object exists, if so, receiving port data corresponding to the connection object, storing the port data into a cache, and entering the step A4, otherwise, repeating the step A3;
a4, judging whether the starting of the network communication thread is based on the acquisition of the network communication data according to the port data, if so, the thread is in a ready state, does not operate and is ended, otherwise, the thread is converted from the ready state to an operating state, performs control instruction and shared memory management and enters step A5;
and A5, judging whether a slave core awakening instruction exists in a signal sent by the network communication thread through a driving management thread in the Linux system, if so, awakening the process of the slave core CPU1 through an interrupt device of a logic layer, and ending a master core management mechanism, otherwise, directly ending the master core management mechanism.
Further, the slave core management mechanism is specifically: starting the slave core CPU1, judging whether the process is awakened or not through the slave core CPU1, if so, establishing a thread through the slave core CPU1, converting the ready state into an operation state, processing data, feeding back information to the master core CPU0, entering the ready state after the data is processed to wait for awakening, and otherwise, not operating;
and the data interaction of the main core CPU0 and the slave core CPU1 adopts a memory sharing mode.
Further, the specific step of calling the driver layer interface to establish the communication request between the master core and the slave core in step S4 is:
b1, starting application program operation, calling a driving layer interface in an application layer through a main core CPU0, and sending an interrupt signal;
b2, calling a copy _ from _ uesr () function through a driving layer according to the interrupt signal to obtain a memory address of the application program operation under the application layer;
b3, judging whether the memory address is in an address range set by the logic layer, if so, calling an IOwrite32 () function to write the address, carrying out interrupt response on the slave core CPU1, and entering the step B4, otherwise, not operating, and feeding back information of calling drive interface failure to the master core CPU0;
b4, establishing a thread through the slave core CPU1, converting the ready state into the running state, starting data processing, and feeding back information to the master core CPU0;
b5, judging whether feedback information errors, no feedback information or overtime waiting time exist or not through the CPU0 of the main core, if so, judging that the communication request is abnormal, returning to the step B1, and re-applying the inter-core communication, otherwise, judging that the communication request flow is correct and the communication request is successful.
Further, the communication between the master core and the slave core in step S4 includes a master core communication flow and a slave core communication flow, and the master core communication flow and the slave core communication flow share a memory.
Further, the main core communication process specifically includes:
c1, monitoring network data through an application layer, and performing command analysis on the monitored network data;
c2, acquiring a slave core CPU1 memory access mark corresponding to the command, judging whether the slave core CPU1 memory access mark is false or not, if so, modifying the slave core CPU1 memory access mark to be true, calling a data memory access driver to store the data into a shared memory, entering the step C3, and otherwise, repeating the step C2;
c3, sending an interrupt communication application to the slave core CPU1, and acquiring a memory access mark of the master core CPU0;
and C4, judging whether the memory access mark of the CPU0 of the main core is false, if so, judging that the process of the CPU1 of the slave core does not feed back correct information or the interrupt communication application is invalid, repeating the step C3 after the waiting time is overtime, otherwise, judging that the data interaction of the master core and the slave core is successful, setting the memory access mark of the CPU0 of the main core to be false, and finishing the communication flow of the main core.
Further, the slave core communication process specifically includes:
d1, starting a data processing process by receiving an interrupt signal uploaded by a logic layer from the core CPU1, and acquiring a memory access mark of the slave core CPU 1;
d2, judging whether the memory access mark of the slave core CPU1 is false, if so, repeating the step D2, otherwise, setting the memory access mark of the slave core CPU1 to be false, and entering the step D3;
d3, acquiring data from the shared memory through the slave CPU1 and performing data processing;
and D4, acquiring the memory access flag of the CPU0 of the main core and judging whether the memory access flag is true, if so, repeating the step D4 after the waiting time is overtime, otherwise, setting the memory access flag of the CPU0 of the main core to be false, and finishing the communication process of the slave core.
The invention has the beneficial effects that:
(1) The invention is suitable for the characteristics of different CPUs, adopts different operating systems for interaction, and simultaneously ensures that each operating system can use the independent API to communicate without adding other API interfaces by an interrupt mechanism.
(2) The shared memory of the invention realizes the convenience of resource management and allocation and simplifies the problem of cache consistency in multi-core communication.
(3) The invention provides an inter-core communication mode based on an AMP architecture, which reduces the inconsistency of data interaction interfaces between different operating systems, has short response time and avoids the problem of data loss.
Drawings
Fig. 1 is a flowchart of an inter-core communication method based on an AMP architecture according to the present invention.
Detailed Description
The following description of the embodiments of the present invention is provided to facilitate the understanding of the present invention by those skilled in the art, but it should be understood that the present invention is not limited to the scope of the embodiments, and it will be apparent to those skilled in the art that various changes may be made without departing from the spirit and scope of the invention as defined and defined in the appended claims, and all matters produced by the invention using the inventive concept are protected.
Embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
As shown in fig. 1, an inter-core communication method based on an AMP architecture includes the following steps:
s1, dividing a multi-core communication system into an application layer, a driving layer and a logic layer;
s2, configuring a circuit of a logic layer, and performing multi-core communication initialization configuration to obtain a configured multi-core communication system;
s3, starting a main core in the configured multi-core communication system, monitoring network information in an application layer through the main core, and constructing a main core and auxiliary core management mechanism;
and S4, calling a driving layer interface to establish a communication request between the master core and the slave core according to a master-slave core management mechanism, and starting communication between the master core and the slave core.
The application layer in the step S1 is used for providing a network data interaction interface, performing TCP reliable network communication, providing a data packing processing or instruction parsing interface according to a communication protocol, acquiring a device driver descriptor, and performing inter-core data interaction and data sharing by using a driver layer interface;
the driving layer in the step S1 is configured to perform data read-write operation on a specific address or a register according to a hardware address provided by the logic layer, and provide a bottom layer operation interface for the application layer;
the logic layer in step S1 is used to design an interrupt signal generation circuit, configure a system clock, and share a memory address, so as to provide a physical link connection for multi-core communication management.
The step S2 comprises the following sub-steps:
s21, configuring a circuit of a logic layer, initializing a register, reading a BOOT mode of the multi-core communication system, and acquiring a BOOT.bin file on an SD card in the multi-core communication system;
s22, transmitting the BOOT. Bin file obtained in the step S21 to a DDR memory, judging whether a bit file exists in the DDR memory, if so, loading the bit file into the FPGA, and entering the step S23, otherwise, directly entering the step S23;
and S23, judging whether the elf file exists or not, if so, loading the elf file into a corresponding memory address space to obtain the configured multi-core communication system, otherwise, not operating to obtain the configured multi-core communication system.
The master-slave management mechanism in step S3 includes a master management mechanism and a slave management mechanism.
The main core management mechanism specifically comprises:
a1, starting a main core CPU0, and initializing a Linux system through the main core CPU0;
a2, enabling the Linux system to start working, creating a TCP network communication object through a main core CPU0, and adding the TCP network communication object into a thread pool to obtain a network communication thread;
a3, monitoring a network state through a network communication thread, judging whether a connection object exists, if so, receiving port data corresponding to the connection object, storing the port data into a cache, and entering the step A4, otherwise, repeating the step A3;
a4, judging whether the starting of the network communication thread is based on the acquisition of the network communication data according to the port data, if so, the thread is in a ready state, does not operate and is ended, otherwise, the thread is converted from the ready state to an operating state, performs control instruction and shared memory management and enters step A5;
and A5, judging whether a slave core awakening instruction exists in a signal sent by the network communication thread through a driving management thread in the Linux system, if so, awakening the process of the slave core CPU1 through an interrupt device of a logic layer, and ending a master core management mechanism, otherwise, directly ending the master core management mechanism.
The slave core management mechanism is specifically as follows: starting the slave core CPU1, judging whether the process is awakened or not through the slave core CPU1, if so, establishing a thread through the slave core CPU1, converting the ready state into an operation state, processing data, feeding back information to the master core CPU0, entering the ready state after the data is processed to wait for awakening, and otherwise, not operating;
and the data interaction of the main core CPU0 and the slave core CPU1 adopts a memory sharing mode.
The specific steps of calling the driver layer interface to establish the communication request between the master core and the slave core in the step S4 are as follows:
b1, starting application program operation, calling a driving layer interface in an application layer through a main core CPU0, and sending an interrupt signal;
b2, calling a copy _ from _ uesr () function through a driving layer according to the interrupt signal to obtain a memory address of the application program operation under the application layer;
b3, judging whether the memory address is in an address range set by the logic layer, if so, calling an IOwrite32 () function to write the address, carrying out interrupt response on the slave core CPU1, and entering the step B4, otherwise, not operating, and feeding back information of calling drive interface failure to the master core CPU0;
b4, establishing a thread through the slave core CPU1, converting the ready state into the running state, starting data processing, and feeding back information to the master core CPU0;
b5, judging whether feedback information errors, no feedback information or overtime waiting time exist or not through the CPU0 of the main core, if so, judging that the communication request is abnormal, returning to the step B1, and re-applying the inter-core communication, otherwise, judging that the communication request flow is correct and the communication request is successful.
The communication between the master core and the slave core in the step S4 includes a master core communication flow and a slave core communication flow, and the master core communication flow and the slave core communication flow share a memory.
The main core communication process specifically comprises the following steps:
c1, monitoring network data through an application layer, and performing command analysis on the monitored network data;
c2, acquiring a slave core CPU1 memory access mark corresponding to the command, judging whether the slave core CPU1 memory access mark is false, if so, modifying the slave core CPU1 memory access mark to be true, calling a data memory access driver to store data into a shared memory, entering the step C3, otherwise, repeating the step C2;
c3, sending an interrupt communication application to the slave core CPU1, and acquiring a memory access mark of the master core CPU0;
and C4, judging whether the memory access mark of the CPU0 of the main core is false, if so, judging that the process of the CPU1 of the slave core does not feed back correct information or the interrupt communication application is invalid, repeating the step C3 after the waiting time is overtime, otherwise, judging that the data interaction of the master core and the slave core is successful, setting the memory access mark of the CPU0 of the main core to be false, and finishing the communication flow of the main core.
The slave core communication flow specifically comprises the following steps:
d1, starting a data processing process by receiving an interrupt signal uploaded by a logic layer from the core CPU1, and acquiring a memory access mark of the slave core CPU 1;
d2, judging whether the memory access mark of the slave core CPU1 is false, if so, repeating the step D2, otherwise, setting the memory access mark of the slave core CPU1 to be false, and entering the step D3;
d3, acquiring data from the shared memory through the slave CPU1 and performing data processing;
and D4, acquiring the memory access flag of the CPU0 of the main core and judging whether the memory access flag is true, if so, repeating the step D4 after the waiting time is overtime, otherwise, setting the memory access flag of the CPU0 of the main core to be false, and finishing the communication process of the slave core.
In this embodiment, under a ZYNQ-7000 series dual-core chip platform, 16MB/s auto-increment data received by the network interface is used as an input test, and the experimental result shows: compared with an SMP (symmetric multi-processing) architecture system, the method meets the performance requirement of a real-time system, and can improve the interrupt response time from the level of a few milliseconds to the level of tens of microseconds. In multiple measurements, no data loss or data packet drop phenomenon is found.
The invention has the beneficial effects that:
(1) The invention is suitable for the characteristics of different CPUs, adopts different operating systems for interaction, and simultaneously ensures that each operating system can use the independent API to communicate without adding other API interfaces by an interrupt mechanism.
(2) The invention realizes the convenience of resource management and allocation by sharing the memory, and simplifies the problem of cache consistency during multi-core communication.
(3) The invention provides an inter-core communication mode based on an AMP architecture, which reduces the inconsistency of data interaction interfaces between different operating systems, has short response time and avoids the problem of data loss.
Claims (4)
1. The inter-core communication mode based on the AMP architecture is characterized by comprising the following steps:
s1, dividing a multi-core communication system into an application layer, a driving layer and a logic layer;
s2, configuring a circuit of a logic layer, and performing multi-core communication initialization configuration to obtain a configured multi-core communication system;
s3, starting a main core in the configured multi-core communication system, monitoring network information in an application layer through the main core, and constructing a main core and auxiliary core management mechanism;
s4, calling a driving layer interface to establish a communication request between the master core and the slave core according to a master-slave core management mechanism, and starting communication between the master core and the slave core;
the master-slave core management mechanism in the step S3 comprises a master core management mechanism and a slave core management mechanism;
the main core management mechanism specifically comprises:
a1, starting a main core CPU0, and initializing a Linux system through the main core CPU0;
a2, enabling the Linux system to start working, creating a TCP network communication object through a main core CPU0, and adding the TCP network communication object into a thread pool to obtain a network communication thread;
a3, monitoring a network state through a network communication thread, judging whether a connection object exists, if so, receiving port data corresponding to the connection object, storing the port data into a cache, and entering the step A4, otherwise, repeating the step A3;
a4, judging whether the starting of the network communication thread is based on the acquisition of the network communication data according to the port data, if so, the thread is in a ready state, does not operate and is ended, otherwise, the thread is converted from the ready state to an operating state, performs control instruction and shared memory management and enters step A5;
a5, judging whether a slave core awakening instruction exists in a signal issued by a network communication thread through a driving management thread in the Linux system, if so, awakening the process of a slave core CPU1 through an interrupt device of a logic layer, and ending a master core management mechanism, otherwise, directly ending the master core management mechanism;
the slave core management mechanism is specifically as follows: starting the slave core CPU1, judging whether the process is awakened or not through the slave core CPU1, if so, establishing a thread through the slave core CPU1, converting the ready state into an operation state, processing data, feeding back information to the master core CPU0, entering the ready state after the data is processed to wait for awakening, and otherwise, not operating;
the data interaction of the main core CPU0 and the slave core CPU1 adopts a memory sharing mode;
the communication between the master core and the slave core in the step S4 includes a master core communication flow and a slave core communication flow, and the master core communication flow and the slave core communication flow share a memory;
the main core communication process specifically comprises the following steps:
c1, monitoring network data through an application layer, and performing command analysis on the monitored network data;
c2, acquiring a slave core CPU1 memory access mark corresponding to the command, judging whether the slave core CPU1 memory access mark is false, if so, modifying the slave core CPU1 memory access mark to be true, calling a data memory access driver to store data into a shared memory, entering the step C3, otherwise, repeating the step C2;
c3, sending an interrupt communication application to the slave core CPU1, and acquiring a memory access mark of the master core CPU0;
c4, judging whether the memory access mark of the CPU0 of the main core is false, if so, judging that the process of the CPU1 of the slave core does not feed back correct information or the interrupt communication application is invalid, repeating the step C3 after the waiting time is overtime, otherwise, judging that the data interaction of the master core and the slave core is successful, setting the memory access mark of the CPU0 of the main core to be false, and finishing the communication flow of the main core;
the slave core communication flow specifically comprises the following steps:
d1, starting a data processing process by receiving an interrupt signal uploaded by a logic layer from the core CPU1, and acquiring a memory access mark of the slave core CPU 1;
d2, judging whether the memory access mark of the slave core CPU1 is false, if so, repeating the step D2, otherwise, setting the memory access mark of the slave core CPU1 to be false, and entering the step D3;
d3, acquiring data from the shared memory through the slave CPU1 and performing data processing;
and D4, acquiring the memory access flag of the CPU0 of the main core and judging whether the memory access flag is true, if so, repeating the step D4 after the waiting time is overtime, otherwise, setting the memory access flag of the CPU0 of the main core to be false, and finishing the communication process of the slave core.
2. The inter-core communication mode based on the AMP architecture of claim 1, wherein the application layer in the step S1 is configured to provide a network data interaction interface, perform TCP reliable network communication, provide a data packing processing or instruction parsing interface according to a communication protocol, obtain a device driver descriptor, and perform inter-core data interaction and data sharing by using a driver layer interface;
the driving layer in the step S1 is configured to perform data read-write operation on a specific address or a register according to a hardware address provided by the logic layer, and provide a bottom layer operation interface for the application layer;
the logic layer in step S1 is used to design an interrupt signal generation circuit, configure a system clock, and share a memory address, so as to provide a physical link connection for multi-core communication management.
3. The AMP architecture-based inter-core communication of claim 1, wherein the step S2 comprises the sub-steps of:
s21, configuring a circuit of a logic layer, initializing a register, reading a BOOT mode of the multi-core communication system, and acquiring a BOOT.bin file on an SD card in the multi-core communication system;
s22, transmitting the BOOT. Bin file obtained in the step S21 to a DDR memory, judging whether a bit file exists in the DDR memory, if so, loading the bit file into the FPGA, and entering the step S23, otherwise, directly entering the step S23;
and S23, judging whether the elf file exists or not, if so, loading the elf file into a corresponding memory address space to obtain the configured multi-core communication system, otherwise, not operating to obtain the configured multi-core communication system.
4. The AMP architecture-based inter-core communication manner of claim 1, wherein the specific steps of invoking the driver layer interface in step S4 to establish the communication request between the master core and the slave core are:
b1, starting application program operation, calling a driving layer interface in an application layer through a main core CPU0, and sending an interrupt signal;
b2, calling a copy _ from _ uesr () function through a drive layer according to the interrupt signal to obtain a memory address of application program operation under the application layer;
b3, judging whether the memory address is in an address range set by the logic layer, if so, calling an IOwrite32 () function to write the address, carrying out interrupt response on the slave core CPU1, and entering the step B4, otherwise, not carrying out operation, and feeding back information of calling a drive interface failure to the master core CPU0;
b4, establishing a thread through the slave core CPU1, converting the ready state into the running state, starting data processing, and feeding back information to the master core CPU0;
b5, judging whether feedback information errors, no feedback information or overtime waiting time exist or not through the CPU0 of the main core, if so, judging that the communication request is abnormal, returning to the step B1, and re-applying the inter-core communication, otherwise, judging that the communication request flow is correct and the communication request is successful.
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