CN213634473U

CN213634473U - Device and system for realizing remote deployment and debugging of FPGA (field programmable Gate array) based on SIP (Session initiation protocol)

Info

Publication number: CN213634473U
Application number: CN202022165484.9U
Authority: CN
Inventors: 秦波; 韩国荣; 张建东; 韦林; 陈铭
Original assignee: Beijing Huake Haixun Technology Co ltd
Current assignee: Beijing Huake Haixun Technology Co ltd
Priority date: 2020-09-28
Filing date: 2020-09-28
Publication date: 2021-07-06
Anticipated expiration: 2030-09-28

Abstract

The utility model discloses a device based on SIP realizes long-range deployment and debugging FPGA adopts SIP technique to realize collecting the debugging and deploying FPGA function in the single encapsulation module of an organic whole, supports network remote operation, and inside integrated large capacity nonvolatile memory with richen peripheral hardware interface supports the user and deploys FPGA array and system health management function in batches. The device for realizing remote deployment and debugging of the FPGA based on the SIP adopts a system-in-package SIP process, and comprises the following components: 100Base-T interface, SGMII interface, SelectMAP interface and XVC interface; the PC or the switch is connected with the 100Base-T interface; the SGMII equipment is connected with the SGMII equipment through an SGMII interface; the SelectMAP interface of the FPGA is connected with the SelectMAP interface, the JTAG interface of the FPGA is connected with the XVC interface, and the FPGA is configured in a SelectMAP mode.

Description

Device and system for realizing remote deployment and debugging of FPGA (field programmable Gate array) based on SIP (Session initiation protocol)

Technical Field

The utility model relates to a encapsulation field especially relates to a realize long-range deployment and debugging FPGA's device and system based on SIP.

Background

The FPGA sets the working state of the FPGA by a program stored in an on-chip RAM, so the on-chip RAM needs to be programmed during working. The user can adopt different programming modes according to different configuration modes. When the power is on, the FPGA chip reads the data in the FLASH into the on-chip programming RAM, and after the configuration is finished, the FPGA enters a working state.

In the conventional application of the existing FPGA, a FLASH is mounted on an FPGA board and used for storing an FPGA program file, interfaces between the FLASH and the FPGA are 3 types, such as SPI, selectMAP, BPI and the like, according to the configuration mode of the FPGA, and a JTAG debugging interface is simultaneously led out from a board card. The FPGA debugger is connected with the debugging board card through a JTAG port, and is connected with a computer through a USB interface. And the on-line debugging of the FPGA and the FLASH solidification are carried out by an FPGA debugger.

The prior art scheme adopts a mode of a USB interface FPGA debugger, and mainly has the following defects: (1) since the USB communication distance generally does not exceed 5m, the debugging computer cannot be too far away from the device. When the equipment is in severe environments such as a machine room, the field and the like, the equipment is extremely inconvenient to debug; (2) when the equipment needs to be debugged by a plurality of persons, the equipment or a computer needs to be moved, so that the efficiency is low; (3) the speed of curing FLASH through a USB is low, about 6 minutes is needed when a FLASH file with the size of 16MB is cured, and the curing time is multiplied when a system has a plurality of FLASH; (4) FLASH can not be deployed and managed in batch; (5) in part of designs, a USB debugger is designed and integrated in the equipment, the equipment directly goes out of a USB interface for debugging and management, the debugging and the deployment are discrete components, the design occupies a large board card area, and the use is limited in a board card with high device density.

The to-be-solved technical problem of the utility model has the following points: (1) by adopting a network technology, the remote loading and debugging of the FPGA are realized, the transmission distance is long, and the transmission can reach more than 200m under the condition of not adding any network repeater. (2) Due to the fact that the network is adopted, time-sharing multiplexing of the same set of equipment can be achieved by multiple people through the access switch, mobile equipment is not needed, and development and debugging efficiency is greatly improved. (3) The parallel FLASH and EXMC buses are adopted, the curing speed of the FLASH is improved, and compared with a USB debugger, the speed can be improved by more than 10 times. Meanwhile, the FPGA adopts a SelectMAP bus to carry out rapid loading. (4) All the FPGAs of the system are accessed into the network, and the batch solidification of FLASH, software version management and the like can be realized through PC software. (5) By adopting the SIP technology, the integrated network, the MCU and the FLASH are designed IN a SIP (System IN packet) with the size of 20 × 6mm, the integration level is high, and the occupied board card volume is small. And simultaneously, the functions of original debugging, deployment, FLASH and the like can be realized, and the performance is superior to that of a discrete element scheme.

SUMMERY OF THE UTILITY MODEL

The utility model aims to solve the technical problem that a device based on SIP realizes long-range deployment and debugging FPGA is provided, adopts the SIP technique, realizes collecting the debugging and deploys FPGA function in the single encapsulation module of an organic whole, supports network remote operation, and internal integration large capacity nonvolatile memory with richen peripheral hardware interface supports the user and deploys FPGA array and system health management function in batches.

In order to solve the technical problem, the utility model provides a device based on SIP realizes long-range deployment and debugging FPGA adopts system level packaging SIP technology, the device includes:

100Base-T interface, SGMII interface, SelectMAP interface and XVC interface;

the PC or the switch is connected with the 100Base-T interface;

the SGMII equipment is connected with the SGMII equipment through an SGMII interface;

the interface of the SelectMAP of the FPGA is connected through the SelectMAP interface, the interface of the JTAG of the FPGA is connected through the XVC interface, and the FPGA is configured to be in a SelectMAP mode.

Alternatively to this, the first and second parts may,

the device further comprises: and the MCU is used for setting the select MAP interface and the XVC interface.

Alternatively to this, the first and second parts may,

the device further comprises: and the PHY is used for realizing a network interface and is communicated with the MCU through an MII interface, and the PHY is provided with the 100Base-T interface and the SGMII interface.

Alternatively to this, the first and second parts may,

the device further comprises: and the clock is used for providing 25M working clock for the MCU and the PHY.

Alternatively to this, the first and second parts may,

the device further comprises: a DCDC capable of converting 3.3V to 1.0V or 2.5V and powering the PHY.

Alternatively to this, the first and second parts may,

the device further comprises: and the FLASH is used for storing the FPGA program file, and is communicated with the MCU.

Alternatively to this, the first and second parts may,

the packaging process adopts a 3D embedded type process, 3 layers of device surfaces are divided, and 96 devices are packaged in a single package with 20 × 6 mm.

Alternatively to this, the first and second parts may,

the SIP pins are packaged in an LGA planar grid array package, and comprise 105 pins.

Alternatively to this, the first and second parts may,

the SIP four-corner side wall metallization is used for SIP welding reinforcement;

the LGA leads pins out in a contact manner.

The utility model also provides a system for realize long-range deployment and debugging FPGA based on SIP, include:

m devices for realizing remote deployment and debugging of the FPGA based on the SIP, N upper computers and L FPGAs;

m, N and L are positive integers;

the device is in communication with the FPGA;

the upper computer is connected with the device through the Ethernet.

Compared with the prior art, the utility model discloses following beneficial effect has:

the SIP external interface comprises the following parts: the power supply interface inputs a 3.3V power supply, the working current is less than 500mA, and the 100Base-T interface and the SGMII interface are connected with the power supply interface; the SelectMAP interface is used for configuring the FPGA, supports a data bit X8/X16 mode, and can configure more than 4 FPGAs in a time division multiplexing mode; and the XVC interface can be used for configuration and online debugging of the FPGA. By adopting the SIP technology, the single-package module integrating the functions of debugging and deploying the FPGA is realized, the remote operation of a network is supported, a large-capacity nonvolatile memory and rich peripheral interfaces are integrated inside, and the batch deployment of the FPGA array and the system health management function of a user are supported.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.

Fig. 1 is a functional block diagram of an embodiment of a device for implementing remote deployment and debugging of an FPGA based on an SIP according to the present invention;

fig. 2 is the utility model discloses in a device embodiment's multi-disc FPGA selectMAP configuration diagram based on SIP realizes long-range deployment and debugging FPGA.

Detailed Description

In order to make the technical solution of the present invention better understood, the technical solution of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative efforts belong to the protection scope of the present invention.

The terms "first," "second," and the like in the description and in the claims, and in the drawings described above, are used for distinguishing between different objects and not necessarily for describing a particular sequential or chronological order. Furthermore, the terms "include" and "have," as well as any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, apparatus, product, or apparatus that comprises a list of steps or elements is not limited to those listed but may alternatively include other steps or elements not listed or inherent to such process, method, product, or apparatus.

Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the invention. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is explicitly and implicitly understood by one skilled in the art that the embodiments described herein can be combined with other embodiments.

The utility model aims to solve the technical problem that an embodiment of a device based on SIP realizes long-range deployment and debugging FPGA is provided, adopts system level packaging SIP technology, and the device includes: 100Base-T interface, SGMII interface, SelectMAP interface and XVC interface; the PC or the switch is connected with the 100Base-T interface; the SGMII equipment is connected with the SGMII equipment through an SGMII interface; the SelectMAP interface of the FPGA is connected with the SelectMAP interface, the JTAG interface of the FPGA is connected with the XVC interface, and the FPGA is configured in a SelectMAP mode.

In the embodiment, 100Base-T and SGMII interfaces (only one interface can be used at the same time and can be configured through GPIO or software) are directly connected to a PC or a switching device, and the system is managed through PC software. The SelectMAP and the XVC interfaces are used for connecting the FPGA, the SelectMAP interfaces are connected to the SelectMAP interfaces of the FPGA, the FPGA is configured in a Salve SelectMAP mode, and the XVC interfaces are connected to the JTAG interfaces of the FPGA. By adopting the SIP technology, the single-package module integrating the functions of debugging and deploying the FPGA is realized, the remote operation of a network is supported, a large-capacity nonvolatile memory and rich peripheral interfaces are integrated inside, and the batch deployment of the FPGA array and the system health management function of a user are supported. FPGA, a semiconductor device having Programmable elements, and a Field Programmable Gate Array (FPGA) element for Field programming by a user. The FPGA is a product which is further developed on the basis of programmable devices such as PAL, GAL, CPLD and the like. By adopting the SIP packaging technology, the occupied space of the board card is greatly reduced, and the body-side vibration resistance is improved.

It should be noted that the device further includes: the MCU is provided with a select MAP interface and an XVC interface. And the PHY is used for realizing the network port and is communicated with the MCU through an MII interface, and the PHY is provided with a 100Base-T interface and an SGMII interface. And the clock is used for providing 25M working clock for the MCU and the PHY.

In this embodiment, as shown in fig. 1, the MCU is used as a control core of the SIP, and a domestic mega innovative GD32 series single chip microcomputer, 32-bit, ARM Cortex-M4 RISC core, and a master frequency of 200MHz, are used. The MCU mainly realizes the following functions: peripheral interfaces of the MCU, such as AD, SPI, I2C, CAN, IO, UART and the like are led out; performing read-write control on FLASH; control of the PHY, communication with the PC; realizing an XVC interface; implementation of a SelectMAP interface; and (4) realizing data transmission processes of loading, curing, debugging and the like of the BIT file. The PHY and the MCU communicate through an MII interface.

It should be noted that the device further includes: DCDC, which can convert 3.3V to 1.0V or 2.5V and power the PHY.

In this embodiment, the DCDC can convert 3.3V to 1.0V or 2.5V and supply power to the PHY, so that the conversion is stable and smooth.

It should be noted that the device further includes: and the FLASH is used for storing the FPGA program file and is communicated with the MCU.

In this embodiment, the SelectMAP interface may be used to configure the FPGA, support the data bit X8/X16 mode, and perform configuration of more than 4 FPGAs in a time division multiplexing manner. On the basis of having the FLASH function of the original scheme, the FLASH storage capacity is greatly improved, and the function of the original debugger is increased; the system has the FPGA batch deployment function, so that the system FPGA curing time is reduced; the remote debugging and curing function of the network can greatly reduce the danger and damage of the harsh environment to the life health of the operators

Further illustrating a typical application scenario of the present embodiment includes the following: rapidly deploying and curing the program; remote debugging and maintenance; and dynamically reconfiguring hardware. The specific indexes are as follows: JTAG debug XVC interface: 1 path; 8 analog inputs (12 bits) including an SPI 2 path, an I2C 2 path, a serial port 2 path and a CAN 2 path; a hundred mega ethernet interface: 1 way 100BASE-T,1 way SGMII; downloading speed: the maximum is 4000KB/s, which far exceeds the similar products; curing speed: the maximum is 900KB/s, which far exceeds the similar products; friendly software application interfaces; the external dimension is as follows: 20mm × 20mm × 6 mm; power consumption: not more than 1.3W; power supply: direct current + 3.3V.

It should be noted that, the packaging process adopts a 3D embedded process, and the 96 devices are packaged in a single package of 20 × 6mm by dividing the device surface into 3 layers.

In this embodiment, the SIP (system in a package) technology integrates circuits with different functions into one package, so as to implement a certain substantially complete function. SIP has attracted considerable attention as an effective method for improving the functions of a single-chip processor, and has been rapidly developed in recent years. And the adoption of the single-in-one package has high integration level and small occupied board card volume.

It should be noted that the SIP pins are packaged by LGA planar grid array, and include 105 pins.

In this embodiment, the LGA packaged chip can be connected to a Printed Circuit Board (PCB) or soldered directly to the PCB, which can reduce the problem of pin damage and increase pin count compared to the conventional pin-on-ic package.

The side walls of four corners of the SIP are metallized, and the side walls are used for SIP welding reinforcement; the LGA leads pins out in a contact manner.

In this embodiment, SIP four corners lateral wall metallization for SIP welding is consolidated, and the pin is drawn forth with the contact mode to the LGA, very big improvement the convenience of test.

The utility model also provides a system for realize long-range deployment and debugging FPGA based on SIP, include: m devices for realizing remote deployment and debugging of the FPGA based on the SIP, N upper computers and L FPGAs; m, N and L are positive integers; the device communicates with the FPGA; the upper computer is connected with the device through the Ethernet.

In this embodiment, the client communicates with the service program through the ethernet to implement the curing, loading, and debugging of the FPGA logic. FPGA solidification logic: through client software, a user can cure files on the nor false, cure a plurality of files and acquire related file information. Setting an FPGA starting file: through managing client software, a user can quickly set a solidified file to be an FPGA power-on loading file, and the user can modify the loading file at will. Debugging the FPGA on line: the user can perform network connection with 1804 and debug the FPGA through other FPGA debugging software (Vivado and the like). Batch operation of multiple FPGAs: by operating the client in batch, a user can control the multiple TBS1804 and the multiple FPGA to perform network loading, file curing and the like. As shown in fig. 2, when multiple FPGAs are connected, the SelectMAP interface data line is shared, the 8-bit and 16-bit width modes are supported, the control signals CS are separated, and the XVC interface forms a JTAG link, thereby implementing configuration debugging of the multiple FPGAs.

The above-described embodiments of the apparatus are merely illustrative, and the modules described as separate components may or may not be physically separate, and the components shown as modules may or may not be physical modules, may be located in one place, or may be distributed on a plurality of network modules. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of the present embodiment. One of ordinary skill in the art can understand and implement it without inventive effort.

Finally, it should be noted that: the device and the apparatus for implementing remote deployment and debugging of FPGA based on SIP disclosed in the embodiments of the present invention are only disclosed in the preferred embodiments of the present invention, and are only used for illustrating the technical solution of the present invention, not for limiting the same; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those skilled in the art; the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not depart from the spirit and scope of the present invention in its corresponding aspects.

Claims

1. A device for realizing remote deployment and debugging of FPGA based on SIP is characterized in that a system-in-package SIP process is adopted, and the device comprises:

100Base-T interface, SGMII interface, SelectMAP interface and XVC interface;

the PC or the switch is connected with the 100Base-T interface;

the SGMII interface is connected with the SGMII equipment;

the SelectMAP interface of the FPGA is connected with the SelectMAP interface, the JTAG interface of the FPGA is connected with the XVC interface, and the FPGA is configured in a SelectMAP mode.

2. The device for remotely deploying and debugging an FPGA based on SIP of claim 1,

3. The device for remotely deploying and debugging an FPGA based on SIP of claim 2,

4. The device for remotely deploying and debugging an FPGA based on SIP of claim 3,

5. The device for remotely deploying and debugging an FPGA based on SIP of claim 3,

6. The device for remotely deploying and debugging an FPGA based on SIP of claim 2,

7. The device for remotely deploying and debugging an FPGA based on SIP according to any one of claims 1-6,

the system-in-package SIP process adopts a 3D embedded process, 3 layers of device surfaces are divided, and 96 devices are packaged in a single package with 20 × 6 mm.

8. The device for remotely deploying and debugging an FPGA based on SIP according to any one of claims 1-6,

9. The device for remotely deploying and debugging an FPGA based on SIP according to claim 8,

the LGA leads pins out in a contact manner.

10. A system for realizing remote deployment and debugging of FPGA based on SIP is characterized by comprising:

m devices for realizing remote deployment and debugging of an FPGA based on SIP according to any one of claims 1 to 9, N upper computers and L FPGAs;

m, N and L are positive integers;

the device is in communication with the FPGA;

the upper computer is connected with the device through the Ethernet.