CN206684533U - Wechat remote control chip - Google Patents

Abstract

The utility model discloses a kind of wechat remote control chip, provided with a hardware debugging interface, one DLL, reset circuit, external wake circuit, multiple I/O interfaces, multichannel compares timer circuit, multiple SPI interface circuitries, multiple serial interface circuits, one D/A converting circuit, usb circuit, multiple IIC interface circuits, multiple four-way timers, one real time clock circuit, two external clock input circuits, one reserce cell and input power, the also built-in CPU of wechat remote control chip, high-speed memory, multiple I/O ports, two ADC converters, two high-speed high-grade peripheral bus and an Advanced High-Performance Bus, DLL is connected with CPU, I/O ports high-speed memory is connected with CPU.The utility model is using process is relatively simple, operation is more convenient, can realize and is remotely controlled whenever and wherever possible, realizes borderless and unlimited distance remote control.

Description

Wechat remote control chip

Technical field

Wechat control field is the utility model is related to, more particularly to a kind of wechat remote control chip.

Background technology

Traditional telecontrol engineering, substantially using dedicated radio link, bluetooth connection, ultrasonic wave connection or infrared connection side Formula.These remote control modes can not break through limited remote control distance, not be the remote control whenever and wherever possible of real meaning.And conventional remote controls Complex using process, operation is also inconvenient.For user, it is necessary to the remote control equipment not influenceed by distance；Set for product Meter developer is, it is necessary to be available for the underlying hardware and software assembly that exploitation uses.With the popularization of smart mobile phone, wechat therein is soft The user of part has reached more than 700,000,000, has played the huge user's usage amount of wechat, high frequency time uses, without installing control software Advantage, increasing user use wechat.However, there is presently no wechat is applied in the remote control of chip.

Utility model content

The technical problems to be solved in the utility model is, for the drawbacks described above of prior art, there is provided one kind used Journey is relatively simple, operation is more convenient, can realize and is remotely controlled whenever and wherever possible, realizes that the wechat of borderless and unlimited distance remote control is remote Process control chip.

Technical scheme is used by the utility model solves its technical problem：A kind of wechat remote control chip is constructed, Compare meter provided with a hardware debugging interface, a DLL, reset circuit, external wake circuit, multiple I/O interfaces, multichannel When device circuit, multiple SPI interface circuitries, multiple serial interface circuits, a D/A converting circuit, usb circuit, multiple IIC interface circuits, multiple four-way timers, a real time clock circuit, two external clock input circuits, a backup electricity Pond and input power, the also built-in CPU of the wechat remote control chip, high-speed memory, multiple I/O ports, two ADC conversions Device, two high-speed high-grade peripheral bus and an Advanced High-Performance Bus, the DLL are connected with the CPU, the height Fast memory is connected with the CPU, and each I/O interface passes through corresponding I/O ports and a wherein high-speed high-grade Peripheral bus connects, and the D/A converting circuit passes through ADC converters one of them described and a wherein high-speed high-grade Peripheral bus connects, wherein a high-speed high-grade peripheral bus passes through high-speed high-grade peripheral bus region and the advanced height Performance bus connects, and the high-speed high-grade peripheral bus region is also by described in low speed advanced peripheral bus region and other one High-speed high-grade peripheral bus connects.

In wechat remote control chip described in the utility model, the quantity of the I/O interface is five, the comparison The quantity of timer circuit is four tunnels, and the quantity of the SPI interface circuitry is two, and the quantity of the serial interface circuit is three Individual, the quantity of the IIC interface circuits is two, and the quantity of the four-way timer is three.

In wechat remote control chip described in the utility model, also built-in trace port interface unit, joint test Working Group Criteria test protocol interface, tracking/trigger, nested vector interrupt unit, tracking control unit and direct memory access Unit, the trace port interface unit and tracking control unit are connected with the tracking/trigger, the joint test work Group standard test protocols interface, tracking/trigger and nested vector interrupt unit are connected with the CPU, the direct internal memory Access unit is connected by bus matrix with the nested vector interrupt unit.

In wechat remote control chip described in the utility model, built-in power administrative unit, the reset circuit are gone back It is connected with the PMU, electrification reset built in the PMU/power-off restoration module and programmable voltage Detector.

In wechat remote control chip described in the utility model, an also built-in external interrupt wakeup port, four Timer, two SPI ports, three USART ports, two I2C ports and a USB device controller, the external wake Circuit is connected by the external interrupt wakeup port with the wherein one high-speed high-grade peripheral bus, the relatively timer Circuit is connected by timer one of them described with the wherein one high-speed high-grade peripheral bus, its excess-three timing Device connects with the corresponding four-way timer respectively, and each SPI interface circuitry is by corresponding SPI port and accordingly High-speed high-grade peripheral bus connection, each serial interface circuit passes through corresponding USART ports and corresponding institute State high-speed high-grade peripheral bus connection, the IIC interface circuits by the corresponding I2C ports with outside corresponding high-speed high-grade If bus connects, the usb circuit passes through the USB device controller and the other one high-speed high-grade peripheral bus Connection.

In wechat remote control chip described in the utility model, also built-in power supply, two external crystal-controlled oscillations, independences House dog, spare interface, real time clock unit, back-up registers, backup interface and extension local area network bus, the power supply The voltage of the input power is accessed, each external clock input circuit connects with the corresponding external crystal-controlled oscillation, institute State independent house dog to be connected with the reserce cell by the spare interface, the real time clock circuit is deposited with the backup Device connects, and the back-up registers and real time clock unit be also connected with the backup interface, the backup interface also with addition One high-speed high-grade peripheral bus connection.

In wechat remote control chip described in the utility model, also built-in frequency multiplication controller, internal RC oscillators and Outside RC oscillators, the internal RC oscillators are connected with the frequency multiplication controller, the frequency multiplication controller also with one of them The external crystal-controlled oscillation connection, the outside RC oscillators are connected with the independent house dog.

In wechat remote control chip described in the utility model, also built-in window house dog, the window house dog It is connected with the other one high-speed high-grade peripheral bus.

In wechat remote control chip described in the utility model, the CPU built in hardware CRC generators/checker.

In wechat remote control chip described in the utility model, the high-speed memory includes the flash memory of 128K bytes With the SRAM of 20K bytes, the flash memory of the 128K bytes is connected by flash interface with the CPU, the SRAM of the 20K bytes It is connected by the bus matrix with the CPU.

Implement wechat remote control chip of the present utility model, have the advantages that：Due to being adjusted provided with a hardware Mouth, a DLL, reset circuit, external wake circuit, multiple I/O interfaces, the multichannel of trying compare timer circuit, multiple It is SPI interface circuitry, multiple serial interface circuits, a D/A converting circuit, usb circuit, multiple IIC interface circuits, more Individual four-way timer, a real time clock circuit, two external clock input circuits, a reserce cell and input power, The also built-in CPU of wechat remote control chip, high-speed memory, multiple I/O ports, two ADC converters, two advanced peripherals are total Line and an Advanced High-Performance Bus, by integrating CPU, communication bus, peripheral bus and the common hardware of voltage distribution portion, Integrated to be fabricated to a chipset, user can be remotely controlled or transmit data by wechat, so it is more simple using process It is single, operation is more convenient, can realize and is remotely controlled whenever and wherever possible, realizes that borderless and unlimited distance is remotely controlled.

Brief description of the drawings

, below will be to embodiment in order to illustrate more clearly of the utility model embodiment or technical scheme of the prior art Or the required accompanying drawing used is briefly described in description of the prior art, it should be apparent that, drawings in the following description are only It is some embodiments of the utility model, for those of ordinary skill in the art, is not paying the premise of creative work Under, other accompanying drawings can also be obtained according to these accompanying drawings.

Fig. 1 is the structural representation in the utility model wechat remote control chip one embodiment.

Embodiment

Below in conjunction with the accompanying drawing in the utility model embodiment, the technical scheme in the embodiment of the utility model is carried out Clearly and completely describing, it is clear that described embodiment is only the utility model part of the embodiment, rather than whole Embodiment.Based on the embodiment in the utility model, those of ordinary skill in the art are not under the premise of creative work is made The every other embodiment obtained, belong to the scope of the utility model protection.

In the utility model wechat remote control chip embodiment, the structural representation of the wechat remote control chip is such as Shown in Fig. 1.In Fig. 1, the wechat remote control chip is provided with an a hardware debugging interface, DLL, reset circuit, outer Portion's wake-up circuit, multiple I/O interfaces, multichannel compare timer circuit, multiple SPI interface circuitries, multiple serial interface circuits, one Individual D/A converting circuit, usb circuit, multiple IIC interface circuits, multiple four-way timers, a real time clock circuit, Two external clock input circuits, a reserce cell and input power, the voltage of input power input is 2 to 3.6V, and this is micro- Believe the also built-in CPU of remote control chip, high-speed memory, multiple I/O ports GPIO, two ADC converters, two high-speed high-grades A peripheral bus APB2 and Advanced High-Performance Bus AHB.

In the present embodiment, hardware debugging interface is used to connect programmable device, is communicated with PC ends, makes PC ends developing instrument can With the debugging routine when hardware is run；DLL is used to connect programmable device, is communicated with PC ends, carries out the work of programming program Make；Reset circuit is used for cpu peripheral reset circuit, and control CPU is restarted；External wake circuit is used in CPU dormancy, by outside Circuit wakes up CPU；I/O interface is universal input/output interface, and it is the external electricity of comparator/timer that multichannel, which compares timer circuit, Road, for external external pulse circuit, counted by CPU；SPI interface is Serial Peripheral Interface (SPI), for connecting the peripheral hardware of spi bus Hardware；Serial interface circuit is used to carry out standard TTL serial communications；D/A converting circuit is digital-to-analog amount change-over circuit, is used In quantization analog quantity；Usb circuit is USB circuit, for connecting USB peripheral hardware；IIC interface circuits are IC bus, for connecting IIC peripheral hardware hardware；Four-way timer is timer circuit, for providing the time to software Benchmark；When clock circuit for real-time timing use；When clock circuit be external clock pulse input circuit, for two and brilliant Shake and circuit；Reserce cell is data backup battery, and data are kept for powering off.

In the present embodiment, CPU is central processing unit, is the core of computing, and using 32 RISC cores, working frequency is 72MHz, its model Cortex-M3, CPU working voltage are 2V-3.6V.The flash memory of high-speed memory including 128K bytes and The flash memory of the SRAM of 20K bytes, 128K byte is the Flash 128KB 64bit in Fig. 1, that is, 64 128KB flash memories Memory, the flash memory of 128K bytes are connected by flash interface flash Interface with CPU, and the SRAM of 20K bytes passes through total Wire matrix Bus Matrix are connected with CPU.The SRAM of 20K bytes is 20KB static RAMs.

Two ADC converters are exactly 12bit ADC1 and the 12bit ADC2 in Fig. 1.Each ADC converters share up to 16 external channels, it is possible to achieve single or scan transformation.In scanning-mode it, it is automatic to carry out in one group of selected simulation input On conversion.The sampling and holding that ADC converters can also synchronize, the sampling and holding of intersection, unitary sampling, ADC conversions Device can also use dma operation.

In the present embodiment, APB (Advanced Peripheral Bus) is advanced peripheral bus, AHB (Advanced High performance Bus) it is Advanced High-Performance Bus, it is total advanced high-performance can be configured using multiple pre-distributors Line AHB frequency, high-speed high-grade peripheral bus (i.e. APB2) region and low speed advanced peripheral bus is (APB1) region.Advanced height Performance bus AHB and the highest frequency in high-speed high-grade peripheral bus region are 72MHz, the highest in low speed advanced peripheral bus region Frequency is 36MHz.Advanced High-Performance Bus AHB is mainly used in the communication of system high-performance, high clock rate intermodule；It is advanced outer If bus APB is On-Chip peripheral bus, it is mainly used in the communication of On-Chip peripheral at a slow speed and kernel.

In the present embodiment, DLL is connected with CPU, and high-speed memory is connected with CPU, and each I/O interface passes through correspondingly I/O ports GPIO be connected with a wherein high-speed high-grade peripheral bus APB2, D/A converting circuit pass through one of ADC turn Parallel operation is connected with a wherein high-speed high-grade peripheral bus APB2, wherein a high-speed high-grade peripheral bus APB2 passes through height at a high speed Level peripheral bus region (i.e. AHB2APB2) is connected with Advanced High-Performance Bus AHB, and high-speed high-grade peripheral bus region also passes through Low speed advanced peripheral bus region (i.e. AHB2APB1) is connected with other high-speed high-grade peripheral bus APB2.AHB2APB2、 Data exchange controllers of the AHB2APB1 between AHB and APB.Two a/d converters be respectively 12bit ADC1IF in Fig. 1, 12bit ADC2IF, two a/d converters are 12 digit mould switching controllers.The Temp being connected with 12bit ADC2IF Sensor is internal temperature sensor.

The utility model is integrated by integrating CPU, communication bus, peripheral bus and the common hardware of voltage distribution portion A chipset is fabricated to, user can be remotely controlled or transmit data by wechat, and process is relatively simple so it is used, grasps Make it is more convenient, can realize and be remotely controlled whenever and wherever possible, realize borderless and unlimited distance remote control.

Each I/O ports GPIO can by software merit rating into output (recommend or open-drain), input (with or without pull-up or Drop-down) or multiplexing peripheral functionality port.All I/O ports GPIO have high current handling capacity.In high-speed high-grade peripheral hardware The reversal rate of I/O ports GPIO on bus APB2 up to 18MHz.

In the present embodiment, the quantity of I/O interface is five, and the quantity for comparing timer circuit is four tunnels, the number of SPI interface Measure as two, the quantity of serial interface circuit is three, and the quantity of IIC interface circuits is two, the quantity of four-way timer For three.Certainly, under the certain situation of the present embodiment, the quantity of I/O interface, the quantity for comparing timer circuit, serial interface The quantity of the quantity of circuit, the quantity of IIC interface circuits and four-way timer can also be other quantity, can be according to specific Situation adjusts accordingly.

In the present embodiment, the also built-in trace port interface unit TPIU of the wechat remote control chip, joint test work Group standard test protocols interface SW/JTAG, tracking/trigger Trace/Trig, nested vector interrupt unit NVIC, tracing control Device Trace Controller and direct memory access unit GP DMA, wherein, trace port interface unit TPIU and tracking are controlled Device Trace Controller processed are connected with tracking/trigger Trace/Trig, joint test working group standard test protocols Interface SW/JTAG, tracking/trigger Trace/Trig and nested vector interrupt unit NVIC are connected with CPU, and direct internal memory is deposited Unit GP DMA are taken to be connected by bus matrix Bus Matrix with nested vector interrupt unit NVIC.

Joint test working group standard test protocols interface SW/JTAG is that (IEEE1149.1 is simultaneous for international standard test protocol Hold), it is mainly used in chip internal test；Nested vector interrupt unit NVIC is nested vector interrupt controller, different for managing Reason condition；Meet memory access unit GP DMA and use direct memory access mode, be that one kind is directly deposited without CPU from internal memory The data exchange mode for evidence of fetching；Bus matrix Bus Matrix are used for internal exchange of data.

In Fig. 1, Pbus is p buses, for connecting tracking control unit；Ibus is I buses, for connecting flash memory (i.e. Flash 128KB 64bit)；Dbus is D buses, for connecting bus matrix Bus Matrix；System is interruption system Bus, for connecting bus matrix Bus Matrix.

In the present embodiment, wechat remote control chip also built-in power administrative unit Supply supervision, power supply Administrative unit Supply supervision are used for Power Supply Monitoring, reset circuit and PMU Supply Supervision connections, electrification reset built in PMU Supply supervision/power-off restoration module POR/ PDR and programmable voltage detector PVD.

Electrification reset module POR function is before vdd voltage rises cross defined threshold value from low to high, keeps core Piece resets, after a bit of time after this threshold value is crossed (lag time resets sluggish), terminate to reset and take reset to Amount, start execute instruction.In addition, also there is following function in electrification reset module POR：It is decreased past from high to low in vdd voltage After defined threshold value, reset will be produced in chip internal.

Programmable voltage detector PVD effect be monitoring supply voltage, supply voltage drop to given threshold value with When lower, an interruption is produced, notice software does emergent management.When supply voltage returns to more than given threshold values again, also can An interruption is produced, notifies software service restoration.The threshold value that the threshold value declined rises with power supply of powering has a fixed difference, The purpose for introducing this difference is to prevent voltage from slightly being shaken up and down in threshold value, and continually produces interruption.

In Fig. 1, Rst is internal reset circuit, and Int is internal interrupt.

In the present embodiment, also built-in external interrupt wakeup port EXTI WAKEUP of the wechat remote control chip, four Individual timer (i.e. TM1, TM2, TM3, TM4), two SPI ports (i.e. SPI1, SPI2), three USART ports (i.e. USART1, USART2, USART3), two I2C ports (i.e. I2C1, I2C2) and a USB device controller USB 2.0FS, external wake Circuit is connected by external interrupt wakeup port with a wherein high-speed high-grade peripheral bus, is compared timer circuit and is passed through wherein One timer (i.e. TM1) is connected with a wherein high-speed high-grade peripheral bus APB2, its excess-three timer (i.e. TM2, TM3, TM4) connected respectively with corresponding four-way timer, each SPI interface circuitry passes through corresponding SPI port and corresponding high speed Advanced peripheral bus APB2 connections, each serial interface circuit pass through corresponding USART ports and corresponding high-speed high-grade peripheral hardware Bus APB2 connections, IIC interface circuits pass through corresponding I2C ports and corresponding high-speed high-grade peripheral bus APB2 connections, USB Interface circuit is connected by USB device controller USB 2.0FS with other high-speed high-grade peripheral bus APB2.

External interrupt wakeup port EXTI WAKEUP are used for external interrupt wakeup；Five GPIO ports are that universal input is defeated Outgoing interface, five outside I/O interfaces are corresponded to respectively.Four timers (i.e. TM1, TM2, TM3, TM4) are internal timer electricity Road, for providing time reference to software；SPI port is Serial Peripheral Interface (SPI) controller, and I2C ports are IC bus control Device processed；USART ports are serial communication interface controller, and USB device controller USB 2.0FS control for USB Device.

It is noted that USB device controller USB 2.0FS follow full speed USB device (12 megabit per second) standard, end Point can have standby/arousal function by software merit rating.48MHz clocks special USB directly produce (clock source by internal main PLL Must be a HSE crystal oscillator).7 or 10 bit addressings are supported in I2C ports, support during 7 slave patterns double to seek from address Location.

USART ports have CTS the and RTS signal managements of hardware, support IrDA SIR ENDEC transmission coding/decodings, compatibility ISO7816 smart card simultaneously provides the master/slave functions of LIN.All USART ports can use dma operation.SPI port exists From or holotype under, the traffic rate of full and half duplex is up to 18 megabit per seconds.The pre-divider of 3 can produce 8 kinds of main moulds Formula frequency, it can be configured to every frame 8 or 16.All SPI ports can use dma operation.

In the present embodiment, the also built-in power supply POWER of the wechat remote control chip, two external crystal-controlled oscillations, independently see Door dog IWDG, spare interface Standby interface, real time clock unit RTC AWU, back-up registers Backup reg, Backup interface Backup interface and extension local area network bus bxCAN, power supply POWER access the electricity of input power Pressure, each external clock input circuit connect with corresponding external crystal-controlled oscillation, and independent house dog IWDG passes through spare interface Standby interface are connected with reserce cell, and real time clock circuit is connected with back-up registers Backup reg, and backup is posted Storage Backup reg and real time clock unit RTC AWU are also connected with backup interface Backup interface, backup interface Backup interface are also connected with other high-speed high-grade peripheral bus APB2.

In two external crystal-controlled oscillations, one of them is XTAL OSC 4-16MHz, supports 4-16MHz；Another is XTAL 32KHz, it is 32KHz external crystal-controlled oscillations.

In the present embodiment, also built-in frequency multiplication controller PLL＆CLOCK MANAGT of the wechat remote control chip, internal RC Oscillator and outside RC oscillators, internal RC oscillators are connected with frequency multiplication controller PLL＆CLOCK MANAGT, frequency multiplication controller PLL＆CLOCK MANAGT are also connected with one of external crystal-controlled oscillation, and outside RC oscillators are connected with independent house dog IWDG.Its In, internal RC oscillators are the RC 8MHz in Fig. 1, and outside RC oscillators are the RC 40KHz in Fig. 1.

Independent house dog IWDG is used for application program caused by detecting external disturbance or unpredictable logical condition away from just Normal running process and caused software fault, spare interface Standby interface are standard interface controller, real-time clock Unit R TC AWU are internal real time clock circuit, and main pulse during for producing, back-up registers Backup reg are used in CPU The data in register are made not change during reset, backup interface Backup interface are back-up registers interfaces.

In Fig. 1, PCLK1, PCLK2 are used to supply clock signal for APB buses, and HCLK is used to supply clock for ahb bus Signal, FCLK are used to supply clock signal to CPU, and RC 8MHz are 8MHz resistance-capacitance oscillating circuit, and RC 40KHz are 40KHz resistance-capacitance oscillating circuit.

Internal RC oscillators are chosen as the cpu clock of acquiescence, can select outside 4~16MHz clocks；When detecting outside When clock fails, it will be isolated, and system will automatically switch to internal RC oscillators, if opening interruption, software can connect Receive corresponding interruption.Equally, can take when needed to the complete interrupt management of pll clock (as used indirectly when one Outside RC oscillators failure when).

In the present embodiment, the wechat remote control chip also built-in window house dog WWDG, window house dog WWDG with it is another Outer high-speed high-grade peripheral bus APB2 connections.Window house dog WWDG is used to detect external disturbance or unpredictable logic bar The CPU built in hardware CRC in normal run sequence and caused software fault, the present embodiment of application program caused by part occurs Device/checker (not shown), CRC generators/checker can use dma operation and support SMBus buses 2.0 editions/ PMBus buses.

In the present embodiment, the also built-in 512 byte static RAM of the wechat remote control chip, i.e. in Fig. 1 SRAM 512B.

In a word, in the present embodiment, the general of this several part is distributed by integrating CPU, communication bus, peripheral bus and voltage Hardware, operation program is write, hardware and software is encapsulated, integrated and make a chipset.In chip program, use Transmission Control Protocol sends operation information by modern communications technology, connects corresponding application server, then explained by http protocol and Forwarding information, socket director datas bag is then sent to hardware terminal by 3G/4G/WIFI/ Ethernets, finally by hardware Terminal receives the level pulse control signal that I/O ports are construed to after socket director data bags, is output to the wechat and remotely controls In the respective gut of coremaking piece.

Use the wechat remote control chip, it is allowed to which user is remotely controlled or transmitted data by wechat, can remotely control Motor processed rotates, switch closes and remote control, can extend up to 2,000 signalizing activities；Support camera access control System, carries out remote monitoring in wechat.This chipset is applied to make various Remote equipment such as Household intelligent devices and work Industry equipment remote detection diagnosis etc.；And it is supplied to smart machine developer to carry out secondary development use, and businessman is without carrying out Any underlying hardware Software for Design.Respiratory function is designed in the communication process of canned program simultaneously, ensures that the wechat is long-range Each hardware components of control chip can be corresponding at any time, effectively avoids prolonging when being absorbed in net dormancy state and being waken up once again Slow or unpredictable mistake.

Preferred embodiment of the present utility model is the foregoing is only, it is all at this not to limit the utility model Within the spirit and principle of utility model, any modification, equivalent substitution and improvements made etc., the utility model should be included in Protection domain within.

Claims (10)

1. a kind of wechat remote control chip, it is characterised in that provided with a hardware debugging interface, a DLL, reset Circuit, external wake circuit, multiple I/O interfaces, multichannel compare timer circuit, multiple SPI interface circuitries, multiple serial interfaces Circuit, a D/A converting circuit, usb circuit, multiple IIC interface circuits, multiple four-way timers, one it is real-time when Clock circuit, two external clock input circuits, a reserce cell and input power, the wechat remote control chip are also built-in CPU, high-speed memory, multiple I/O ports, two ADC converters, two high-speed high-grade peripheral bus and an advanced high-performance Bus, the DLL are connected with the CPU, and the high-speed memory is connected with the CPU, and each I/O interface is logical Cross corresponding I/O ports to be connected with the wherein one high-speed high-grade peripheral bus, the D/A converting circuit passes through wherein one The individual ADC converters are connected with the wherein one high-speed high-grade peripheral bus, wherein a high-speed high-grade peripheral hardware is total Line is connected by high-speed high-grade peripheral bus region with the Advanced High-Performance Bus, and the high-speed high-grade peripheral bus region is also It is connected by low speed advanced peripheral bus region with the other one high-speed high-grade peripheral bus.

2. wechat remote control chip according to claim 1, it is characterised in that the quantity of the I/O interface is five, The quantity of the relatively timer circuit is four tunnels, and the quantity of the SPI interface circuitry is two, the serial interface circuit Quantity is three, and the quantity of the IIC interface circuits is two, and the quantity of the four-way timer is three.

3. wechat remote control chip according to claim 2, it is characterised in that also built-in trace port interface unit, Joint test working group standard test protocols interface, tracking/trigger, nested vector interrupt unit, tracking control unit and directly Memory access unit, the trace port interface unit and tracking control unit are connected with the tracking/trigger, the joint Test job group standard test protocols interface, tracking/trigger and nested vector interrupt unit are connected with the CPU, described Direct memory access unit is connected by bus matrix with the nested vector interrupt unit.

4. wechat remote control chip according to claim 3, it is characterised in that built-in power administrative unit is gone back, it is described Reset circuit is connected with the PMU, electrification reset built in the PMU/power-off restoration module and can Program voltage detector.

5. the wechat remote control chip according to Claims 1-4 any one, it is characterised in that also built-in one outer Portion, which is interrupted, wakes up port, four timers, two SPI ports, three USART ports, two I2C ports and a USB device Controller, the external wake circuit pass through the external interrupt wakeup port and a wherein high-speed high-grade peripheral bus Connection, the relatively timer circuit are connected by timer one of them described and the wherein one high-speed high-grade peripheral bus Connect, its excess-three timer connects with the corresponding four-way timer respectively, and each SPI interface circuitry passes through Corresponding SPI port connects with the corresponding high-speed high-grade peripheral bus, and each serial interface circuit passes through corresponding USART ports connect with the corresponding high-speed high-grade peripheral bus, and the IIC interface circuits pass through the corresponding I2C ends Mouth connects with corresponding high-speed high-grade peripheral bus, and the usb circuit passes through the USB device controller and other one The high-speed high-grade peripheral bus connection.

6. the wechat remote control chip according to Claims 1-4 any one, it is characterised in that also built-in power supply electricity Source, two external crystal-controlled oscillations, independent house dog, spare interface, real time clock unit, back-up registers, backup interface and extension office Area network bus, the power supply access the voltage of the input power, each external clock input circuit with it is corresponding External crystal-controlled oscillation connection, the independent house dog is connected by the spare interface with the reserce cell, described real-time Clock circuit is connected with the back-up registers, and the back-up registers and real time clock unit also connect with the backup interface Connect, the backup interface is also connected with the other one high-speed high-grade peripheral bus.

7. wechat remote control chip according to claim 6, it is characterised in that also built-in frequency multiplication controller, internal RC Oscillator and outside RC oscillators, the internal RC oscillators are connected with the frequency multiplication controller, the frequency multiplication controller also with One of them described external crystal-controlled oscillation connection, the outside RC oscillators are connected with the independent house dog.

8. wechat remote control chip according to claim 7, it is characterised in that also built-in window house dog, the window Mouth house dog is connected with the other one high-speed high-grade peripheral bus.

9. wechat remote control chip according to claim 1, it is characterised in that the CPU built in hardware CRC occurs Device/checker.

10. wechat remote control chip according to claim 3, it is characterised in that the high-speed memory includes 128K The flash memory of byte and the SRAM of 20K bytes, the flash memory of the 128K bytes are connected by flash interface with the CPU, the 20K The SRAM of byte is connected by the bus matrix with the CPU.