CN208638364U - A kind of LVDS bus detection system based on Ethernet - Google Patents
A kind of LVDS bus detection system based on Ethernet Download PDFInfo
- Publication number
- CN208638364U CN208638364U CN201821078880.4U CN201821078880U CN208638364U CN 208638364 U CN208638364 U CN 208638364U CN 201821078880 U CN201821078880 U CN 201821078880U CN 208638364 U CN208638364 U CN 208638364U
- Authority
- CN
- China
- Prior art keywords
- lvds
- ethernet
- programmable chip
- module
- detection system
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Landscapes
- Small-Scale Networks (AREA)
Abstract
The utility model discloses a kind of LVDS bus detection system based on Ethernet interface, comprising: is used for prosecutor equipment real-time communication, the LVDS module that realization LVDS is monitored and data, instruction respond；For controlling the programmable chip FPGA of LVDS module；For the data passed down being encoded to generate the programmable chip S698PM for accordingly meeting protocol signal；The ethernet communication module of data exchange is carried out for realizing host computer and programmable chip S698PM；And the power module for powering to entire detection system.The LVDS module is connect with programmable chip FPGA, carries out data communication by parallel data bus line between the programmable chip FPGA and programmable chip S698PM, and the programmable chip S698PM is connect with ethernet communication module.This system integrates multiple signals, makes full use of Ethernet high transfer rate, versatile advantage so that the module have the characteristics that it is highly integrated, multi-functional, small in size, versatile.
Description
" technical field "
The utility model relates to infomation detection fields, and in particular to a kind of LVDS bus detection system based on Ethernet.
" background technique "
Based on the core component that Ethernet interface LVDS bus detection system is in satellite prosecutor equipment, it is mainly used for completing
The Detection tasks such as satellite control, Star Service management, data processing.The complexity that satellite can complete task largely depends on
In control ability and data-handling capacity based on Ethernet interface LVDS bus detection system.With advances in technology, satellite
On sensor obtain information it is increasing, the scientific equipment of Seeds of First Post-flight is more and more, satellite carry out task increasingly
Complicated these are required can be provided powerful data processing and accurately be defended based on Ethernet interface LVDS bus detection system
Star control ability etc..In addition, be work in electromagnetic environment complex environment based on Ethernet interface LVDS bus detection system,
So that must have very high reliability based on Ethernet interface LVDS bus detection system.Therefore highly reliable, high-performance is developed
The demand based on Ethernet interface LVDS bus detection system it is more more and more urgent.
" utility model content "
The utility model is intended to provide a kind of highly reliable, high performance LVDS bus detection system based on Ethernet.
The technical solution adopted in the utility model is as follows: a kind of LVDS bus detection system based on Ethernet,
Include:
LVDS module realizes that LVDS is monitored and data, instruction respond with prosecutor equipment real-time communication；
Programmable chip FPGA, for controlling LVDS module；
Programmable chip S698PM, for encoding the data passed down to generate the signal for accordingly meeting agreement；
Ethernet communication module carries out data exchange for realizing host computer and programmable chip S698PM；
Power module, for powering to entire detection system；
The LVDS module is connect with programmable chip FPGA, the programmable chip FPGA and programmable chip S698PM
Between data communication carried out by parallel data bus line, the programmable chip S698PM connect with ethernet communication module.
Further, the LVDS module includes LVDS receiving element and LVDS transmitting element.
Further, the ethernet communication module includes that Ethernet interconnected connects bridging chip and Ethernet connects
Mouthful, the ethernet bridging chip is connect with programmable chip S698PM, and the Ethernet interface is connect with host computer.
Further, the Ethernet meets the model RTL8201BL of bridging chip.
Further, the programmable chip S698PM includes:
First state control unit；
First processor unit, the data communication for controlling ethernet communication module, between processing and host computer；
Communication unit, the first processor unit are connect by communication unit with ethernet communication module.
Further, FLASH module connected to it and SRAM module are additionally provided with outside programmable chip S698PM.
Further, the programmable chip FPGA includes:
Data storage cell；
Second status control unit, for controlling LVDS receiving element and LVDS transmitting element；
Second processor unit, for controlling the work between each unit and between external each component.
Further, the LVDS receiving element forms 32 tunnel analog signal input channels, and 32 tunnel analog signal is defeated
Enter the connector that channel uses model SNJ55LVDS32W.
Further, the LVDS transmitting element forms 32 road analog signal output channels, and 32 tunnel analog signal is defeated
Channel uses the connector of model SNJ55LVDS31W out.
32 road LVDS transmitting elements and 32 road LVDS receiving elements are provided, parallel interface and UART asynchronous serial is supported to connect
Mouthful.Its function includes that (1) system has 32 road LVDS transmission and 32 road LVDS reception connection function, per mutually indepedent all the way；(2)
Receive per LVDS all the way and the LVDS of LVDS synchronous parallel interface, which are sent, can become synchronous parallel interface by software configuration；
(3) the clock maximum of synchronous parallel interface supports 50MHz, and parallel interface sending and receiving data is received and dispatched as a data frame, number
It is up to 45Khz according to the frequency of frame, frame data are up to 20 bytes；(4) system maximum supports 10 tunnels simultaneously and concurrently receiving interface
With 10 tunnels simultaneously and concurrently transmission interface；(5) LVDS Asynchronous Serial Interface, 32 tunnels, which receive, and 32 tunnels are sent can pass through software configuration
As Asynchronous Serial Interface, the communication baud rate of Asynchronous Serial Interface is up to 2Mbps；(6) system maximum supports 32 roads asynchronous
Serial received interface and 32 road asynchronous serial transmission interfaces.
Further, the model EP3C55F486 of the programmable chip FPGA.
Beneficial effect provided by the utility model is: passing through a kind of LVDS bus detection system based on Ethernet of design
System, the advantages of multichannel LVDS signal is received with sending one, making full use of Ethernet high transfer rate by Ethernet interface,
So that the module has the features such as highly integrated, multi-functional, small in size, versatile；And hardware logic realization physical layer (PHY),
The functions such as signals layer, character layer, switching layer and layer data packet agreement；This system can be responsible for satellite control, including Satellite Attitude
The detection of the data communications such as state and orbits controlling, satellitosis management has and meets the various data processings of satellite and transaction controlling
The performance of detection.
" Detailed description of the invention "
The utility model will illustrate by example and with reference to the appended drawing, in which:
Fig. 1 is the utility model overall structure block diagram；
Fig. 2 is the internal structure block diagram of the utility model.
" specific embodiment "
With reference to the accompanying drawing, the utility model is described in detail.
In order to make the purpose of the utility model, technical solutions and advantages more clearly understood, below in conjunction with attached drawing and implementation
Example, the present invention will be further described in detail.It should be appreciated that specific embodiment described herein is only used to explain
The utility model is not used to limit the utility model.
As shown in Figure 1 and Figure 2, a kind of LVDS bus detection system based on Ethernet interface, comprising: for being set with ground inspection
Standby real-time communication realizes that LVDS monitors the LVDS module with data, instruction response；For controlling the programmable chip of LVDS module
FPGA；For the data passed down being encoded to generate the programmable chip S698PM for accordingly meeting protocol signal；For reality
Existing host computer and programmable chip S698PM carry out the ethernet communication module of data exchange；And for entire detection system
The power module of power supply.The LVDS module is connect with programmable chip FPGA, the programmable chip FPGA and programmable core
Data communication, the programmable chip S698PM and ethernet communication module are carried out by parallel data bus line between piece S698PM
Connection.
The LVDS module includes LVDS receiving element and LVDS transmitting element.The LVDS receiving element forms 32 road moulds
Quasi- signal input channel, the 32 tunnel analog signal input channel use the connector of model SNJ55LVDS32W.It is described
LVDS transmitting element forms 32 road analog signal output channels, and the 32 road analog signal output channel uses model
The connector of SNJ55LVDS31W.
The ethernet communication module includes that Ethernet interconnected connects bridging chip and Ethernet interface, the ether
Net bridging chip is connect with programmable chip S698PM, and the Ethernet interface is connect with host computer.The programmable chip
S698PM includes: first state control unit；First processor unit, for controlling ethernet communication module, processing with it is upper
Data communication between machine；Communication unit, the first processor unit are connect by communication unit with ethernet communication module.?
FLASH module connected to it and SRAM module are additionally provided with outside programmable chip S698PM.The programmable chip FPGA
It include: data storage cell；Second status control unit, for controlling LVDS receiving element and LVDS transmitting element；At second
Device unit is managed, for controlling the work between each unit and between external each component.Power module, input power interface be+
28V direct current, output have+2.5V/+1.2V/+1.0V/+3.3V/+1.8V/+28V/+12V/+5V.Programmable chip S698PM
System control is realized using the SOC chip and programmable chip fpga chip of SPARC framework, completes Ethernet protocol stack, LVDS
Data parsing, the data exchange with ground.
In the present embodiment, ethernet bridging chip concrete model is RTL8201BL；Programmable chip model S698PM
With EP3C25F324 Series FPGA, wherein programmable chip S698PM be responsible for by ethernet bridging chip and host computer communication,
Host computer instruction is given to programmable chip FPGA to be further processed by parallel data bus line, programmable chip FPGA is then
The control sended and received to LVDS signal is realized by reading the instruction that programmable chip S698PM is transmitted.
When utility model works, Ethernet interface is connect with host computer, and the interface of physical layer passes through transit cable
It is connect with external equipment, realizes that host computer and external equipment carry out LVDS communication.Its workflow specifically includes two processes: hair
It send data workflow and receives data workflow.
Send data workflow:
Upper layer test software is run first on host computer, and the relevant parameter of sendaisle is set by it, setting
Parameter includes sending information, the information such as signal type, sendaisle, transmission baud rate to be sent to and can compile by Ethernet interface
First processor unit in journey chip S698PM, programmable chip S698PM controlled according to the parameter that host computer passes down
One status control unit, is arranged the related register parameter of sendaisle, and status register, clock division register, data are deposited
Memory register carries out parameter configuration, completes the initialization operation of sendaisle.Then user is again by running on the inspection of host computer
Software is surveyed, data packet is sent through Ethernet interface by industry ethernet, which is compiled by programmable chip FPGA
Code, can be transmitted a signal on SNJ55LVDS31W connector, then pass through switching according to unlike signal type by LVDS module
Cable is sent to external equipment.
Receive data workflow:
Host computer test software is run first on host computer, the relevant parameter of receiving channel is set by it, is arranged
Parameter include receiving signal type, receiving channel, receiving the information such as baud rate, which is sent to by Ethernet interface can
Chip S698PM is programmed, the first processor unit on programmable chip S698PM controls the according to the parameter that host computer passes down
One status control unit, is arranged the related register parameter of receiving channel, and status register, clock division register, data are deposited
Memory register carries out parameter configuration, completes the initialization operation of receiving channel.Then, LVDS module is according to different signal types
Level conversion is carried out, is transferred to programmable chip FPGA, programmable chip FPGA is connect after being decoded to signal by Ethernet
Mouth is uploaded to host computer.
Above embodiments are only sufficiently open rather than limitation the utility model, all creation purports based on the utility model,
The replacement of equivalence techniques feature without creative work should be considered as the range of the application exposure.
Claims (10)
1. a kind of LVDS bus detection system based on Ethernet characterized by comprising
LVDS module realizes that LVDS is monitored and data, instruction respond with prosecutor equipment real-time communication；
Programmable chip FPGA, for controlling LVDS module；
Programmable chip S698PM, for encoding the data passed down to generate the signal for accordingly meeting agreement；
Ethernet communication module carries out data exchange for realizing host computer and programmable chip S698PM；
Power module, for powering to entire detection system；
The LVDS module is connect with programmable chip FPGA, between the programmable chip FPGA and programmable chip S698PM
Data communication is carried out by parallel data bus line, the programmable chip S698PM is connect with ethernet communication module.
2. the LVDS bus detection system based on Ethernet as described in claim 1, which is characterized in that the LVDS module includes
LVDS receiving element and LVDS transmitting element.
3. the LVDS bus detection system based on Ethernet as claimed in claim 2, which is characterized in that the ethernet communication mould
Block includes that Ethernet interconnected connects bridging chip and Ethernet interface, the ethernet bridging chip and programmable chip
S698PM connection, the Ethernet interface are connect with host computer.
4. the LVDS bus detection system based on Ethernet as claimed in claim 3, which is characterized in that the Ethernet connects bridge joint
The model RTL8201BL of chip.
5. the LVDS bus detection system based on Ethernet as claimed in claim 3, which is characterized in that the programmable chip
S698PM includes:
First state control unit；
First processor unit, the data communication for controlling ethernet communication module, between processing and host computer；
Communication unit, the first processor unit are connect by communication unit with ethernet communication module.
6. the LVDS bus detection system based on Ethernet as claimed in claim 3, which is characterized in that in programmable chip
FLASH module connected to it and SRAM module are additionally provided with outside S698PM.
7. the LVDS bus detection system based on Ethernet as claimed in claim 2, which is characterized in that the programmable chip
FPGA includes:
Data storage cell；
Second status control unit, for controlling LVDS receiving element and LVDS transmitting element；
Second processor unit, for controlling the work between each unit and between external each component.
8. the LVDS bus detection system based on Ethernet as claimed in claim 7, which is characterized in that the LVDS receiving element
32 tunnel analog signal input channels are formed, the 32 tunnel analog signal input channel uses the connection of model SNJ55LVDS32W
Device.
9. the LVDS bus detection system based on Ethernet as claimed in claim 7, which is characterized in that the LVDS transmitting element
32 road analog signal output channels are formed, the 32 road analog signal output channel uses the connection of model SNJ55LVDS31W
Device.
10. the LVDS bus detection system based on Ethernet as claimed in claim 7, which is characterized in that the programmable chip
The model EP3C55F486 of FPGA.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821078880.4U CN208638364U (en) | 2018-07-09 | 2018-07-09 | A kind of LVDS bus detection system based on Ethernet |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821078880.4U CN208638364U (en) | 2018-07-09 | 2018-07-09 | A kind of LVDS bus detection system based on Ethernet |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN208638364U true CN208638364U (en) | 2019-03-22 |
Family
ID=65736644
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201821078880.4U Active CN208638364U (en) | 2018-07-09 | 2018-07-09 | A kind of LVDS bus detection system based on Ethernet |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN208638364U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112782562A (en) * | 2021-01-05 | 2021-05-11 | 珠海欧比特宇航科技股份有限公司 | ATE-based SOC chip low-voltage differential signal testing method and device |
| CN115729150A (en) * | 2022-11-22 | 2023-03-03 | 广东安达智能装备股份有限公司 | Control method of track controller, track controller and storage medium |
-
2018
- 2018-07-09 CN CN201821078880.4U patent/CN208638364U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112782562A (en) * | 2021-01-05 | 2021-05-11 | 珠海欧比特宇航科技股份有限公司 | ATE-based SOC chip low-voltage differential signal testing method and device |
| CN115729150A (en) * | 2022-11-22 | 2023-03-03 | 广东安达智能装备股份有限公司 | Control method of track controller, track controller and storage medium |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104809094B (en) | SPI controller and its communication means | |
| CN104426950B (en) | A kind of electric power Internet of Things intelligent communication method and system and intelligence communication gateway | |
| CN105893307B (en) | A kind of high speed big data quantity information processing system | |
| CN107980215A (en) | A kind of protocol converter and method for converting protocol | |
| CN105959288A (en) | Network protocol conversion method for power grid system and intercommunication method of power grid system | |
| CN106162528B (en) | LoRa signal and Bluetooth signal conversion module, conversion method and sender unit | |
| CN105051706A (en) | Device, method and system for operation of a low power PHY with a PCIe protocol stack | |
| CN105337421A (en) | Protocol conversion method and mutual communication method in intelligent power network system | |
| CN104050139A (en) | Method, apparatus, and system for improving inter-chip and single-wire communication for a serial interface | |
| US20120030380A1 (en) | Transmission device, transmission method, and control program for transmission device | |
| CN208638364U (en) | A kind of LVDS bus detection system based on Ethernet | |
| CN202190284U (en) | Protocol converter for CAN bus and SpaceWire bus | |
| CN104915303A (en) | High-speed digital I/O system based on PXIe bus | |
| CN104156333A (en) | FPGA-based UART multi-interface extension system and method | |
| CN104991880B (en) | A kind of FC AE ASM Communication Cards based on PCI E interfaces | |
| CN106445853A (en) | Transformation method of SPI (Serial Peripheral Interface) and UART (Universal Asynchronous Receiver/Transmitter) interface on the basis of FPGA (Field Programmable Gate Array) | |
| CN105137864A (en) | Lower computer coordinative control SoC chip for spacecraft | |
| CN109634673A (en) | Satellite borne electronic system management and control equipment | |
| CN107436851A (en) | The line shielding system of Serial Peripheral Interface (SPI) four and its control method | |
| CN205091734U (en) | SpaceWire bus node communication module based on CPCI interface | |
| CN205103813U (en) | SpaceWire bus node communication module based on PCI interface | |
| CN208386579U (en) | A kind of 1553B bus detection system based on Ethernet | |
| CN110401586A (en) | A kind of bus communication, device, equipment and readable storage medium storing program for executing | |
| CN202111737U (en) | Network management enhanced E1/ETH protocol converter | |
| CN206684533U (en) | Wechat remote control chip |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant |