CN113704834A

CN113704834A - Intelligent destroying method based on Feiteng processor

Info

Publication number: CN113704834A
Application number: CN202110942199.XA
Authority: CN
Inventors: 李修录; 尹善腾; 朱小聪; 吴健全
Original assignee: Axd Anxinda Memory Technology Co ltd
Current assignee: Axd Anxinda Memory Technology Co ltd
Priority date: 2021-08-17
Filing date: 2021-08-17
Publication date: 2021-11-26
Anticipated expiration: 2041-08-17
Also published as: CN113704834B

Abstract

The invention discloses an intelligent destroying method based on a Feiteng processor, which is applied to an embedded memory chip, wherein an embedded memory chip board is attached to the Feiteng processor, and the embedded memory chip is electrically connected with the Feiteng processor, and the method comprises the following steps: receiving a destruction signal transmitted by the Feiteng processor, wherein the destruction signal is used for indicating the embedded memory chip to erase the memory data stored in the embedded memory chip by the Feiteng processor; when a destroying signal transmitted by the Feiteng processor is received, monitoring the duration time of the destroying signal; judging whether the duration time meets the preset time or not; if the duration time meets the preset time, determining to enter an erasing execution state, and erasing the stored data based on the erasing execution state; judging whether the erasing operation is finished or not according to a preset judgment condition; and entering a standby state if the erasing operation is determined to be completed. The invention improves the safety of the stored data and reduces the risk of data leakage.

Description

Intelligent destroying method based on Feiteng processor

Technical Field

The embodiment of the invention relates to the technical field of chip processing, in particular to an intelligent destroying method based on a Feiteng processor.

Background

With the development of information technology, higher requirements are put forward on the attention of information security and confidentiality, the requirement of adopting an autonomous platform server is continuously expanded, and the requirement on a mainboard is higher and higher in a specific environment.

At present, a multi-CPU (Central Processing Unit/Processor) applied to most of computer products in China is designed by adopting a foreign CPU chip, and because a back door is reserved on the chip, the foreign CPU chip is applied to a domestic computer system, and the safety and confidentiality of information are difficult to ensure. Thus, home-made chips have come up, such as Feiteng processors. However, if the data amount is too large, the cpu load of the soar processor becomes too large, and the operation speed is reduced. Therefore, the storage product with large capacity is externally connected, but the existing storage product is as follows: the shock resistance is poor; when the cpu of the Feiteng processor is attacked, the safety of the data of the Feiteng processor can not be ensured, and the risk of data leakage is increased.

Disclosure of Invention

In view of the above, an object of the embodiments of the present invention is to provide an intelligent destruction method based on a FT processor, so as to solve the problems of poor earthquake resistance and low data security in the prior art.

In order to achieve the above object, an embodiment of the present invention shows an intelligent destruction method based on a FT processor, which is applied to an embedded memory chip, wherein an embedded memory chip board is attached to the FT processor, and the embedded memory chip is electrically connected to the FT processor, and the method includes:

receiving a destruction signal transmitted by the Feiteng processor, wherein the destruction signal is used for instructing the embedded memory chip to erase the memory data stored in the embedded memory chip by the Feiteng processor;

when a destruction signal transmitted by the Feiteng processor is received, monitoring the duration time of the destruction signal;

judging whether the duration time meets a preset time or not;

if the duration time meets the preset time, determining to enter an erasing execution state, and erasing the stored data based on the erasing execution state;

judging whether the erasing operation is finished or not according to a preset judgment condition; and

and entering a standby state if the erasing operation is determined to be finished.

Further, the method further comprises:

when the state is in the erasing execution state, if any control signal of the Feiteng processor or other servers is received, the state is changed into a fault processing state from the erasing execution state; any one of the control signals is used for indicating the embedded memory chip to enter a corresponding task execution state; and

generating an error signal responding to any one control signal, and returning the error signal to the Feiteng processor or other processors, wherein the error signal is used for indicating that the embedded memory chip fails to enter the corresponding task execution state; and

and after the error signal is sent, entering the erasing execution state from the fault processing state so as to continue the erasing operation.

Further, the method further comprises:

when the embedded memory chip is in the erasing execution state, if a power supply circulating signal is received, entering an erasing pause state from the erasing execution state, wherein the power supply circulating signal is used for indicating the embedded memory chip to execute power supply circulating operation;

executing power supply circulation operation according to the power supply circulation signal; and

and when the power supply cycle operation is completed, entering the erasing execution state from the erasing pause state so as to continue the erasing operation.

Furthermore, the embedded memory chip comprises a plurality of groups of first differential signal transmitting and receiving pin pairs, and the plurality of groups of first differential signal transmitting and receiving pin pairs correspond to a plurality of groups of second differential signal transmitting and receiving pin pairs of the Feiteng processor one by one;

the method further comprises the following steps:

and constructing a signal transmission channel between the embedded memory chip and the Feiteng processor in advance according to the corresponding relation between the plurality of groups of first differential signal transmitting and receiving pin pairs and the corresponding groups of second differential signal transmitting and receiving pin pairs.

Furthermore, the embedded memory chip comprises a control module, a flash memory module, a cache module and an input/output interface module.

Furthermore, the control module, the flash memory module, the cache module and the input/output interface module are packaged in the embedded memory chip by BGA technology.

Furthermore, the embedded memory chip is connected with an external power supply through an external power supply circuit, and the power supply circuit is used for supplying power to the embedded memory chip;

prior to said receiving a destruction signal transmitted by said Feiteng processor, said method further comprising:

receiving a first voltage transmitted by a first output end of the power supply circuit through the control module;

receiving a second voltage transmitted by a second output end of the power supply circuit through the input/output interface module;

receiving, by the cache module, a third voltage transmitted by a third output terminal of the power supply circuit;

and receiving a fourth voltage transmitted by a fourth output end of the power supply circuit through the flash memory module.

Further, the first voltage, the second voltage, the third voltage and the fourth voltage are voltages transmitted to the embedded memory chip by a voltage sequence control circuit in the power supply circuit according to a preset power-on sequence.

Further, the power supply circuit includes a first power supply circuit and a second power supply circuit, the first power supply circuit is configured to transmit the first voltage to the control module, transmit the second voltage to the input/output interface module, and transmit the fourth voltage to the flash memory module, and the second power supply circuit is configured to transmit the third voltage to the cache module;

one or more first decoupling capacitors for energy storage, one or more second decoupling capacitors for energy storage and one or more third decoupling capacitors for energy storage are connected to the first power supply circuit; one or more fourth decoupling capacitors for energy storage are connected to the second power supply circuit;

the method further comprises the following steps:

if the external power supply is disconnected from the power supply circuit, the external power supply is connected to the power supply circuit

Receiving, by the control module, a fifth voltage provided by the first decoupling capacitor;

receiving a sixth voltage provided by the second decoupling capacitor through the input-output interface module;

receiving, by the flash memory module, a seventh voltage provided by the third decoupling capacitor;

receiving, by the cache module, an eighth voltage provided by the fourth decoupling capacitor.

In order to achieve the above object, an embodiment of the present invention shows an intelligent destruction method based on a FT processor, where the FT processor is electrically connected to an embedded memory chip, and the embedded memory chip board is attached to the FT processor; the method comprises the following steps:

sending a destruction signal to the embedded memory chip through the Feiteng processor, wherein the destruction signal is used for indicating the embedded memory chip to erase the memory data stored in the embedded chip by the Feiteng processor;

executing the following operations by the embedded memory chip:

receiving the destruction signal;

judging whether the duration time meets a preset time or not;

The intelligent destruction method based on the Feiteng processor provided by the embodiment of the invention is connected with the embedded memory chip, so that the memory capacity is increased, and the embedded memory chip is pasted on the Feiteng processor; after the embedded memory chip receives the destruction signal of the Feiteng processor, the destruction function can be started to destroy the stored data stored in the embedded memory chip, and the safety of the data is ensured.

Drawings

Fig. 1 is a schematic diagram of an environmental application of the intelligent destruction method based on the FT processor according to the present invention.

Fig. 2 is a flowchart of a first embodiment of an intelligent destruction method based on a FT processor according to the present invention.

Fig. 3 is a flowchart of steps S200 to S204 in a first embodiment of an intelligent destruction method based on a FT processor.

Fig. 4 is a flowchart illustrating steps S300 to S304 in a first embodiment of an intelligent destruction method based on a FT processor according to the present invention.

Fig. 5 is a flowchart illustrating an implementation of an intelligent destruction function of an embedded memory chip according to an embodiment of the present invention.

Fig. 6 is a schematic diagram illustrating a correspondence relationship between a plurality of groups of first differential signal transceiver pin pairs and a plurality of groups of second differential signal transceiver pins according to an embodiment of the present invention.

Fig. 7-1 is a schematic structural diagram of an embedded memory chip according to an embodiment of the present invention.

Fig. 7-2 is a diagram illustrating the effect of the embedded memory chip packaged by BGA technology according to the embodiment of the present invention.

Fig. 8 is a general flowchart of the embedded memory chip implementing the intelligent destruction function in the embodiment of the present invention.

Fig. 9-1 is a circuit diagram of a first power supply circuit in an embodiment of the invention.

Fig. 9-2 is a circuit diagram of a second power supply circuit in an embodiment of the invention.

Fig. 10 is a flowchart of a second embodiment of the intelligent destruction method based on a FT processor.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

The terms most relevant to the subject matter of the invention are explained:

a Feiteng processor: also known as a Feiteng platform, is an FT2000-4 COME core board, and is mainly a high-performance general processor oriented to desktop application. FT-2000/4 integrates 4 64-bit high-performance cores with a master frequency of 2.6GHz and a built-in crypto acceleration engine.

AXD SATAIII BGA SSD embedded memory chip: the self-developed BGA package embedded Memory chip integrates a NAND flash Memory, a DRAM (Dynamic Random Access Memory) and a self-developed controller into a whole.

The inventors have appreciated that: the storage disks of domestic chip platforms such as the soar platform are all standard solid state hard disks, for example: the solid state disk of the mSATA (mini-SATA, mini SATA interface) interface and the solid state disk of the 7+15PIN (chip) interface have at least the following defects:

(1) the solid state disk of the existing Feiteng platform occupies a large space and has poor shock resistance.

(2) The existing solid state disk storage of the Feiteng platform cannot realize the destruction function, and the risk of data leakage exists.

(3) The solid state disk of the existing Feiteng platform has poor integration degree.

To address the above issues, a number of embodiments are provided below, each of which can be used to implement a flyer processor-based intelligent destruction.

Fig. 1 schematically shows an environment application diagram of the intelligent destruction method based on the FT processor according to the embodiment of the present application. In an exemplary embodiment, the environment application schematic includes a FT processor 10 and an embedded memory chip 20; the Feiteng processor 10 and the embedded memory chip 20 are connected through a SATA interface; the embedded memory chip 20 is integrated with a flash memory module, a cache module, a control module and an input/output interface module.

The application aims at providing an intelligent destruction scheme based on a Feiteng processor, and in the scheme, the intelligent destruction scheme comprises the following steps:

(1) the AXD SATAIII BGA SSD embedded memory chip board is pasted on a Feiteng platform, so that the effects of small occupied space and good shock resistance are achieved.

(2) The self-developed AXD SATAIII BGA SSD embedded memory chip can achieve the highest read-write of a standard SATA (Serial Advanced Technology Attachment, a protocol used when signals are transmitted through a Serial hardware driver interface based on an industrial standard) on the performance, meets the data interaction processing requirement of a Feiteng platform, and has an intelligent destruction function and higher safety.

(3) The self-developed AXD SATAIII BGA SSD embedded memory chip is a BGA encapsulation embedded memory chip integrating a NAND flash memory, a DRAM cache and a self-developed controller, is matched with a Feiteng platform to realize a nationwide production platform, and is used for making a chain from a domestic CPU to a domestic storage medium.

One or more embodiments are provided below to more particularly describe a Feiteng processor-based intelligent destruction scheme.

Example one

Referring to fig. 2, a flowchart of steps of an intelligent destruction method based on a FT processor according to an embodiment of the present invention is shown, where the method is applied to an embedded memory chip, the embedded memory chip board is attached to the FT processor, and the embedded memory chip is electrically connected to the FT processor. It is to be understood that the flow charts in the embodiments of the present method are not intended to limit the order in which the steps are performed. The embedded memory chip is taken as an execution subject for exemplary description. The details are as follows.

Step S100, receiving a destruction signal transmitted by the Feiteng processor, wherein the destruction signal is used for instructing the embedded memory chip to erase the memory data stored in the embedded memory chip by the Feiteng processor.

In order to improve the shock resistance of the external memory chip, the embodiment of the invention pastes the embedded memory chip board on the Feiteng processor.

Further, in order to reduce the risk of data leakage, the embodiment of the invention improves the embedded memory chip, and the intelligent destruction function starting control is carried out on the embedded memory chip through the destruction signal sent by the Feiteng processor. The destroy signal is a low level signal, the embedded memory chip is set to receive the low level signal, and the intelligent destroy function is triggered when the duration time of the low level signal is one second. The intelligent destruction function described in this embodiment is to erase the storage data embedded in the memory chip without damaging the embedded memory chip.

When the soar processor is in an emergency and cannot send a destruction signal, in order to ensure that the destruction function of the embedded memory chip is smoothly executed in an emergency, the embodiment further sets an intelligent destruction extension socket on the soar processor. The intelligent destruction extension socket is electrically connected with the enabling pin of the embedded memory chip for starting the intelligent destruction function, and the short circuit of the enabling pin is realized by the intelligent destruction extension socket cap, so that a low level is given to the enabling pin, and the intelligent destruction function starting control of the embedded memory chip is realized. The intelligent destruction function is realized by a direct cap short circuit mode, the destruction time can be guaranteed within 5 seconds, and the intelligent destruction efficiency is improved.

Step S102, when a destruction signal transmitted by the Feiteng processor is received, the duration time of the destruction signal is monitored.

In order to determine whether the intelligent destruction function needs to be started, the duration of the control signal of the Feiteng processor is monitored, and the duration can be understood as the time when the embedded memory chip continuously receives the destruction signal.

And step S104, judging whether the duration time meets the preset time.

In order to improve the efficiency of the intelligent destruction, the preset time is preferably at most one second for determining whether to perform the erasing operation. If the short circuit is formed by extension and plug, the preset time is preferably up to one second.

And step S106, if the duration time meets the preset time, determining to enter an erasing execution state, and performing erasing operation on the stored data based on the erasing execution state.

In order to ensure the progress of the erase operation, an erase execution state is set, indicating that the erase operation is started.

Step S108, judging whether the erasing operation is finished or not according to preset judgment conditions.

In order to improve the erasing efficiency, whether the erasing operation is completed is judged according to a preset judgment condition, and the judgment condition can be judgment on an erasing execution state and judgment on whether the erasing execution state is still maintained.

Step S110, if it is determined that the erasing operation is completed, entering a standby state.

After the erasing operation is finished, the embedded memory chip is changed into an initialization state, namely, enters a standby state to continue to receive data for storage.

Illustratively, referring to fig. 3, the method further comprises:

step S200, when the processor is in the erasing execution state, if any control signal of the Feiteng processor or other processors is received, the processor enters a fault processing state from the erasing execution state; any one of the control signals is used for indicating the embedded memory chip to enter a corresponding task execution state. Step S202, generating an error signal in response to any one of the control signals, and returning the error signal to the FT processor or other processors, where the error signal is used to indicate that the embedded memory chip fails to enter the corresponding task execution state. Step S204, after sending the error signal, entering the erase execution state from the failure handling state to continue the erase operation.

In order to improve the data security, the embedded memory chip sets the erase execution state to the highest level. When the embedded memory chip is in the erasing execution state, any processor sending control signals will not be executed. At the moment, the embedded memory chip enters a fault processing state, an error signal is generated and returned to the processor in the fault processing state, and the erasing operation is continuously executed after the error signal is returned, so that the stored data are completely erased.

Illustratively, referring to fig. 4, the method further comprises:

step S300, when the embedded memory chip is in the erase execution state, if a power cycling signal is received, entering an erase suspend state from the erase execution state, where the power cycling signal is used to instruct the embedded memory chip to execute a power cycling operation. And step S302, executing power supply circulation operation according to the power supply circulation signal. Step S304, after the power cycling operation is completed, entering the erase execution state from the erase suspend state to continue the erase operation.

In order to ensure the smooth execution of the erasing operation, a power supply circulation function is configured in the embedded memory chip, and when the power consumption of the embedded memory chip is insufficient, the embedded memory chip is supplied with power in time. When the embedded memory chip starts the power circulation function, a power circulation signal or a power circulation instruction is received. At this time, the erase execution state is suspended, the erase suspended state is entered, and after the power cycling operation is completed, the erase execution state is re-entered from the erase suspended state to continue the erase operation.

For better understanding of the erase function, refer to fig. 5, which is a flowchart illustrating the embedded memory chip implementing the intelligent destruction function in this embodiment. The specific description is as follows.

Before the intelligent destruction function is started, the embedded memory chip is in a QE0 state, QE 0: device _ IDLE: when the embedded memory chip is successfully powered on or any command is successfully executed, the embedded memory chip enters the state after completing the initialization process, and the QE1 state is also referred to as a standby state.

Conversion QE 0: QE1 procedure: when the embedded memory chip detects QEE set for at least 1 second, the device should switch to QE 1: quick _ Erase _ Execute. QEE are used to monitor the duration of the low level.

QE 1: quick _ Erase _ Execute state: QE1 is the erase execution state, entered when QEE-was asserted for the last 1 second. In the erasing execution state, the embedded storage chip starts to search for the storage data in all the data blocks and then erases the storage data. When the erase execution state is entered QEB-asserted by the device, QEB is used to determine if the erase operation is complete.

Conversion QE 1: QE1 procedure: in the suspended state, when power is cycled, the embedded memory chip continues to erase after the initialization process is completed.

Conversion QE 1: QE2 procedure: when all data blocks are successfully erased, the embedded memory chip should switch to QE 2: quick _ Erase _ Finish.

Conversion QE 1: QE3 procedure: when any command is issued by the Feiteng processor or other processor in the erase execution state, the command can be understood as a control signal, and the embedded memory chip should be converted to QE 3: command _ Error, failure handling status.

QE 2: quick _ Erase _ Finish state: to erase the end state, the state is entered after all data blocks have been successfully erased. When this state is entered, QEB will be cancelled by the embedded memory chip.

Conversion QE 2: QE0 procedure: after all data blocks are erased, the embedded memory chip should be converted to QE 0: device _ IDLE state.

QE 3: command _ Error status: when the Feiteng processor sends any command through a connected control pin or HRST/SRST command sent by CF/PATA hard disk equipment through a parallel port or SRST emergency command/COMREST command sent by SATA hard disk equipment through a serial port, if the embedded memory chip is in an erasing execution state for erasing all data blocks, the embedded memory chip enters the pause state, the erasing process is regarded as the highest priority, and an ERR state (fault state) is returned to the Feiteng processor by using ABRT, wherein the ABRT is a stop signal.

Conversion QE 3: QE 1: when the ERR state is returned, the embedded memory chip should continue to perform the erase process and transition to QE 1: quick _ Erase _ Execute.

The embedded memory chip needs to pay attention when the intelligent destruction function is started:

(1) before the embedded memory chip executes the intelligent destroying function, the program of the erasing function is led into the embedded memory chip through the MPtool, and the embedded memory chip is set not to enter a sleep mode all the time when the erasing function is realized. The MPtool can perform formatting, mass production and other operations on the storage device.

(2) The erase function of the embedded memory chip has the highest priority, so in this state, the embedded memory chip will not stop executing the erase function when receiving any command from any processor, including a command directly transmitted through the Feiteng processor, an HRST/SRST command transmitted through the parallel port of the CF/PATA hard disk device, and an SRST/COMREST command transmitted through the serial port of the SATA hard disk device. The serial port and the parallel port are input and output modules.

(3) If the enable pin QEE is controlled by a General-purpose input/output (GPIO) pin of the soar processor, the embedded memory chip enters the idle state, which can be understood as the standby state, and the erase function is executed when the embedded memory chip enters the idle state and activates the QEE pin for at least 1 second.

(4) If the enable pin QEE-is manually controlled, e.g., the enable pin is inadvertently pressed, the QEE-pin is activated for at least 3 seconds to enter into performing the erase function.

(5) The busy time to erase all data blocks depends on the flash configuration:

busy time = (erase time block number) + (program time block number) + (clean versus time now log). The erasing time is the erasing time of a single data block tested in advance; the block number is the number of the data block which needs to be erased currently; the program time is the time for starting an erasing function program when each data block is erased; clean pair time is the time at which each data pair is erased; the number of the matching pairs is the number of the existing data pairs in the embedded memory chip, the data pairs comprise a plurality of data blocks, and some data need to be stored by the plurality of data blocks when the data are stored to form the data pairs.

In this embodiment, the busy time of the erasing function can be controlled to be at least five seconds, so as to improve the erasing efficiency.

(6) And state description:

after the intelligent destruction is completed, the lba (logical Block address) logical Block address of the embedded memory chip is all 0, and a WinHex tool may be used to check whether the embedded memory chip is completely destroyed, so as to ensure that the embedded memory chip cannot be recovered after being destroyed and returns to an unused (before leaving the factory) state. The WinHex tool is used for checking and repairing various files, recovering deleted files, data loss caused by hard disk damage and the like.

(7) Before the intelligent destruction function is realized, a GPIO interface pin of the Feiteng memory is welded with a QE enabling pin of the embedded memory chip, the Feiteng processor provides a destruction signal for the embedded chip through the GPIO interface pin, the QE enabling pin is set to meet the low level effect, the intelligent destruction function can be triggered, all previous stored data can be erased even in the power supply cycle period, and the device can be continuously used for storing data and reformatting by a host after the function is completed.

Illustratively, the embedded memory chip comprises a plurality of groups of first differential signal transmitting and receiving pin pairs, and the plurality of groups of first differential signal transmitting and receiving pin pairs correspond to a plurality of groups of second differential signal transmitting and receiving pin pairs of the Feiteng processor one by one;

the method further comprises the following steps:

In this embodiment, in order to ensure that signal transmission can be normally implemented between the embedded memory chip and the FT processor, in an exemplary embodiment, the method further includes pre-establishing a signal transmission channel between the embedded memory chip and the FT processor. In this embodiment, the signal transmission channel may be a differential signal transmission channel. And a plurality of groups of first differential signal transmitting and receiving pin pairs arranged through the embedded memory chip correspond to a plurality of groups of second differential signal transmitting and receiving pin pairs arranged through the Feiteng processor one to one. As shown in fig. 6, a schematic diagram of a corresponding relationship between a plurality of groups of first differential signal transceiver pin pairs and a plurality of groups of second differential signal transceiver pins is shown. The embedded memory chip is provided with two groups of first differential signal transmitting and receiving pin pairs, namely a K8 pin TXN, a K9 pin TXP, a L8 pin RXN and a L9 pin RXP. And two groups of second differential signal transmitting and receiving pin pairs are correspondingly arranged on the Feiteng processor, and are respectively a SATA _ RXN pin, a SATA _ RXP pin, a SATA _ TXP pin and a SATA _ TXN pin. The correspondence of the pin pairs of the transmission interface follows the manner of RX pair TX, where RX represents reception differential signals, TX represents transmission differential signals, P represents positive polarity, and N represents negative polarity. If the embedded memory chip cannot be identified by a wrong Feiteng processor, reworking is carried out to connect the differential signal sending and receiving pin pairs in a communication mode again.

Illustratively, the embedded memory chip comprises a control module, a flash memory module, a cache module and an input/output interface module.

The embedded memory chip in the embodiment is preferably an AXD SATAIII BGA SSD embedded memory chip, which is a self-developed BGA-packaged embedded memory chip integrating a NAND flash memory module, a DRAM cache module, and a self-developed control module. The AXD SATAIII BGA SSD embedded storage chip adopts the SATAIII interface, can provide the link speed of 6Gbps speed, and enables the data transmission speed to be faster and more efficient.

In an exemplary embodiment, in order to better understand the connection relationship between the modules in the embedded memory chip, referring to fig. 7-1, a schematic structural diagram of the embedded memory chip is shown. The embedded Memory chip comprises a bus controller, a microprocessor, a Test module JTAG, a secure encoder/decoder, a UART interface, a main system buffer area, a DMA controller, a DRAM controller, a DDR3 (a computer Memory standard cache product) cache, a flash Memory controller, a flash Memory chip and a SATA interface, wherein the bus controller is connected with the microprocessor, the secure encoder/decoder, the UART interface (Universal Asynchronous Receiver/Transmitter), the main system buffer area, a DMA (Direct Memory Access) controller, a DRAM (computer Memory standard cache product) controller and the flash Memory controller, the microprocessor is connected with the Test module JTAG (Joint Test Group, mainly used for chip internal Test), the DRAM controller is connected with the DDR3 cache, the flash Memory controller is connected with the flash Memory chip, the embedded storage chip is connected with the external processor through the SATA port. The control module can be a bus controller, a microprocessor and a DMA controller, the flash memory module can be a flash memory controller and a flash memory chip, and the DRAM cache module can be a DRAM controller and a DDR3 cache. The input/output interface module can be a SATA interface and a UART interface.

Illustratively, the control module, the flash memory module, the cache module and the input/output interface module are packaged in the embedded memory chip by BGA technology.

Referring to fig. 7-2, an effect of the embedded memory chip packaged by BGA technology is shown. The BGA (ball Grid array) packaging technology is a ball Grid array packaging technology, and the high-density surface mount packaging technology. At the bottom of the package, the leads are all spherical and arranged in a grid-like pattern, hence the name BGA. The embedded memory chip packaged by adopting the BGA technology can improve the memory capacity by two to three times under the condition that the volume of the embedded memory chip is not changed, and compared with a TSOP, the BGA has smaller volume and better heat radiation performance and electrical performance. The BGA packaging technology greatly improves the storage capacity per square inch, and the volume of an embedded memory chip adopting the BGA packaging technology is only one third of that of TSOP packaging under the same capacity; compared with the traditional TSOP packaging mode, the BGA packaging mode has a faster and more effective heat dissipation way.

Illustratively, the embedded memory chip is connected with an external power supply through an external power supply circuit, and the power supply circuit is used for supplying power to the embedded memory chip;

In order to improve the power supply efficiency of the embedded cache chip, each module of the embedded memory chip is powered by a power supply circuit. The power supply circuit divides four voltage output ends. In this embodiment, the first voltage is preferably 1.1V, the second voltage is preferably 3.3V, the third voltage is preferably 1.5V, and the fourth voltage is preferably 1.8V. Namely, the supply voltage required by the control module is 1.1V, NANDflash, the supply voltage required by the flash memory module is 1.8V, DRAM, and the supply voltage required by the module buffer is 1.5V, IO, and the supply voltage required by the input/output interface module is 3.3V. The first output end of the power supply circuit is VCCK, the second output end of the power supply circuit is VCC3F, the third output end of the power supply circuit is VCCDQ, and the fourth output end of the power supply circuit is VCCFQ.

Illustratively, the first voltage, the second voltage, the third voltage and the fourth voltage are voltages transmitted to the embedded memory chip by a voltage sequence control circuit in the power supply circuit according to a preset power-on sequence. The preset power-on time sequence is 1.1V >3.3V >1.5V >1.8V, namely, the power-on time sequence is preset to be that the power-on of the voltage of 1.1V is earlier than the voltage of 3.3V, the power-on of the voltage of 3.3V is earlier than the voltage of 1.5V, and the power-on of the voltage of 1.5V is earlier than the voltage of 1.8V. If the preset power-on time sequence is not met, the situation that the disk cannot be identified occurs, namely the Feiteng processor cannot identify the embedded memory chip, so that the connection stability of the Feiteng processor and the embedded memory chip is ensured, and the Feiteng processor can normally read the embedded memory chip. The voltage time sequence control circuit can ensure that an external power supply circuit can supply power to each module of the embedded memory chip according to a preset power-on time sequence, uniformly and effectively manages the power-on of each module of the embedded memory chip, effectively reduces the granules of a power supply grid at the moment when each module is powered on simultaneously, and ensures the stability and safety of power utilization.

In order to ensure that the embedded memory chip can be normally identified by the soar processor, please refer to fig. 8, the method further includes: carrying out recognition test operation on the embedded memory chip after the independent research and development is finished in advance, specifically as follows;

step S400, sending a first test differential signal to the Feiteng processor through the at least one group of first differential signal sending and receiving pin pairs;

step S402 of generating a second test differential signal based on the first test differential signal through at least one set of second differential signal transmit receive pin pairs corresponding to the at least one set of first differential signal transmit receive pin pairs;

step S404, when a second test differential signal returned by the Feiteng processor is received, determining to establish a signal transmission channel with the Feiteng processor;

step S406, after the signal transmission channel is established, a plurality of voltages transmitted by the power supply circuit are received, and the voltage values of the voltages are inconsistent;

step S408, judging whether the plurality of voltages are received according to a preset power-on time sequence;

step S410, if the voltages are received according to the preset power-on sequence, determining to establish a connection with the soar processor, so that the soar processor identifies the embedded memory chip.

In an exemplary embodiment, if a second test differential signal returned by at least one second differential signal transmitting and receiving pin pair corresponding to the at least one first differential signal transmitting and receiving pin pair based on the first test differential signal is not received within a preset time, it is determined that the signal transmission connection with the soar processor fails, that is, the embedded memory chip cannot be identified by the soar processor, and it is determined that the embedded memory chip enters a rework state, so as to reconfigure the embedded memory chip.

If the voltages are not received according to the preset power-on sequence, determining that the connection between the embedded memory chip and the Feiteng processor fails, namely the embedded memory chip cannot be normally powered on, so that the embedded memory chip cannot be identified by the Feiteng processor, and determining that the embedded memory chip enters a reworking state to reconfigure the embedded memory chip.

Illustratively, the power supply circuit includes a first power supply circuit and a second power supply circuit, the first power supply circuit is configured to transmit the first voltage to the control module, transmit the second voltage to the input/output interface module, and transmit the fourth voltage to the flash memory module, and the second power supply circuit is configured to transmit the third voltage to the cache module; referring to fig. 9-1 and 9-2, fig. 9-1 schematically shows a power supply principle diagram of the first power supply circuit, and fig. 9-2 schematically shows a power supply principle diagram of the second power supply circuit. The method comprises the following specific steps:

as shown in fig. 9-1, the first power supply circuit:

the first power supply circuit comprises a first power supply chip, wherein the first power supply chip comprises a plurality of groups of first power input interfaces, such as two groups of VIN1, two groups of VIN2, two groups of VIN3 and VIN, and the plurality of groups of first power input interfaces are connected with an external power supply. Illustratively, two groups of VIN1, two groups of VIN2, two groups of VIN3 and VIN are connected in parallel through conducting wires and are connected with an external power supply VCCIN. Two groups of VIN1, two groups of VIN2, two groups of VIN3 and VIN are connected with one capacitor and then grounded.

The first power supply chip further comprises a first output interface VOUT3 and a second output interface, and the second output interface comprises a second main output interface VOUT1 and a second I/O output interface VOUT 2; the first power supply circuit comprises a first inductor L6 for voltage stabilization, a second inductor L3 for voltage stabilization, a first capacitor C31 for coupling, a second capacitor C41 for coupling and a third capacitor C30 for coupling;

one end of the first inductor L6 is connected to a first inductor connection port LX3 of the first power supply chip, the other end of the first inductor L6 is connected to the input terminal VCCK of the control module and the first output interface VOUT3, the first output interface VOUT3 is connected to one end of the first capacitor C19, and the other end of the first capacitor 31 is grounded;

the second main output interface VOUT1 is connected to the first input terminal VCC3F of the flash memory, the second main output interface VOUT1 is connected to one end of the second capacitor C41, and the other end of the second capacitor C41 is grounded;

the second I/O output interface VOUT2 is connected to one end of a second inductor L3, one end of the second inductor L3 is further connected to a second input terminal VCCFQ of the flash memory, the other end of the second inductor L3 is connected to a second inductor connection port LX3 of the first power supply chip, the second I/O output interface VOUT2 is connected to one end of a third capacitor C19, and the other end of the third capacitor C19 is grounded.

As shown in fig. 9-2, the second power supply circuit:

the second power supply circuit comprises a second power supply chip, the second power supply chip comprises a second power supply input interface VIN, an enabling pin EN, a feedback pin FB and a conversion pin SW, the second power supply input interface VIN is connected with the external power supply VCCN, and an enabling pin QE is connected with a standby pin DEVSLP of the first power supply chip; the second power supply circuit comprises a voltage stabilizing circuit consisting of a fourth capacitor C22, a third inductor L4 and a resistor R17. One end of the fourth capacitor C22 is connected to the feedback pin FB, and the other end of the fourth capacitor C22 is connected to the third output terminal VCCDQ; one end of the third inductor L4 is connected to the switch pin SW, and the other end of the third inductor L4 is connected to the third output terminal VCCDQ; one end of the first resistor R17 is connected to the feedback pin FB, and the other end of the first resistor R17 is connected to the third output terminal VCCDQ. The connection end of the first resistor R17, the fourth capacitor C22 and the feedback pin FB is connected with a second resistor R18, and the other end of the second resistor R18 is grounded.

In order to ensure the normal operation of the embedded memory chip when the power supply circuit cannot supply power to the embedded memory chip or cannot supply power in time, in an exemplary embodiment, the first power supply circuit is connected with one or more first decoupling capacitors for energy storage, one or more second decoupling capacitors for energy storage, and one or more third decoupling capacitors for energy storage; one or more fourth decoupling capacitors for energy storage are connected to the second power supply circuit.

The method further comprises the following steps:

Through the first decoupling capacitor, the second decoupling capacitor, the third decoupling capacitor and the fourth decoupling capacitor, interference of other signals is avoided in the signal transmission process, and the first decoupling capacitor, the second decoupling capacitor, the third decoupling capacitor and the fourth decoupling capacitor have the function of buffering energy. When a high-frequency device works, under the influence of frequency, great inductance influence is generated, and therefore power supply of each module of the embedded memory chip is not timely or when a power supply circuit is disconnected with the embedded memory chip, power is timely supplied to each module of the embedded memory chip through the decoupling capacitor, and the embedded memory chip can normally run.

Example two

Referring to fig. 10, a flowchart of steps of a intelligent destruction method based on a FT processor according to a second embodiment of the present invention is shown, in which the FT processor is electrically connected to an embedded memory chip, and the embedded memory chip board is attached to the FT processor. It is to be understood that the flow charts in the embodiments of the present method are not intended to limit the order in which the steps are performed. The following is an exemplary description, in particular, as follows.

Step S500, a destroy signal is sent to the embedded memory chip through the Feiteng processor, and the destroy signal is used for indicating the embedded memory chip to erase the memory data stored in the embedded chip by the Feiteng processor.

In order to improve the shock resistance of the external memory chip, the embedded memory chip board is pasted on the Feiteng processor in the embodiment of the invention, and the board paste is in point-to-point connection, so that the occupied space for mounting the embedded memory chip board on the Feiteng processor is small.

Further, in order to reduce the risk of data leakage, the embodiment of the invention improves the embedded memory chip, and the intelligent destruction function starting control is carried out on the embedded memory chip through the destruction signal sent by the Feiteng processor.

Step S502, receiving the destruction signal through the embedded memory chip.

The execution main body for carrying out the destroying function is an embedded memory chip, the destroying signal is a low level signal, the embedded memory chip is set to receive the low level signal, and the intelligent destroying function is triggered when the duration time of the low level signal is one second. The intelligent destruction function described in this embodiment is to erase the storage data embedded in the memory chip without damaging the embedded memory chip.

Step S504, when the embedded memory chip receives the destruction signal transmitted by the Feiteng processor, the duration time of the destruction signal is monitored.

Step S506, determining whether the duration time meets a preset time through the embedded memory chip.

Step S508, if the embedded memory chip determines that the duration time meets the preset time, it is determined to enter an erase execution state, and the memory data is erased based on the erase execution state.

Step S510, determining whether the erasing operation is completed based on the embedded memory chip according to a preset determination condition.

Step S512, if the embedded memory chip determines that the erasing operation is completed, entering a standby state.

Illustratively, the method further comprises performing, by the embedded memory chip, the steps of:

when the processor is in the erasing execution state, if any control signal of the Feiteng processor or other processors is received, the processor enters a fault processing state from the erasing execution state; any one of the control signals is used for indicating the embedded memory chip to enter a corresponding task execution state. And generating an error signal responding to any one control signal, and returning the error signal to the Feiteng processor or other processors, wherein the error signal is used for indicating that the embedded memory chip fails to enter the corresponding task execution state. And after the error signal is sent, entering the erasing execution state from the fault processing state so as to continue the erasing operation.

and when the embedded memory chip is in the erasing execution state, if a power supply circulating signal is received, entering an erasing pause state from the erasing execution state, wherein the power supply circulating signal is used for indicating the embedded memory chip to execute power supply circulating operation. And executing power supply circulation operation according to the power supply circulation signal. And when the power supply cycle operation is completed, entering the erasing execution state from the erasing pause state so as to continue the erasing operation.

The above-mentioned serial numbers of the embodiments of the present invention are merely for description and do not represent the merits of the embodiments.

Through the above description of the embodiments, those skilled in the art will clearly understand that the method of the above embodiments can be implemented by software plus a necessary general hardware platform, and certainly can also be implemented by hardware, but in many cases, the former is a better implementation manner.

The above description is only a preferred embodiment of the present invention, and not intended to limit the scope of the present invention, and all modifications of equivalent structures and equivalent processes, which are made by using the contents of the present specification and the accompanying drawings, or directly or indirectly applied to other related technical fields, are included in the scope of the present invention.

Claims

1. An intelligent destruction method based on a Feiteng processor is applied to an embedded memory chip, the embedded memory chip is pasted on the Feiteng processor, the embedded memory chip is electrically connected with the Feiteng processor, and the method comprises the following steps:

judging whether the duration time meets a preset time or not;

2. The Feiteng processor-based smart destruction method according to claim 1, further comprising:

when the processor is in the erasing execution state, if any control signal of the Feiteng processor or other processors is received, the processor enters a fault processing state from the erasing execution state; any one of the control signals is used for indicating the embedded memory chip to enter a corresponding task execution state; and

3. The Feiteng processor-based smart destruction method according to claim 1, further comprising:

4. The intelligent destruction method based on the Feiteng processor according to claim 1, wherein the embedded memory chip comprises a plurality of groups of first differential signal sending and receiving pin pairs, and the plurality of groups of first differential signal sending and receiving pin pairs are in one-to-one correspondence with a plurality of groups of second differential signal sending and receiving pin pairs of the Feiteng processor;

the method further comprises the following steps:

5. The intelligent destruction method based on the Feiteng processor according to claim 1, wherein the embedded memory chip comprises a control module, a flash memory module, a cache module, and an input/output interface module.

6. The Feiteng processor-based intelligent destruction method according to claim 5, wherein the control module, the flash memory module, the cache module and the input/output interface module are encapsulated in the embedded memory chip by BGA technology.

7. The intelligent destruction method based on the Feiteng processor according to claim 6, wherein the embedded memory chip is connected to an external power source through an external power supply circuit, and the power supply circuit is used for supplying power to the embedded memory chip;

8. The intelligent destruction method based on a Feiteng processor according to claim 7, wherein the first voltage, the second voltage, the third voltage and the fourth voltage are voltages transmitted to the embedded memory chip by a voltage timing control circuit in the power supply circuit according to a preset power-on timing sequence.

9. The intelligent destruction method based on a Feiteng processor according to claim 8, wherein the power supply circuit comprises a first power supply circuit and a second power supply circuit, the first power supply circuit is configured to transmit the first voltage to the control module, the second voltage to the input/output interface module, and the fourth voltage to the flash memory module, and the second power supply circuit is configured to transmit the third voltage to the cache module;

the method further comprises the following steps:

10. An intelligent destroying method based on a Feiteng processor is characterized in that the Feiteng processor is electrically connected with an embedded memory chip, and an embedded memory chip board is attached to the Feiteng processor; the method comprises the following steps:

executing the following operations by the embedded memory chip:

receiving the destruction signal;

judging whether the duration time meets a preset time or not;