CN216388074U

CN216388074U - Storage mainboard based on godson processor

Info

Publication number: CN216388074U
Application number: CN202121936272.4U
Authority: CN
Inventors: 李修录; 尹善腾; 朱小聪; 吴健全
Original assignee: Axd Anxinda Memory Technology Co ltd
Current assignee: Axd Anxinda Memory Technology Co ltd
Priority date: 2021-08-17
Filing date: 2021-08-17
Publication date: 2022-04-26
Anticipated expiration: 2031-08-17
Also published as: WO2023020484A1

Abstract

The utility model provides a godson processor-based storage mainboard, which comprises: the Loongson processor; the bridge piece is connected with the Loongson processor through an HT3.0 interface; the embedded memory chip is pasted on the Loongson processor in a plate mode and connected with the bridge piece; the embedded memory chip comprises a controller, a flash memory and a cache, wherein the controller is connected with the flash memory and the cache; the embedded memory chip is used for storing the data to be processed transmitted by the Loongson processor. In the utility model, the embedded memory chip 3 has high integration degree by combining the embedded memory chip and the Loongson processor which are pasted on the Loongson processor, which is beneficial to fast data storage and improves data storage efficiency.

Description

Storage mainboard based on godson processor

Technical Field

The embodiment of the utility model relates to the technical field of chips, in particular to a storage mainboard based on a Loongson processor.

Background

With the development of information technology, the demand of large data storage in the information age is also increased. At present, the memory disk design of a Central Processing Unit (CPU) applied to most of computer products in China adopts a foreign CPU chip to combine with a foreign memory chip to realize data storage. Because the chip is provided with a back door, the foreign memory chip is applied to a domestic computer system, and the safety and the confidentiality of information are difficult to ensure. Therefore, a domestic CPU chip, such as a Loongson processor, is in force.

The storage disk of the existing Loongson processor is usually integrated with a PCIe transmission data differential pin pair for realizing data storage, but the number of the PCIe transmission data differential pin pairs integrated with the storage disk of the existing Loongson processor is limited, so that the storage disk of the existing Loongson processor cannot meet the requirements of mass storage and rapid storage of data in the information age.

SUMMERY OF THE UTILITY MODEL

In view of this, embodiments of the present invention provide a storage motherboard based on a Loongson processor, which is used to solve the problems of small storage disk storage capacity and low storage efficiency of an existing Loongson processor.

The embodiment of the utility model solves the technical problems through the following technical scheme:

the utility model also provides a storage mainboard based on the Loongson processor, which comprises:

the Loongson processor;

the bridge piece is connected with the Loongson processor through an HT3.0 interface; and

the embedded memory chip is pasted on the Loongson processor in a plate mode and connected with the bridge piece; the embedded memory chip comprises a controller, a flash memory and a cache, wherein the controller is connected with the flash memory and the cache; the embedded memory chip is used for storing the data to be processed transmitted by the Loongson processor.

Optionally, the embedded memory chip is provided with four sets of first PCIe transmission data differential pin pairs;

the bridge chip is provided with four groups of second PCIe transmission data differential pin pairs;

the four groups of second PCIe transmission data differential pin pairs respectively correspond to the four groups of first PCIe transmission data differential pin pairs one by one, and the four groups of second PCIe transmission data differential pin pairs are respectively in communication connection with the corresponding first PCIe transmission data differential pin pairs so as to realize signal transmission.

Optionally, the embedded memory chip further includes a bus controller, and the controller is connected to the bus controller;

the Flash memory comprises a Flash controller and a Flash memory chip array; the Flash controller is respectively connected with the Flash memory chip array and the bus controller;

the cache comprises a DRAM controller and a DDR3 DRAM memory array; the DRAM controller is respectively connected with the DDR3 DRAM memory array and the bus controller.

Optionally, the storage motherboard further includes a power supply circuit, where the power supply circuit includes a first power supply circuit connected to the first power supply chip and a second power supply circuit connected to the second power supply chip;

the first power supply chip comprises a plurality of groups of first power input interfaces, and the plurality of groups of first power input interfaces are connected with an external power supply;

the first power supply chip further comprises a first output interface and a second output interface, and the second output interface comprises a second main output interface and a second I/O output interface; the first power supply circuit comprises a first inductor for stabilizing voltage, a second inductor for stabilizing voltage, a first capacitor for coupling, a second capacitor for coupling and a third capacitor for coupling;

the first power supply chip is connected with one end of the first inductor, the other end of the first inductor is connected with the first output interface and the input end of the controller, the first output interface is connected with one end of the first capacitor, and the other end of the first capacitor is grounded;

the second main output interface is connected with the first input end of the flash memory, the second main output interface is connected with one end of the second capacitor, and the other end of the second capacitor is grounded;

the second I/O output interface is connected with one end of a second inductor, the other end of the second inductor is connected with the second input end of the flash memory and the second I/O output interface, the second I/O output interface is connected with one end of a third capacitor, and the other end of the third capacitor is grounded;

the second power supply chip comprises a second power supply input interface and an enable pin, and the second power supply input interface and the enable pin are connected with the external power supply; the second power supply circuit comprises a fourth capacitor for coupling;

the second power supply chip further comprises a third output interface, the third output interface is connected with the input end of the cache, the third output interface is connected with one end of the fourth capacitor, and the other end of the fourth capacitor is grounded.

Optionally, one or more first decoupling capacitors for energy storage and one or more second decoupling capacitors for energy storage are connected to the first power supply circuit; one or more third decoupling capacitors for energy storage are connected to the second power supply circuit.

Optionally, the controller, the flash memory, and the cache are packaged in the embedded memory chip by BGA technology.

According to the storage mainboard based on the Loongson processor, provided by the embodiment of the utility model, the embedded storage chip board is attached to the Loongson processor, and the embedded storage chip is arranged on the Loongson processor, so that the occupied space is small and the shock resistance is good; the embedded memory chip has high integration degree, and the data storage capacity is increased by combining the Loongson processor with the embedded memory chip, the data storage efficiency is improved, and the requirements of the information era on the large-capacity storage and the rapid storage of data can be met.

The utility model is described in detail below with reference to the drawings and specific examples, but the utility model is not limited thereto.

Drawings

FIG. 1 is a schematic diagram illustrating an environment application of a storage motherboard based on a Loongson processor according to an embodiment of the present application;

FIG. 2 is a schematic diagram of an overall structure of a Loongson processor-based storage motherboard according to an embodiment of the present invention;

fig. 2-1 is a schematic structural diagram of the embedded memory chip in the memory motherboard based on a Loongson processor according to an embodiment of the present invention;

FIG. 3 is a circuit diagram of a first power supply circuit in a memory motherboard based on a Loongson processor according to an embodiment of the present invention;

FIG. 4 is a circuit diagram of a second power supply circuit in a memory motherboard based on a Loongson processor according to an embodiment of the present invention;

FIG. 5 is a schematic circuit diagram illustrating one or more first decoupling capacitors in a Loongson processor-based memory motherboard according to an embodiment of the present invention;

FIG. 6 is a schematic circuit diagram illustrating one or more second decoupling capacitors in a Loongson processor-based memory motherboard according to an embodiment of the present invention;

FIG. 7 is a schematic circuit diagram illustrating one or more second decoupling capacitors in a Loongson processor-based memory motherboard according to an embodiment of the present invention;

fig. 8 is a schematic circuit diagram illustrating one or more third decoupling capacitors in a memory motherboard of a Loongson processor according to an embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the utility model and are not intended to limit the utility model. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

It should be noted that the descriptions relating to "first", "second", etc. in the embodiments of the present invention are only for descriptive purposes and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In addition, technical solutions between various embodiments may be combined with each other, but must be realized by a person skilled in the art, and when the technical solutions are contradictory or cannot be realized, such a combination should not be considered to exist, and is not within the protection scope of the present invention.

In the description of the present invention, it should be understood that the numerical references before the steps do not identify the order of performing the steps, but merely serve to facilitate the description of the present invention and to distinguish each step, and thus should not be construed as limiting the present invention.

Interpretation of terms:

a Loongson processor: also known as a Loongson platform, the Loongson processor may be a Loongson 3A4000 chip. The Loongson processor is formed by integrating a plurality of 64-bit four-emission high-performance Loongson IP cores in a Loongson No. 3 high-performance 64-bit multi-core processor chip. The series of chips are applied to desktops, servers, Digital Signal Processors (DSPs), high-end embedded computers and the like, and due to the characteristic of low power consumption, part of the chips can also be applied to equipment of high-performance reinforced computers and the like. Is one of the national produced CPUs (Central Processing units/processors) in China.

Bridge piece: can be 7A1000 pieces of dragon core. The Loongson 7A1000 bridge chip is a matching bridge chip of a Loongson No. 3 serial processor facing the field of servers and desktops. The main peripheral interfaces of the bridge chip comprise 3 x8 PCIe 2.0 interfaces, 2 x4 PCIe 2.0 interfaces, three paths of SATA2.0, six paths of USB2.0, two paths of GMAC, two paths of DVO and other various small interfaces.

An embedded memory chip: in the application, the embedded memory chip may be a self-developed AXD PCIe NVMe BGA SSD embedded memory chip; the BGA packaging embedded memory chip is a self-developed BGA packaging embedded memory chip integrating a NAND flash memory, a DRAM cache and an autonomous research and development controller.

The applicant of the present invention has learned that: the storage disks of domestic chip platforms such as Loongson processors are all standard solid state disks, for example: the solid state disk of the mSATA (mini-SATA, mini SATA interface, which is a kind of computer bus) and the solid state disk of the 7+15PIN (chip) interface have at least the following defects:

(1) the solid state disk of the existing Loongson processor occupies a large space and has poor shock resistance.

(2) The existing godson processor's solid state disk usually employs SATA protocol (Serial Advanced Technology Attachment, a protocol used when signals are transmitted through an industry standard-based Serial hardware driver interface) or USB protocol (Universal Serial Bus, a protocol used when signals are transmitted through a Universal Serial Bus) to perform data transmission, and the upper limit of speed is not high, and cannot meet the requirement for processing big data in the information era.

(3) The solid state disk of the existing Loongson processor has poor integration degree.

To address the above issues, various embodiments are provided below, which may be used to implement Loongson processor-based data storage.

Fig. 1 schematically shows an environment application diagram of a data storage method based on a Loongson processor according to an embodiment of the present application. In an exemplary embodiment, the environment application schematic includes a Loongson processor 10, a bridge 20, and an embedded memory chip 30; the Loongson processor 10 is connected with the bridge chip 20, the bridge chip 20 is connected with the embedded memory chip through a first PCIe differential pin pair for transmitting data, and the Loongson processor 10 is connected with the embedded memory chip 30 through the bridge chip 20; the embedded memory chip 30 is integrated with a flash memory, a cache and a controller.

The utility model aims to provide a data storage mainboard based on a Loongson processor, and the key points of the utility model are as follows:

(1) the AXD PCIe NVMe embedded storage chip board which is researched and developed is attached to the Loongson processor, so that the effects of small occupied space and good shock resistance are achieved.

(2) The self-developed data transmission protocol for data transmission between the AXD PCIe NVMe embedded memory chip and the Loongson processor is PCIe3.0X4, the bandwidth is 8GB/s, the upper limit of the speed is high, and the requirement for large data processing in the information era can be met.

(3) The self-developed AXD PCIe NVM (advanced peripheral component interconnect express) embedded memory chip is a BGA (ball grid array) packaged embedded memory chip integrating a NAND Flash memory, a DRAM (dynamic random access memory) cache and a self-developed controller, is matched with a Loongson processor to realize a nationwide production platform, and is used for manufacturing a chain from a domestic CPU (central processing unit) to a domestic storage medium.

One or more embodiments are provided below to more particularly describe a Loongson processor-based data storage scheme.

Referring to fig. 2, an overall structural diagram of a storage motherboard 1 based on a Loongson processor according to an embodiment of the present invention is schematically shown.

As shown in fig. 2, the Loongson processor-based storage motherboard 1 includes: the smart card comprises a Loongson processor 10, a bridge chip 20 and an embedded memory chip 30, wherein the Loongson processor is used for transmitting a memory signal, and the memory signal is a signal based on a PCIe3.0X4 data transmission protocol; the bridge chip 20 can be connected with the Loongson processor 10 through an HT3.0 interface; the embedded memory chip 30 is attached to the Loongson processor 10, and the embedded memory chip 30 is connected with the bridge piece 20; the embedded memory chip 30 comprises a controller 4, a flash memory and a cache, wherein the controller 4 is connected with the flash memory and the cache; the embedded memory chip 30 is used for storing the data to be processed transmitted by the Loongson processor 10. The Loongson processor 10 is a Loongson 3A4000 chip. The bridge piece 20 can be a dragon core 7A1000 bridge piece. The embedded memory chip 30 may be a self-developed AXD PCIe NVMe BGA SSD embedded memory chip. The Flash memory may be a NAND Flash memory 5. The cache may be a DRAM cache 6(Dynamic Random Access Memory).

In the present invention, since the board pastes are connected point-to-point, the embedded memory chip 30 is mounted on the Loongson processor 10 in a small space, and the shock resistance of the embedded memory chip 30 on the Loongson processor 10 is effectively improved. The embedded memory chip 30 has high integration degree; the interface variety of storage mainboard 1 is abundant, can satisfy the multiple user demand of user to the storage product.

In order to ensure that normal signal transmission can be realized between the embedded memory chip 30 and the Loongson processor 10, in an exemplary embodiment, the embedded memory chip 30 is provided with four sets of first PCIe differential pin pairs for transmitting data; the bridge chip 20 is provided with four groups of second PCIe differential pin pairs for transmitting data; the four groups of second PCIe transmission data differential pin pairs respectively correspond to the four groups of first PCIe transmission data differential pin pairs one by one, and the four groups of second PCIe transmission data differential pin pairs are respectively in communication connection with the corresponding first PCIe transmission data differential pin pairs so as to realize signal transmission. In this implementation, the correspondence relationship between the four sets of first PCIe transmission data differential pin pairs and the four sets of second PCIe transmission data differential pin pairs follows a principle that RX and TX correspond to each other one to one, where RX represents receiving a differential signal, TX represents sending a differential signal, P represents a positive pole, and N represents a negative pole.

In order to realize the signal transmission among the modules in the embedded memory chip 30, the embedded memory chip 30 further comprises a bus controller, and the controller 4 is connected with the bus controller; the Flash memory comprises a Flash controller and a Flash memory chip array; the Flash controller is respectively connected with the Flash memory chip array and the bus controller; the cache comprises a DRAM controller and a DDR3 DRAM memory array; the DRAM controller is respectively connected with the DDR3 DRAM memory array and the bus controller. In this embodiment, the controller 4 controls the flash memory and the cache memory to realize the data storage function of the embedded memory chip 30.

With reference to fig. 2-1, a schematic structural diagram of the embedded memory chip 30 is shown. The embedded memory chip 30 realizes signal transmission between each module therein through a PCIe bus and realizes signal transmission between the embedded memory chip 30 and an external processor (such as the Loongson processor 10) through a PCIe port. The PCIe bus includes a PCIe physical layer, which is a bottom layer of the PCIe bus, and the PCIe physical layer further includes a PCIe MAC (Media Access Control) layer. In the utility model, the core related to the PCIe MAC layer is the PCIe NVMe standard (which is a solid state disk industry standard based on the PCIe protocol).

The embedded Memory chip 30 includes a bus controller, a dual-core CPU (i.e., controller 4), an RAID codec, a Flash controller, a Flash Memory chip array, a security engine, a main system buffer, a DMA controller, a DRAM controller, and a DDR3 DRAM (a cache product of a computer Memory specification), where the bus controller is connected to the dual-core CPU, the RAID codec (a disk array codec ), the Flash controller, the security engine, the main system buffer, and the DMA controller (Direct Memory Access, a controller that allows communication between hardware devices with different speeds) and the DRAM controller, the Flash controller is connected to the Flash Memory chip array, and the DRAM controller is connected to the DDR3 DRAM.

In an exemplary embodiment, the controller, the flash memory, and the cache are packaged in the embedded memory chip by BGA technology. The bga (ball Grid array) packaging technology is a ball Grid array packaging technology, which is a high-density surface mount packaging technology. The embedded memory chip adopting the BGA packaging technology has smaller volume, faster and more effective heat radiation performance and electrical performance under the same capacity.

In order to realize the power supply of the embedded memory chip 30; in an exemplary embodiment, the storage motherboard 1 further includes a power supply circuit including a first power supply circuit connected to the first power supply chip and a second power supply circuit connected to the second power supply chip;

the first power supply chip is connected with one end of the first inductor, the other end of the first inductor is connected with the first output interface and the input end of the controller 4, the first output interface is connected with one end of the first capacitor, and the other end of the first capacitor is grounded;

For better control of the preset power-up sequence, please refer to fig. 3 and 4, in which fig. 3 schematically shows a power supply circuit diagram of the first power supply circuit, and fig. 4 schematically shows a second power supply circuit diagram. The method comprises the following specific steps:

as shown in fig. 3, the first power supply circuit:

the first power supply circuit comprises a first power supply chip, wherein the first power supply chip comprises a plurality of groups of first power input interfaces, such as two groups of VIN1, two groups of VIN2, two groups of VIN3 and VIN, and the plurality of groups of first power input interfaces are connected with an external power supply H33V. Illustratively, two groups of VIN1, two groups of VIN2, two groups of VIN3 and VIN are connected in parallel through conducting wires and are connected with an external power supply H33V. Two groups of VIN1, two groups of VIN2, two groups of VIN3 and VIN are connected with one capacitor and then grounded.

The first power supply chip further comprises a first output interface VOUT3 (such as a pin G1) and a second output interface, wherein the second output interface comprises a second main output interface VOUT1 (such as pins D5 and D6) and a second I/O output interface VOUT2 (such as a pin E6); the first power supply circuit comprises a first inductor L3 for elegant, a second inductor L2 for voltage stabilization, a first capacitor C19 for coupling, a second capacitor C10 for coupling and a third capacitor C16 for coupling.

The first power supply circuit further includes a first inductor connection interface LX3 (e.g., pins F3 and G3), the first inductor connection interface LX3 is connected to one end of the first inductor L3, the other end of the first inductor L3 is connected to the first output interface VOUT3 and the input terminal VCCK of the controller 4 (e.g., pins G7, G8, G11, G12, H7, H8, H11, H12, J7, J8, J11 and J12), the first output interface VOUT3 is connected to one end of the first capacitor C19, and the other end of the first capacitor C19 is grounded.

The second main output interface VOUT1 is connected to a first input terminal VCC3F (e.g., pins D10, E9, E10, W9, W10, Y9, Y10) of the flash memory, the second main output interface VOUT1 is connected to one end of the second capacitor C10, and the other end of the second capacitor C10 is grounded.

The first power supply circuit further includes a second inductor connection interface LX2 (e.g., pins F5 and F6), the second inductor connection interface LX2 is connected to one end of the second inductor L2, the other end of the second inductor L2 is connected to the second I/O output interface VOUT2 and the second input VCCFQ of the flash memory (e.g., pins R8, R11, R12, T7, T8, T11, T12, U7, U8, U11, U12), the second I/O output interface VOUT2 is connected to one end of the third capacitor C16, and the other end of the third capacitor C16 is grounded.

The first power supply circuit further includes a first ground interface PGND1 (e.g., pins a5, a6), a second ground interface PGND2 (e.g., pin E5), a third ground interface PGND3 (e.g., pins F4, G4), and a fourth ground interface AGND (e.g., pin C1).

As shown in fig. 4, the second power supply circuit:

the second power supply circuit comprises a second power supply chip, the second power supply chip comprises a second power input interface VIN and an enable pin EN, and the second power input interface VIN and the enable pin EN are connected with the external power supply H33V; the second power supply circuit comprises a fourth capacitor C23 for coupling;

the second power supply chip further comprises a third output interface VOUT, the third output interface VOUT is connected to the input terminal V18 (for example, a pin R7) of the buffer, the third output interface VOUT is connected to one end of the fourth capacitor, and the other end of the fourth capacitor is grounded. The second power supply chip further includes ground terminals, such as GND and SGND.

In order to ensure the normal operation of the embedded memory chip 30 when the power supply circuit cannot supply power to the embedded memory chip 30 or cannot supply power in time, as shown in fig. 5 to 8, the first power supply circuit is connected with one or more first decoupling capacitors for energy storage and one or more second decoupling capacitors for energy storage; one or more third decoupling capacitors for energy storage are connected to the second power supply circuit. Through the first decoupling capacitor, the second decoupling capacitor and the third decoupling capacitor, interference of other signals is avoided in the signal transmission process, and the first decoupling capacitor, the second decoupling capacitor and the third decoupling capacitor have the function of buffering energy. When the high-frequency device works, under the influence of frequency, a large inductance influence is generated, and therefore when power supply of each module of the embedded memory chip 30 is not timely or a power supply circuit is disconnected with the embedded memory chip 30, each module of the embedded memory chip 30 is timely powered through the decoupling capacitor, and the embedded memory chip 30 can normally run.

As shown in fig. 5, the first decoupling capacitor includes a capacitor C6542, a capacitor BC46, a capacitor BC47, and a capacitor BC49, wherein one end of the capacitor C6542 is connected to the input terminal VCCK of the controller 4, one end of the capacitor C6542 is connected to one end of the capacitor BC46, the other end of the capacitor C6542 is connected to the other end of the capacitor BC46, and the other end of the capacitor C6542 is grounded; one end of the capacitor BC46 is connected with one end of the capacitor BC47, and the other end of the capacitor BC46 is connected with the other end of the capacitor BC 47; one end of the capacitor BC47 is connected to one end of the capacitor BC49, and the other end of the capacitor BC47 is connected to the other end of the capacitor BC 49.

As shown in fig. 6, the second decoupling capacitor includes a capacitor C6537, a capacitor BC48, a capacitor BC35, and a capacitor BC40, wherein one end of the capacitor C6537 is connected to the first input terminal VCC3F of the flash memory, one end of the capacitor C6537 is connected to one end of the capacitor BC48, the other end of the capacitor C6537 is connected to the other end of the capacitor BC48, and the other end of the capacitor C6537 is grounded; one end of the capacitor BC48 is connected with one end of the capacitor BC35, and the other end of the capacitor BC48 is connected with the other end of the capacitor BC 35; one end of the capacitor BC35 is connected to one end of the capacitor BC40, and the other end of the capacitor BC35 is connected to the other end of the capacitor BC 40.

As shown in fig. 7, the second decoupling capacitor further includes a capacitor C6541, a capacitor BC51, a capacitor BC38, a capacitor BC52 and a capacitor BC55, wherein one end of the capacitor C6541 is connected to the second input VCCFQ of the flash memory, one end of the capacitor C6541 is connected to one end of the capacitor BC51, the other end of the capacitor C6541 is connected to the other end of the capacitor BC51, and the other end of the capacitor C6541 is grounded; one end of the capacitor BC51 is connected with one end of the capacitor BC38, and the other end of the capacitor BC51 is connected with the other end of the capacitor BC 38; one end of the capacitor BC38 is connected with one end of the capacitor BC52, and the other end of the capacitor BC38 is connected with the other end of the capacitor BC 52; one end of the capacitor BC52 is connected to one end of the capacitor BC55, and the other end of the capacitor BC52 is connected to the other end of the capacitor BC 55.

As shown in fig. 8, the third decoupling capacitor further includes a capacitor C6538 and a capacitor BC45, wherein one end of the capacitor C6538 is connected to the input terminal V18 of the buffer, one end of the capacitor C6538 is connected to one end of the capacitor BC45, the other end of the capacitor C6538 is connected to the other end of the capacitor BC45, and the other end of the capacitor C6538 is grounded.

The embodiment of the utility model at least has the following beneficial effects:

(1) the embedded storage chip direct connection board is pasted on the dragon core processor, and compared with a storage solid state disk with a golden finger, the embedded storage chip direct connection board occupies a small space and has good anti-seismic performance.

(2) The data transmission protocol of the embedded memory chip is PCIe3.0X4 protocol, the bandwidth can reach 8GB/s, the upper limit of the speed is high, and the requirement of the current information era on rapid data storage can be met.

(3) The embedded memory chip is a BGA packaged embedded memory chip which integrates a NAND Flash memory, a DRAM cache and an autonomous research and development controller, is matched with a Loongson processor to realize a nationwide production platform, and is beneficial to promoting the development of domestic CPUs (central processing units) to domestic storage media.

The above-mentioned serial numbers of the embodiments of the present invention are merely for description and do not represent the merits of the embodiments.

Through the above description of the embodiments, those skilled in the art will clearly understand that the method of the above embodiments can be implemented by software plus a necessary general hardware platform, and certainly can also be implemented by hardware, but in many cases, the former is a better implementation manner.

The above description is only a preferred embodiment of the present invention, and not intended to limit the scope of the present invention, and all modifications of equivalent structures and equivalent processes, which are made by using the contents of the present specification and the accompanying drawings, or directly or indirectly applied to other related technical fields, are included in the scope of the present invention.

Claims

1. A godson processor-based storage motherboard, comprising:

the Loongson processor;

2. The Loongson processor-based memory motherboard of claim 1, wherein the embedded memory chip is provided with four sets of first PCIe differential pin pairs for transmitting data;

the four groups of second PCIe transmission data differential pin pairs correspond to the four groups of first PCIe transmission data differential pin pairs one by one, and the four groups of second PCIe transmission data differential pin pairs are respectively in communication connection with the corresponding first PCIe transmission data differential pin pairs so as to realize signal transmission.

3. The Loongson processor-based storage motherboard of claim 1, wherein said embedded memory chip further comprises a bus controller, said controller being connected to said bus controller;

4. The Loongson processor-based storage motherboard of claim 1, further comprising a power supply circuit, the power supply circuit comprising a first power supply circuit connected to the first power supply chip and a second power supply circuit connected to the second power supply chip;

5. The Loongson processor-based storage motherboard of claim 4, wherein the first power supply circuit is connected with one or more first decoupling capacitors for energy storage and one or more second decoupling capacitors for energy storage; one or more third decoupling capacitors for energy storage are connected to the second power supply circuit.

6. The Loongson processor-based storage motherboard of claim 1, wherein the controller, the flash memory and the cache are encapsulated within the embedded storage chip by BGA technology.