CN212433755U - Modular small-size and multi-type data interface processing device - Google Patents
Modular small-size and multi-type data interface processing device Download PDFInfo
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- CN212433755U CN212433755U CN202021366424.7U CN202021366424U CN212433755U CN 212433755 U CN212433755 U CN 212433755U CN 202021366424 U CN202021366424 U CN 202021366424U CN 212433755 U CN212433755 U CN 212433755U
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Abstract
The utility model provides a modularization small size, polymorphic type data interface processing apparatus through the data processor who chooses for use small size, high performance, low-power consumption, provides powerful data reception and throughput to through the logic chip who uses small size, polymorphic type interface, realize the various low-speed/high-speed data interface of seamless adaptation.
Description
Technical Field
The utility model belongs to computer information processing field, specifically speaking relates to a small volume of modularization, polymorphic type data interface processing apparatus.
Background
In the process of information processing of industrial and military computer systems, the source of interface data includes, but is not limited to, embedded computer systems, various encoding and decoding devices, control devices, etc., some of these devices use standard industry interfaces, but with the introduction of new technology and new interfaces, the computer system is also required to be capable of performing compatible processing on them, i.e., the computer system has the capability of performing extended processing on various types of interface data.
The data interface processing device is widely applied to various electronic engineering fields needing to process real-time data, such as various airborne, shipborne and vehicle-mounted electronic engineering fields, has the requirements of wide and applicable data input interfaces, small installation volume, convenience in loading and unloading and higher performance, meets the application requirements in various scenes, and has higher performance and more interfaces in part of occasions to meet the information input and processing requirements of high speed and large data volume.
The existing data interface processing device is usually installed in various connector types, and the device is fixed by means of screws and structural members; in order to reduce power consumption and volume, an embedded processor with low power consumption, small volume and relatively simple peripheral interface and circuit is often selected as an existing data interface processing device, and a special interface form is selected according to different applications. In the situation that the requirement for processing the data volume is low, the data interface processing device selects a conventional RS232/RS422 industrial interface for processing a small amount of important data (usually a plurality of KB/S); under the condition of relatively large requirement on data processing quantity, a data interface processing device usually adopts a special PCIE/network interface, the speed can reach dozens of MB/S capacity, and the requirement on interface data processing in some occasions can be met. However, even if the above method is adopted, the existing data interface processing device still has inflexible interface type adaptation and cannot process the input and output of high-transmission-rate data; although the interface throughput rate is improved compared with the traditional data interface processing device, the processing device still cannot meet the processing requirements of small volume, multiple types of interfaces and large data volume caused by the fact that the current information technology is developed more and more quickly; the conventional data interface processing usually selects an asynchronous serial interface for data transmission, and when the data interface rate is low, the asynchronous serial interface is used for data transmission, which is a convenient and concise solution, but when the data interface rate is high, the conventional PCIE/network interface cannot flexibly and seamlessly adapt to a new technical interface.
SUMMERY OF THE UTILITY MODEL
The utility model discloses to prior art bulky, the inflexible adaptation of interface type, the inconvenient succinct scheduling problem of operation, provided a modularization small size, polymorphic type data interface processing apparatus, through the data processor who chooses for use small size, high performance, low-power consumption, provide powerful data reception and throughput to through the logic chip who uses small size, polymorphic type interface, realize the various low-speed/high-speed data interface of seamless adaptation.
The utility model provides a modular small-volume and multi-type data interface processing device, which comprises a Bridge module, a CPU module and an FPGA module;
the Bridge module is respectively connected with the conventional data interface, the display interface, the state interface and the CPU module;
the CPU module is connected with the FPGA module and the RS232 interface;
the FPGA module is connected with the flexible adaptive data interface;
the conventional data interface comprises a PCIE interface, a LAN interface, a USB interface, a SATA interface and an RS422 interface;
the display interface comprises a VGA interface and a DVI interface;
the status interface comprises a 12C interface;
the flexible adaptive data interface comprises a GTX interface, an LVDS interface and an LVTLL interface.
To better implement the present invention, further, the Bridge module comprises a Bridge dragon core 7a10000 chip; the LAN interface comprises an Ethernet PHY Marvell88E1111 chip, the Bridge Loongson 7A10000 chip is connected with the Ethernet PHY Marvell88E1111 chip through GMAC0 and GMAC1, and the Ethernet PHY Marvell88E1111 chip is connected with an external interface P1 through LAN;
the display interface comprises a DM7150 GMG7123 chip, the Bridge Loongson 7A10000 chip is connected with the DM7150 GMG7123 chip through DCO0 and DVO1, and the DM7150 GMG7123 chip is connected with an external interface P2 through a VGA interface and a DVI interface;
the RS422 interface comprises an RS422 SM3490 chip, the Bridge Loongson 7A10000 chip is connected with an RS422 SM3490 chip through a UART1, and the RS422 SM3490 chip is connected with an external interface P2 through a longson RS 422;
and the PCIE interface, the SATA interface and the USB interface are all connected with an external interface P1.
In order to better implement the present invention, further, the Bridge module further includes a SATA SSD HTUSMU064G chip, a DDR3SM41J256M16M chip, and a first FLASH GD25Q512M chip;
the SATA SSD HTUSMU064G chip is connected with the Bridge Loongson 7A10000 chip through SATA 0;
the DDR3SM41J256M16M chip and the Bridge Loongson 7A10000 chip are in access connection with 16 bits;
the FLASH GD25Q512M chip is connected with the Bridge Loongson 7A10000 chip through an SPI _ CS 0.
In order to better realize the utility model, further, the CPU module comprises a Loongson 3a3000 chip, the RS232 interface comprises a RS232 GMH3232 chip, the Loongson 3a3000 chip is connected with the RS232 GMH3232 chip through UART0 and UART1, the RS232 GMH3232 chip is connected with an external interface P2 through longson RA232 and longson RA232(DB) interfaces;
the Loongson 3A3000 chip and the Bridge Loongson 7A10000 chip are in data interaction connection through a high-speed HT bus.
In order to better realize the utility model, further, the chip further comprises eight DDR3SM41J256M16M chips, a second FLASH GD25Q512M chip; the eight DDR3SM41J256M16M chips are in access connection with the Loongson 3A3000 chip by 64 bits; the second FLASH GD25Q512M chip is connected with the Loongson 3A3000 chip through an SPI _ CS 0.
In order to better implement the present invention, further, the FPGA module includes an FPGA JFM7K325T chip; the FPGA JFM7K325T chip is connected with an external interface P2 through a GTX interface, a GPIO interface and an LVDS interface;
the FPGA JFM7K325T chip is connected with an external interface P0 through a SYSRESET interface and a REF _ CLK interface;
the FPGA JFM7K325T chip is connected with the Bridge Loongson 7A10000 chip through UART2, UART3, SPI _ CS1, LPC, PWM, PCIE and GPIO.
In order to better implement the present invention, further, the FPGA module further includes a configuration chip GD25Q512M, and the configuration chip GD25Q512M is connected to the FPGA JFM7K325T chip through the SPI.
In order to better realize the utility model, the utility model further comprises a monitoring interaction module, wherein the monitoring interaction module comprises a power supply unit and a monitoring interaction unit;
the power supply unit is connected with the monitoring interaction unit, the FPGA JFM7K325T chip, the Loongson 3A3000 chip and the Bridge Loongson 7A10000 chip;
and the monitoring interaction unit is in data connection with a Bridge Loongson 3A3000 chip and an FPGA JFM7K325T chip.
In order to better realize the utility model, further, the power supply unit comprises an XC388QDC chip and a plurality of DC-DC LYM4644 chips, the input end of the XC388QDC chip is connected with 3.3V and 12V direct current power supplies and outputs 12V direct current power supplies to the plurality of DC-DC LYM4644 chips, and the DC-DC LYM4644 chips are connected with a monitoring interaction unit, an FPGA JFM7K325T chip, a loongson 3a3000 chip and a Bridge loongson 7a10000 chip;
the monitoring interaction unit comprises a temperature sensor LC423 and an MCU GD32F103CBT6 chip, and the temperature sensor LC423 is connected with the MCU GD32F103CBT6 chip through an SPI;
the MCU GD32F103CBT6 chip is connected with the DC-DC LYM4644 chip through power-on control, and the DC-DC LYM4644 chip is in data interactive connection with the FPGA JFM7K325T chip and the Loongson 3A3000 chip through UART interfaces.
In order to better realize the utility model discloses, further, all be provided with JTAG test interface on FPGA JFM7K325T chip, the Loongson 3A3000 chip, MCU GD32F103CBT6 chip, the Bridge Loongson 7A10000 chip.
Compared with the prior art, the utility model have following advantage and beneficial effect:
(1) the defects of insufficient processing performance, insufficient interface type support and incapability of flexibly configuring a data transmission interface in the prior art are overcome;
(2) the data interface processing device has the advantages of providing richer interface types, smaller size and volume and lower controllable power consumption.
Drawings
FIG. 1 is a block diagram of the present invention;
FIG. 2 is a schematic diagram of the connection of the chip according to the present invention;
fig. 3 is a schematic diagram of the principle of the PCIE interface circuit of the present invention;
FIG. 4 is a schematic diagram of the GTX interface circuit of the present invention;
fig. 5 is a schematic diagram of the LVDS interface circuit of the present invention;
fig. 6 is a schematic diagram of the LVTTL interface circuit of the present invention;
FIG. 7 is a front view of the physical device of the present invention;
fig. 8 is a top view of the physical device of the present invention.
Detailed Description
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it should be understood that the described embodiments are only some embodiments of the present invention, but not all embodiments, and therefore should not be considered as limitations to the scope of protection. Based on the embodiments in the present invention, all other embodiments obtained by the staff of ordinary skill in the art without creative work belong to the protection scope of the present invention.
In the description of the present invention, it is to be noted that, unless otherwise explicitly specified or limited, the terms "disposed," "connected," and "connected" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the present invention can be understood in specific cases to those skilled in the art.
Example 1:
the embodiment provides a modular small-volume multi-type data interface processing device, as shown in fig. 1, fig. 3, fig. 4, fig. 5, fig. 6, fig. 7, and fig. 8, which includes a Bridge module, a CPU module, an FPGA module, and a monitoring interaction module;
the Bridge module is respectively connected with the conventional data interface, the display interface, the state interface and the CPU module;
the CPU module is connected with the FPGA module and the RS232 interface;
the FPGA module is connected with the flexible adaptive data interface;
the conventional data interface comprises a PCIE interface, a LAN interface, a USB interface, a SATA interface and an RS422 interface;
the display interface comprises a VGA interface and a DVI interface;
the status interface comprises a 12C interface;
the flexible adaptive data interface comprises a GTX interface, an LVDS interface and an LVTLL interface;
the monitoring interaction module comprises a power supply unit and a monitoring interaction unit;
the power supply unit is connected with the monitoring interaction unit, the FPGA JFM7K325T chip, the Loongson 3A3000 chip and the Bridge Loongson 7A10000 chip;
and the monitoring interaction unit is in data connection with a Bridge Loongson 3A3000 chip and an FPGA JFM7K325T chip. The device is shown in figures 7 and 8.
Example 2:
on the basis of the foregoing embodiment 1, in order to better implement the present invention, further, as shown in fig. 2, fig. 3, fig. 4, fig. 5, and fig. 6, the Bridge module includes a Bridge loongson 7a10000 chip, a SATA SSD HTUSMU064G chip, a DDR3SM41J256M16M chip, and a first FLASH GD25Q512M chip; the LAN interface comprises an Ethernet PHY Marvell88E1111 chip, the Bridge Loongson 7A10000 chip is connected with the Ethernet PHY Marvell88E1111 chip through GMAC0 and GMAC1, and the Ethernet PHY Marvell88E1111 chip is connected with an external interface P1 through LAN;
the display interface comprises a DM7150 GMG7123 chip, the Bridge Loongson 7A10000 chip is connected with the DM7150 GMG7123 chip through DCO0 and DVO1, and the DM7150 GMG7123 chip is connected with an external interface P2 through a VGA interface and a DVI interface;
the RS422 interface comprises an RS422 SM3490 chip, the Bridge Loongson 7A10000 chip is connected with an RS422 SM3490 chip through a UART1, and the RS422 SM3490 chip is connected with an external interface P2 through a longson RS 422;
the PCIE interface, the SATA interface and the USB interface are all connected with an external interface P1;
the SATA SSD HTUSMU064G chip is connected with the Bridge Loongson 7A10000 chip through SATA 0;
the DDR3SM41J256M16M chip and the Bridge Loongson 7A10000 chip are in access connection with 16 bits;
the FLASH GD25Q512M chip is connected with the Bridge Loongson 7A10000 chip through an SPI _ CS 0.
The CPU module comprises a Loongson 3A3000 chip, eight DDR3SM41J256M16M chips and a second FLASH GD25Q512M chip, the RS232 interface comprises an RS232 GMH3232 chip, the Loongson 3A3000 chip is connected with the RS232 GMH3232 chip through a UART0 and a UART1, and the RS232 GMH3232 chip is connected with an external interface P2 through longson RA232 and longson RA232(DB) interfaces;
the Loongson 3A3000 chip and the Bridge Loongson 7A10000 chip are in data interactive connection through a high-speed HT bus; the eight DDR3SM41J256M16M chips are in access connection with the Loongson 3A3000 chip by 64 bits; the second FLASH GD25Q512M chip is connected with the Loongson 3A3000 chip through an SPI _ CS 0.
The FPGA module comprises an FPGA JFM7K325T chip; the FPGA JFM7K325T chip is connected with an external interface P2 through a GTX interface, a GPIO interface and an LVDS interface;
the FPGA JFM7K325T chip is connected with an external interface P0 through a SYSRESET interface and a REF _ CLK interface;
the FPGA JFM7K325T chip is connected with the Bridge Loongson 7A10000 chip through UART2, UART3, SPI _ CS1, LPC, PWM, PCIE and GPIO.
The configuration chip GD25Q512M, the configuration chip GD25Q512M is connected with the FPGA JFM7K325T chip through the SPI.
The working principle is as follows: a high-speed data access interface and processing capacity are provided by an FPGA JFM7K325T chip which is provided with a high-performance Loongson 3A3000 chip and a multi-type interface. The Loongson 3A3000 chip processor used can guarantee low power consumption, provide the running frequency up to 1.2GHz and provide the data processing capability with high performance; as shown in fig. 2, the Loongson 3A3000 chip and the Loongson 7A1000 bridge chip perform data interaction through a high-speed HT bus; the Bridge Loongson 7A1000 chip and the FPGA logic chip carry out data interaction through a high-speed PCIE bus and a low-speed UART/SPI/LPC/GPIO interface; and provide 2 routes of asynchronous serial interfaces as the access interface of the low-speed data externally, the highest baud rate is 230400bps, the asynchronous serial interface meets the interface and applies the area extensively, can be suitable for many application scenes, have also provided the adaptive ability of the low-speed data interface;
designing and allocating a DDR memory chip with low power consumption and large capacity, providing a large-capacity data cache space, and providing a cache space with enough size for a processor for high-speed input data to be used as temporary storage of the data;
as shown in fig. 2, the apparatus designs a 1-way GTX x4 interface, a 1-way LVDS x4 interface and an 8-way lvdll interface, which are used as flexibly-extended high-speed transmission interfaces, and can be adapted to not only a general interface in a seamless manner, but also support new interface types in an adaptation manner as required, and support high-speed and low-speed and various protocol interfaces to be adapted by adjusting soft logic codes without changing hardware design, thereby greatly extending the application range of the interfaces;
meanwhile, in practical application, an operating system suitable for the hardware platform is tailored and customized for the modularized small-volume and multi-type data interface processing device, and the operating system provides strong multi-process and multi-task processing capability on the premise of ensuring small volume, and meets the processing and scheduling capability of multi-port large data during high-speed injection; a protocol stack based on an Ethernet/USB/PCIE/GTX/LVDS/LVTLL interface is provided, an interface software platform is provided for supporting, and interface driving and software functions during data transmission are finally realized;
the device designs 2 ways of 10M/100Mbps Ethernet interfaces, 1 way of PCIE x8 interfaces and 4 ways of USB interfaces, and is used as a high-speed transmission interface of conventional data, thereby not only ensuring the universality of the interface, but also providing the rapid transmission capability of the data under the condition that the device transmits a large amount of data, and greatly saving the time of data transmission.
Other parts of this embodiment are the same as those of embodiment 1, and thus are not described again.
Example 3:
the utility model discloses on the basis of any one of above-mentioned embodiment 1-2, in order to realize better the utility model discloses, as shown in fig. 2, further, power supply unit includes XC388QDC chip, a plurality of DC-DC LYM4644 chips, XC388QDC chip input is connected 3.3V and 12V direct current power supply, and output 12V direct current power to a plurality of DC-DC LYM4644 chips, DC-DC LYM4644 chip and control mutual unit, FPGA JFM7K325T chip, Loongson 3A3000 chip, Bri Loongson 7A10000 chip connection;
the monitoring interaction unit comprises a temperature sensor LC423 and an MCU GD32F103CBT6 chip, and the temperature sensor LC423 is connected with the MCU GD32F103CBT6 chip through an SPI;
the MCU GD32F103CBT6 chip is connected with the DC-DC LYM4644 chip through power-on control, and the DC-DC LYM4644 chip is in data interactive connection with the FPGA JFM7K325T chip and the Loongson 3A3000 chip through UART interfaces.
In order to better realize the utility model discloses, further, all be provided with JTAG test interface on FPGA JFM7K325T chip, the Loongson 3A3000 chip, MCU GD32F103CBT6 chip, the Bridge Loongson 7A10000 chip.
The working principle is as follows: as shown in fig. 2, a typical application of the device includes a signal output of a 1-way status indicator I2C connected to the MCU GD32F103CBT6 chip, which provides the current operating status of the module to the user, and provides a simple and clear status indication interface for the user to observe and know the current operating status of the device;
the MCU GD32F103CBT6 chip is mainly used for voltage monitoring and state information processing, and performs data interaction with the Loongson 3A3000 processor and the FPGA logic chip through a UART interface.
Other parts of this embodiment are the same as any of embodiments 1-2 described above, and thus are not described again.
The above is only the preferred embodiment of the present invention, not to the limitation of the present invention in any form, all the technical matters of the present invention all fall into the protection scope of the present invention to any simple modification and equivalent change of the above embodiments.
Claims (10)
1. A modular small-volume multi-type data interface processing device is characterized by comprising a Bridge module, a CPU module and an FPGA module;
the Bridge module is respectively connected with the conventional data interface, the display interface, the state interface and the CPU module;
the CPU module is connected with the FPGA module and the RS232 interface;
the FPGA module is connected with the flexible adaptive data interface;
the conventional data interface comprises a PCIE interface, a LAN interface, a USB interface, a SATA interface and an RS422 interface;
the display interface comprises a VGA interface and a DVI interface;
the status interface comprises a 12C interface;
the flexible adaptive data interface comprises a GTX interface, an LVDS interface and an LVTLL interface.
2. The modular small-volume, multi-type data interface processing device of claim 1, wherein said Bridge module comprises a Bridge Loongson 7A10000 chip; the LAN interface comprises an Ethernet PHY Marvell88E1111 chip, the Bridge Loongson 7A10000 chip is connected with the Ethernet PHY Marvell88E1111 chip through GMAC0 and GMAC1, and the Ethernet PHY Marvell88E1111 chip is connected with an external interface P1 through LAN;
the display interface comprises a DM7150 GMG7123 chip, the Bridge Loongson 7A10000 chip is connected with the DM7150 GMG7123 chip through DCO0 and DVO1, and the DM7150 GMG7123 chip is connected with an external interface P2 through a VGA interface and a DVI interface;
the RS422 interface comprises an RS422 SM3490 chip, the Bridge Loongson 7A10000 chip is connected with an RS422 SM3490 chip through a UART1, and the RS422 SM3490 chip is connected with an external interface P2 through a longson RS 422;
and the PCIE interface, the SATA interface and the USB interface are all connected with an external interface P1.
3. The modular small-volume, multi-type data interface processing device of claim 2, wherein said Bridge module further comprises a SATA SSD HTUSMU064G chip, a DDR3SM41J256M16M chip, a first FLASH GD25Q512M chip;
the SATA SSD HTUSMU064G chip is connected with the Bridge Loongson 7A10000 chip through SATA 0;
the DDR3SM41J256M16M chip and the Bridge Loongson 7A10000 chip are in access connection with 16 bits;
the FLASH GD25Q512M chip is connected with the Bridge Loongson 7A10000 chip through an SPI _ CS 0.
4. The modular small-sized, multi-type data interface processing unit according to claim 2, wherein the CPU module includes a Loongson 3a3000 chip, the RS232 interface includes a RS232 GMH3232 chip, the Loongson 3a3000 chip is connected with the RS232 GMH3232 chip through UART0 and UART1, the RS232 GMH3232 chip is connected with an external interface P2 through longson RA232 and longson RA232(DB) interfaces;
the Loongson 3A3000 chip and the Bridge Loongson 7A10000 chip are in data interaction connection through a high-speed HT bus.
5. The modular small-volume, multi-type data interface processing device of claim 4, further comprising eight DDR3SM41J256M16M chips, a second FLASH GD25Q512M chip; the eight DDR3SM41J256M16M chips and the Loongson 3A3000 chip are in access connection with 64 bit; the second FLASH GD25Q512M chip is connected with the Loongson 3A3000 chip through an SPI _ CS 0.
6. The modular small-volume, multi-type data interface processing device of claim 4 or 5, wherein said FPGA module comprises an FPGA JFM7K325T chip; the FPGA JFM7K325T chip is connected with an external interface P2 through a GTX interface, a GPIO interface and an LVDS interface;
the FPGA JFM7K325T chip is connected with an external interface P0 through a SYSRESET interface and a REF _ CLK interface;
the FPGA JFM7K325T chip is connected with the Bridge Loongson 7A10000 chip through UART2, UART3, SPI _ CS1, LPC, PWM, PCIE and GPIO.
7. The modular small-volume multi-type data interface processing device as claimed in claim 6, wherein said FPGA module further comprises a configuration chip GD25Q512M, said configuration chip GD25Q512M is connected to FPGA JFM7K325T chip through SPI.
8. The modular small-volume, multi-type data interface processing device according to claim 7, further comprising a monitoring interaction module, said monitoring interaction module comprising a power supply unit, a monitoring interaction unit;
the power supply unit is connected with the monitoring interaction unit, the FPGA JFM7K325T chip, the Loongson 3A3000 chip and the Bridge Loongson 7A10000 chip;
and the monitoring interaction unit is in data connection with a Bridge Loongson 3A3000 chip and an FPGA JFM7K325T chip.
9. The modular small-volume multi-type data interface processing device as claimed in claim 8, wherein the power supply unit comprises an XC388QDC chip, a plurality of DC-DC LYM4644 chips, an input terminal of the XC388QDC chip is connected to 3.3V and 12V DC power supplies, and outputs 12V DC power supplies to the plurality of DC-DC LYM4644 chips, and the DC-DC LYM4644 chips are connected to the monitoring interaction unit, the FPGA JFM7K325T chip, the loongson 3a3000 chip, and the Bridge loongson 7a10000 chip;
the monitoring interaction unit comprises a temperature sensor LC423 and an MCU GD32F103CBT6 chip, and the temperature sensor LC423 is connected with the MCU GD32F103CBT6 chip through an SPI;
the MCU GD32F103CBT6 chip is connected with the DC-DC LYM4644 chip through power-on control, and the DC-DC LYM4644 chip is in data interactive connection with the FPGA JFM7K325T chip and the Loongson 3A3000 chip through UART interfaces.
10. The modular small-volume multi-type data interface processing device according to claim 9, wherein the FPGA JFM7K325T chip, the Loongson 3a3000 chip, the MCU GD32F103CBT6 chip, and the Bridge Loongson 7a10000 chip are all provided with JTAG test interfaces.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN117033278A (en) * | 2023-10-08 | 2023-11-10 | 北京云成金融信息服务有限公司 | Data transmission method and system for multiple types of interfaces |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117033278A (en) * | 2023-10-08 | 2023-11-10 | 北京云成金融信息服务有限公司 | Data transmission method and system for multiple types of interfaces |
| CN117033278B (en) * | 2023-10-08 | 2024-04-12 | 华能资本服务有限公司 | Data transmission method and system for multiple types of interfaces |
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