CN215117312U - Real-time signal processing platform based on MPSOC - Google Patents

Abstract

The utility model discloses a real-time signal processing platform based on MPSOC, real-time signal processing platform based on MPSOC carries on the use on the integrated circuit board, and includes: the FPGA module, the storage module, the interface module, the power module, the clock module and the function extension module are all electrically connected. The platform has the characteristics of high integration level, small volume and low power consumption. The minimum embedded system design can be completed on a 3U-size board card. The method conforms to the trend of miniaturization development of modern electronic communication. Just the utility model discloses an extend the interface and use the FMC connector as expansion interface, the FMC connector possesses high-speed interface difference pair and single-ended IO, can expand the collection playback daughter card or other function daughter card platforms of different functions according to user's demand, provides nimble extended functionality for the integrated circuit board.

Description

Real-time signal processing platform based on MPSOC

Technical Field

The utility model relates to an electronic equipment technical field, in particular to real-time signal processing platform based on MPSOC.

Background

With the rapid development of semiconductor technology, the integration level and performance of FPGA devices are continuously improved, and the implementation of electronic circuit design and manufacture by using FPGA technology has become an important solution with high efficiency and reliability, and is increasingly widely applied in the fields of industrial control, signal processing, network communication, graphic images and the like. Modern electronic communication systems have increasingly strict requirements on volume, power consumption and the like in addition to higher performance indexes.

High index, little volume, low-power consumption etc. requirement based on modern electronic communication system, the utility model designs a real-time signal processing platform based on MPSOC.

SUMMERY OF THE UTILITY MODEL

The to-be-solved technical problem of the utility model is to overcome prior art's defect, provide real-time signal processing platform based on MPSOC.

Real-time signal processing platform based on MPSOC carries on the integrated circuit board and uses, and includes:

an FPGA module: for executing programs, data processing, other module circuit control, etc.;

a storage module: the system is used for accessing data for the board card;

an interface module: the board card is used for an external data interaction function;

a power supply module: the circuit board is used for providing working voltage for the board card;

a clock module: the system is used for providing a working clock for each functional module of the board card;

the function expansion module: is used for the function expansion of the board card,

the FPGA module, the storage module, the interface module, the power supply module, the clock module and the function extension module are electrically connected.

As an optimized technical scheme of the utility model, the electric program is gone up in the FPGA module execution, and the mode of electric program has SD card program guide mode, QSPI-Flash program guide mode, EMMC program guide mode three kinds on the FPGA module execution.

As an optimized technical solution of the present invention, the memory module includes a DDR4 memory module and an EMMC memory module.

As an optimized technical solution of the present invention, the interface module includes a USB2.0/3.0 interface, a SATA interface, a RS232 debug interface, a gigabit ethernet interface, a QSFP interface, and a DisplayPort interface.

As an optimized technical scheme of the utility model, clock module is including crystal oscillator and clock generator.

As an optimized technical solution of the present invention, the function expanding module includes an FMC connector.

As an optimal technical scheme of the utility model, the integrated circuit board is 3U standard integrated circuit board size.

Compared with the prior art, the beneficial effects of the utility model are as follows:

the utility model provides a real-time signal processing platform based on MPSOC, real-time signal processing platform based on MPSOC adopts Zynq UltraScale + MPSoC design, based on the high integrated level of this chip, and is small, the characteristics of low-power consumption. The minimum embedded system design can be completed on a 3U-size board card. The method conforms to the trend of miniaturization development of modern electronic communication. Just the utility model discloses an extend the interface and use the FMC connector as expansion interface, the FMC connector possesses high-speed interface difference pair and single-ended IO, can expand the collection playback daughter card or other function daughter card platforms of different functions according to user's demand, provides nimble extended functionality for the integrated circuit board. Additionally, the utility model discloses storage mode to FPGA designs not singlely, has designed two kinds of storage modes of DDR4 and EMMC, also can carry out the mass storage with external SATA dish. The storage mode and capacity of the platform are greatly increased. Finally, the utility model designs a large amount of external interface modules, including USB2.0/3.0, SATA, RS232 debugging interface, ethernet interface, QSFP interface and displayPort interface, can satisfy the different external interface operation requirements of user.

Drawings

The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention, and together with the description, do not constitute a limitation of the invention, in which:

fig. 1 is a functional block diagram of a signal processing universal board card;

FIG. 2 is a schematic diagram of a power-on implementation of an FPGA;

FIG. 3 is a schematic diagram of a power tree and power sequence;

fig. 4 is a functional block diagram of a clock tree.

Detailed Description

The preferred embodiments of the present invention will be described in conjunction with the accompanying drawings, and it will be understood that they are presented herein only to illustrate and explain the present invention, and not to limit the present invention.

Wherein like reference numerals refer to like parts throughout.

In addition, if a detailed description of the known art is not necessary to show the features of the present invention, it is omitted. It should be noted that the terms "inner" and "outer" refer to directions toward and away from, respectively, the geometric center of a particular component.

It should also be noted that, unless expressly stated or limited otherwise, the terms "disposed" and "connected" are to be construed broadly, e.g., as meaning fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.

Examples

The embodiment provides a real-time signal processing platform based on an MPSOC system on chip, the platform is designed based on an MPSOC of XILINX corporation, the size of a 3U standard board card is adopted, and a basic functional block diagram of the platform is shown in fig. 1. The system is characterized by comprising the following functional modules:

an FPGA module: for executing programs, data processing, other module circuit control, etc.;

2. a storage module: the system is used for accessing data for the board card;

3. an interface module: the board card is used for an external data interaction function;

4. a power supply module: the circuit board is used for providing working voltage for the board card;

5. a clock module: the system is used for providing a working clock for each functional module of the board card;

6. the function expansion module: is used for the function expansion of the board card,

the FPGA module, the storage module, the interface module, the power supply module, the clock module and the function extension module are electrically connected.

An FPGA module:

in the embodiment, the main FPGA processing chip adopts XCZU7EG-FFVC1156 of Zynq UltraScale + MPSoC series of XILINX company. The method is mainly used for onboard program electrifying execution, control and data processing of each functional module of the board card and the like. The Zynq UltraScale + MPSoC processing system mainly has the following characteristics:

a) an application processing unit (ARU) employing a quad-core ARM cortex-A53 processor:

the new generation of ARMv8 architecture supports 32 or 64 bit data widths;

the method is very suitable for Linux and SMP/AMP application systems of bare computers.

b) A real-time processing unit (RPU) employing a dual core ARM Cortex-R5 processor:

low latency, high deterministic performance;

and the APU task is shared.

c) The latest integrated hardened multimedia module:

a Graphics Processing Unit (GPU);

a 4Kx2K 60fps video decoder/decoder (VCU);

4Kx2K 30fps Display Port interface.

d) The latest integrated high-speed peripheral:

PCIE Gen1 or Gen2 root complexes and integrated endpoint modules, x1, x2, and x4 channels;

USB 3.0/2.0 with host, device and OTG modes;

gigabit ethernet with jumbo frames and precision time protocol;

SATA 3.1 host;

up to 6GB/s of dedicated Quad transceivers.

e) General and boot peripherals:

CAN, I2C, QSPI, SD, eMMC and NAND flash memory interfaces;

GPIO, UART and trace port.

f) A 6-port DDR controller with ECC, supporting DDR3, DDR3L, LPDDR3 and DDR4 of x32/x 64;

g) an integrated Platform Management Unit (PMU) supporting multiple power domains;

h) an integrated Configuration Security Unit (CSU);

i) providing TrustZone support;

j) peripheral and memory protection;

the most important module of the embodiment is Zynq UltraScale + MPSoC, which mainly performs the following two functions:

(1) and (3) electrifying execution:

FPGA has the multiple electric program guide mode of going up, for the convenience of user's in-service use, the utility model discloses an SD card, QSPI-Flash, three kinds of program guide modes of EMMC come as the procedure start route.

The SD card is a new generation memory device based on semiconductor flash memory, because its is small, data transmission is fast, excellent characteristics such as hot plug, are used on portable device extensively, the utility model discloses a 104031 and 0811 SD card shell model, through inserting the SD card, the FPGA can read wherein procedure and accomplish the start-up after the electricity.

QSPI is a shorthand of queue SPI, is an extension of SPI interface proposed by Motorola, and is more widely applied than SPI. On the basis of the SPI protocol, Motorola corporation enhances the functions thereof, adds a queue transmission mechanism and promotes a queue serial peripheral interface protocol (namely the QSPI protocol). The utility model discloses a QSPI-Flash mode, power-on back FPGA can read wherein procedure and accomplish the start-up.

The EMMC is a standard specification of an embedded memory that is established by the MMC association and mainly aims at products such as mobile phones or tablet computers. The eMMC integrates a controller in the package, provides standard interfaces, and manages the flash memory. After the power is on, the FPGA can read the program in the FPGA to complete the starting.

The FPGA program guide MODE can be controlled by pulling up and down four pins of PS _ MODE [0:3] at the PS end. Therefore, the corresponding program guide mode can be selected by adopting the dial switch to carry out up-down control on the four control pins. The schematic block diagram is shown in fig. 2.

(2) Control and data processing of modules

Zynq UltraScale + MPSoC has a large number of IO pins, and data transmission and control of various external interfaces of the interface module are completed through the IO pins. In addition, Zynq UltraScale + MPSoC has pins such as GTH, and the GTH clock that the cooperation clock module provided can accomplish data interaction and processing with other external platforms through the FMC interface of extension module.

A storage module:

the storage modes of the FPGA are various, and there are some modes such as RAM (random access memory readable and writable), ROM (read only memory), CAM (content addressable memory), DRAM (dynamic random access memory), SRAM (static random access memory), FLASH memory, FIFO (first in first out buffer), and the like. Generally, only one way is needed, but for the considerations of microcontroller selection, voltage range, battery life, read/write speed, memory size, memory characteristics, erase/write endurance, and overall system cost, the following three ways are used for storage:

(1) DDR4 memory module

The FPGA of the embodiment is externally connected with 4 chips of 64-bit DDR4 with the capacity of 4GB at PS ends and PL ends respectively, the model is MT40A512M16JY-083E, and the maximum speed is 2400 Mb/s.

(2) An EMMC memory module:

the FPGA of this embodiment mounts 1 EMMC chip on the PS terminal, and can be used to store programs and data. The model is MTFC32GJDDQ-4M IT, which is a flash memory chip with 32GB capacity.

An interface module:

the utility model discloses external interface module includes: USB2.0/3.0, SATA, RS232 debug interface, Ethernet interface, QSFP interface and DisplayPort interface.

(1)USB2.0/3.0：

The present embodiment employs a Microchip USB3320 chip, which is a high speed USB2.0 transceiver that provides a configurable physical layer (PHY) solution that is an excellent match for a variety of products. The FPGA is compatible with a USB3.0 interface by adding a group of USB transmitting and receiving signals on the GTR of the PS end to be matched with the USB 2.0.

(2) SATA interface:

in this embodiment, 5607 plus 4200-SH is used as a connector of the SATA interface, and the FPGA completes data interaction of the SATA interface through the GTR at the PS end, and can be used for external large-capacity hard disk storage expansion.

(3) RS232 debugging interface:

the RS232 standard interface is one of the commonly used serial communication interface standards, and in this embodiment, a wiring terminal is used to complete signal transmission between the FPGA and the external RS232 bus, so as to facilitate debugging of a user.

(4) Gigabit ethernet interface:

in this embodiment, signals such as data and clock of gigabit ethernet are transmitted and received through the MIO pin of the PS terminal, and a connector of HFJ11-E1G41E-L12RL type is used as a hardware connector of the gigabit ethernet interface.

(5) QSFP interface:

in the embodiment, the QSFP interface is adopted to complete the transmission of the FPGA and the external optical fiber data.

(6) DisplayPort interface:

in the embodiment, the DisplayPort interface is adopted to complete the transmission of data between the FPGA and the external video interface.

A power supply module:

in the embodiment, 12V external power supply input is adopted, and the power supply is converted into a power supply required in the board through a power supply module to supply power to the board card. The DC-DC voltage reduction chip of the power module adopts the power domains with larger current in the board card such as LTM4630, LTM4644 and LTM4633 of ADI company to provide voltage, and the power domain with smaller current adopts TPS7A8300 of TI company to provide voltage. The power supply power-on sequence of the embodiment is realized by PGOOD power-on completion of a power supply chip and cascade connection of RUN power supply enable signals, and a main power supply in a board is automatically powered on after a 12V external power supply is input. The power tree composition is shown in fig. 3.

A clock module:

the clock module mainly provides clocks for the FPGA module and the interface module, the clock module group comprises a crystal oscillator and a clock generator, the crystal oscillator provides a stable clock source for the clock generator, the clock generator provides an on-board FPGA required clock and part of interface module clocks, and the rest part of the interface module clocks are directly provided by the crystal oscillator.

According to the above-mentioned interface and function of this embodiment, statistics shows this uses novel design clock demand:

a) USB3.0 high speed bus reference clock 26MHz (fixed);

b) USB2.0 physical layer chip reference clock 24MHz (fixed);

c) SATA high speed bus reference clock 125MHz (fixed);

d) gigabit ethernet physical layer chip reference clock 25Mhz (fixed);

e) the MPSoC PS reference clock is 33.3333MHz (fixed);

f) mposc PL global reference clock 100MHz (default/variable);

g) DDR4 reference clock 100MHz (default/variable);

h) QSFP reference clock 156.25MHz (default/variable);

i) DisplayPort reference clock 27MHz (fixed);

in addition to the crystal oscillator, the clock generator of this embodiment selects a CDCM6208 chip of TI company, which is a multipurpose, low-jitter, low-power consumption frequency synthesizer, and can generate eight low-jitter clock outputs by using one of two inputs of a specific low-frequency crystal oscillator or CML, LVPECL, LVDS, or LVCMOS signals, where the outputs can be selected from a high-swing CML similar to LVPECL, a normal-swing CML, and a low-power CML similar to LVDS, and the composition of the clock tree is shown in fig. 4.

An expansion module:

in this embodiment, the FMC connector is used as a function expansion connector to realize function expansion of the board card. The FMC connector interface definition is based on the VITA 57.1 standard definition, providing an 8x GTH high speed interface, as well as multiple single ended and differential pair I/O interfaces. The FPGA completes data interaction and processing with other external platforms through GTH and I/O interface, and the model is ASP-184329-01.

Finally, it should be noted that: although the present invention has been described in detail with reference to the foregoing embodiments, it will be apparent to those skilled in the art that modifications may be made to the embodiments described in the foregoing embodiments, or equivalents may be substituted for elements thereof. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (9)

1. Real-time signal processing platform based on MPSOC, its characterized in that, real-time signal processing platform based on MPSOC carries on the integrated circuit board and uses, and includes:

an FPGA module: for executing programs, data processing, other module circuit control, etc.;

a storage module: the system is used for accessing data for the board card;

an interface module: the board card is used for an external data interaction function;

a power supply module: the circuit board is used for providing working voltage for the board card;

a clock module: the system is used for providing a working clock for each functional module of the board card;

the function expansion module: is used for the function expansion of the board card,

the FPGA module, the storage module, the interface module, the power supply module, the clock module and the function extension module are electrically connected.

2. The MPSOC-based real-time signal processing platform of claim 1, wherein the FPGA module executes a power-on program, and the FPGA module executes the power-on program in three modes, namely an SD card program boot mode, a QSPI-Flash program boot mode, and an EMMC program boot mode.

3. The MPSOC-based real-time signal processing platform of claim 1, wherein the memory modules include a DDR4 memory module and an EMMC memory module.

4. The MPSOC-based real-time signal processing platform of claim 3, wherein the interface module comprises a USB2.0/3.0 interface, a SATA interface, a RS232 debug interface, a gigabit Ethernet interface, a QSFP interface, and a DisplayPort interface.

5. The MPSOC-based real-time signal processing platform of claim 1, wherein the clock module comprises a crystal oscillator and a clock generator.

6. The MPSOC-based real-time signal processing platform of claim 1, wherein the function extension module comprises an FMC connector.

7. The MPSOC-based real-time signal processing platform of claim 1, wherein the board card is a 3U standard board card size.

8. The MPSOC-based real-time signal processing platform of claim 1, wherein the MPSOC-based real-time signal processing platform is mounted on an MPSOC chip of XILINX corporation.

9. The MPSOC-based real-time signal processing platform of claim 1, wherein the FPGA module comprises an XCZU7EG-FFVC1156 processor of the Zynq UltraScale + MPSOC family of XILINX corporation.

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