CN216014247U

CN216014247U - FPGA-based data acquisition control panel and data recorder

Info

Publication number: CN216014247U
Application number: CN202121653800.5U
Authority: CN
Inventors: 潘枫; 魏健民; 王萌; 孙恩元
Original assignee: Hunan Econavi Technology Co Ltd
Current assignee: Hunan Econavi Technology Co Ltd
Priority date: 2021-07-20
Filing date: 2021-07-20
Publication date: 2022-03-11
Anticipated expiration: 2031-07-20

Abstract

The utility model provides a data acquisition control panel and a data recorder based on FPGA, wherein the data acquisition control panel comprises an FPGA unit, an optical fiber connector and an optical fiber transceiver module used for transmitting acquired data or played back data, the optical fiber transceiver module comprises at least 12 optical fiber channels, and data interfaces at PL ends in the FPGA unit are respectively connected with the optical fiber connector through the corresponding optical fiber channels; the PL end is further provided with a SATA3.0 interface, a USB3.0 interface and a first network interface, the SATA3.0 interface is connected with external storage equipment, the USB3.0 interface is connected with external USB equipment, and the first network interface is connected with external network equipment. The utility model has higher integration level, also has various high-speed transmission interfaces, and can meet the requirement of high-speed data transmission.

Description

FPGA-based data acquisition control panel and data recorder

Technical Field

The utility model relates to the field of data acquisition and storage, in particular to a data acquisition control panel and a data recorder based on an FPGA (field programmable gate array).

Background

The increasing popularity of electronic products has driven the rapid development of data acquisition technologies and data storage technologies. Particularly, in the technical fields of satellite navigation, electronics, radar and the like, data acquisition and storage systems play more and more important roles. Moreover, the technical requirements on the data acquisition and storage system are also increasing day by day: high data transmission rate (the unloading rate of more than 1.5GB/s and the recording rate of more than 82.8 Gbps), mass storage capacity, power consumption and low cost. Conventional data acquisition and storage systems have difficulty meeting such requirements.

The Field Programmable Gate Array (FPGA) technology developed in recent years provides good technical support for a new generation of high-speed data acquisition and storage system. The FPGA has a great number of hardware resources, the available logic gate circuit integrated on one chip reaches the level of ten million, very high time frequency can be obtained through an internal phase-locked loop, the internal time consumption is small, and the efficiency is very high. The structure is flexible, a plurality of controllers, decoding codes and various peripheral interface circuits can be integrated, and therefore the data acquisition and data storage part can be designed by using the FPGA. In the aspect of signal processing, the FPGA has abundant kernel resources, so that the FPGA is convenient for a user to call. Therefore, the high-speed data acquisition and storage system adopts the FPGA, so that the design can be simplified, and the flexibility and the processing rate of the system can be improved.

With Xilinx promoting FPGA products such as ZYNQ and MPSoC series integrated with ARM hard cores, the FPGA can realize higher data throughput processing and storage performance at present, and how to apply the new generation FPGA to the field of data acquisition and storage so as to better play the performance of data acquisition and storage equipment is a problem to be solved urgently.

SUMMERY OF THE UTILITY MODEL

The technical problem to be solved by the utility model is as follows: aiming at the technical problems in the prior art, the utility model provides a data acquisition control board and a data recorder based on an FPGA (field programmable gate array). the ZYNQ UltraScale series FPGA is adopted, the integration level is higher, the required core processing function can be realized by using the data acquisition control board, the data acquisition control board has obvious advantages in design power consumption and volume compared with the traditional acquisition equipment, and the data acquisition control board also has various high-speed transmission interfaces and can meet the requirement of high-speed data transmission.

In order to solve the technical problems, the technical scheme provided by the utility model is as follows:

a data acquisition control panel based on FPGA comprises an FPGA unit, an optical fiber connector and an optical fiber transceiver module used for transmitting acquired data or played back data, wherein the optical fiber transceiver module comprises at least 12 optical fiber channels, the FPGA unit comprises a PL end used for data processing, the PL end is provided with data interfaces corresponding to the optical fiber channels one by one, and the data interfaces are connected with the optical fiber connector through the corresponding optical fiber channels respectively; the PL end is also provided with an SATA3.0 interface, and the data interface is connected with external storage equipment through the SATA3.0 interface and the first VPX connector in sequence; the PL end is also provided with a USB3.0 interface and a first network interface, the USB3.0 interface is connected with external USB equipment through the USB connector, and the first network interface is connected with external network equipment through the network connector.

Further, the FPGA unit further comprises a storage unit for storing an operating system, and the PS terminal is used for system management and is respectively connected with the storage unit and the PL terminal, so that the PS terminal starts the operating system and controls the PL terminal to perform data acquisition or data playback.

Furthermore, the system also comprises two cache modules for caching data, wherein the cache modules are respectively connected with the PL terminal and the PS terminal.

Further, the PL end comprises a data processing module, a data channel management module, a SATA drive module and a communication module for interacting with the PS end, the data interface is connected with the data channel management module through the data processing module, the data channel management module is connected with a cache module corresponding to the PL end and is connected with a SATA3.0 interface through the SATA drive module, so that the collected data is cached in the cache module and then output to an external storage device through the SATA3.0 interface, and the data to be played back of the external storage device is acquired through the SATA3.0 interface and sent to the cache module for caching.

Further, the data channel management module comprises a DDR write interface, a DDR read interface, a SATA read interface and a SATA write interface, the DDR write interface is connected with the SATA read interface, the data processing module is connected with the cache module corresponding to the PL side, the DDR read interface is connected with the SATA write interface, the data processing module is connected with the cache module corresponding to the PL side, and the SATA read interface and the SATA write interface are connected with the SATA drive module.

Furthermore, the debugging device also comprises a debugging connector, the PS end is provided with a JTAG debugging interface, and the JTAG debugging interface is connected with external debugging equipment through the debugging connector.

Further, the clock generator comprises a Si5341B clock generator for providing clock signals, and the Si5341B clock generator is connected with the PL terminal clock input end.

The optical fiber transceiver module further comprises a power module and a second VPX connector, wherein the input end of the power module is connected with external power supply equipment through the second VPX connector, and the output end of the power module is connected with the power supply ends of the optical fiber transceiver module and the PL end.

The utility model further provides a data recorder which comprises a VPX back plate, a power supply plate, a data acquisition control plate and at least five storage plates, wherein the VPX back plate, the power supply plate, the data acquisition control plate and the storage plates are arranged in a case, the power supply plate, the data acquisition control plate and the storage plates are respectively detachably connected with the VPX back plate, the data acquisition control plate is respectively connected with the power supply plate and the storage plates through the VPX back plate, and the data acquisition control plate is any one of the data acquisition control plates based on the FPGA.

Further, the storage board comprises a VPX 6U board card and a first solid state disk and a second solid state disk which are arranged on the VPX 6U board card, the second solid state disk and the first solid state disk are in one-to-one correspondence and are stacked on the upper portion of the corresponding first solid state disk, the first solid state disk is grouped in pairs, the first solid state disk in each group is oppositely arranged and the data ends are mutually connected, so that the first solid state disk in each group stores data in a dispersed manner, the second solid state disk is grouped in two pairs, the second solid state disk in each group is oppositely arranged and the data ends are mutually connected, so that the second solid state disk in each group stores data in a dispersed manner, the storage board is in one-to-one correspondence with the first VPX connectors of the data acquisition control board, each first VPX connector corresponds to at least 8 SATA3.0 interfaces, the first solid state disk and the second solid state disk are respectively at least 4 and correspond to the SATA3.0 interfaces in one-to one manner, and the data ends of the first solid state disk and the second solid state disk are respectively connected with the corresponding SATA3.0 interface through the corresponding first VPX connector.

Compared with the prior art, the utility model has the advantages that:

1. in the data acquisition control panel, a data interface at the PL end of the FPGA unit is connected with an optical fiber connector through an optical fiber transceiving module, an optical fiber single channel provides a rate of 10Gbps, the actual transmission rate of the single optical fiber channel is calculated according to the proportion of 20% of overhead of a transmission protocol and 20% of overhead of a data frame structure: 10G × 80% × 80% ═ 6.4Gbit/s = 800MB/s, the fiber transceiver module includes at least 12 fiber channels, 12 channels total theoretical transmission rate: in addition, in the data acquisition control panel, the PL end of the FPGA unit is also provided with a USB3.0 interface and a first network interface, so that high-speed data transmission modes such as a USB3.0 interface and a wired network can be supported.

2. The data recorder adopts a board card and back board mode, the power board, the data acquisition control board and the storage board are respectively detachably connected with the VPX back board, the number of the board cards with different functions can be reduced according to actual needs to reduce power consumption and reduce cost, or the number of the storage boards is increased according to actual needs to increase storage space and improve storage read-write speed, and meanwhile, the data acquisition control board and the storage boards are respectively and independently arranged, so that the number of storage media is prevented from being limited by the space layout of the data acquisition control board.

3. The data recorder comprises at least 5 storage boards, each storage board comprises at least 4 first solid state disks and at least 4 second solid state disks, at least 8 solid state disks are totally arranged, the data end of each solid state disk is connected with a corresponding SATA3.0 interface, the data end is calculated according to the writing speed of a single SATA3.0 interface of 300MB/s, and the recording speed of each storage board is as follows: 8 multiplied by 300M is 2400MB/s, the theoretical storage rate of 5 storage plates can reach 12GB/s, and the recording rate requirement of more than 82.8Gbps is met.

4. The power consumption of the data recorder mainly comes from the storage board, the storage board adopts the solid state disk, the maximum power consumption of the solid state disk is about 5W, and the maximum power consumption of a single storage board is only 45W, so that the lower power consumption can be realized.

Drawings

Fig. 1 is a block diagram illustrating a structure of a data acquisition control board according to an embodiment of the present invention.

FIG. 2 is a block diagram of an FPGA unit in an embodiment of the present invention.

Fig. 3 is a schematic structural diagram of a data recorder according to an embodiment of the present invention.

Fig. 4 is a schematic structural diagram of a memory board according to an embodiment of the utility model.

Illustration of the drawings: the system comprises a 1-FPGA unit, a 2-optical fiber connector, a 3-optical fiber transceiving module, a 4-first VPX connector, a 5-storage unit, a 6-cache module, a 7-debugging connector, an 8-Si5341B clock generator, a 9-power supply module, a 10-second VPX connector, an 11-VPX back plate, a 12-power supply plate, a 13-data acquisition control plate, a 14-storage plate, a 101-data processing module, a 102-data channel management module, a 103-STA drive module, a 104-communication module, a 140-VPX 6U board card, a 141-first solid state disk and a 142-second solid state disk.

Detailed Description

The utility model is further described below with reference to the drawings and specific preferred embodiments of the description, without thereby limiting the scope of protection of the utility model.

The ZYNQ UltraScale series FPGA is divided into a PL end and a PS end, wherein the PL end is a traditional FGPA and can be subjected to programmable logic design; and the PS end is a high-performance ARM, and embedded development can be performed.

As shown in fig. 1, based on the series of FPGAs, the present invention provides a data acquisition control board based on an FPGA, which includes an FPGA unit 1, an optical fiber connector 2 (i.e., an interface P6 in fig. 1), and an optical fiber transceiver module 3 for transmitting acquired data or played back data, where the optical fiber transceiver module 3 includes at least 12 optical fiber channels, the FPGA unit 1 includes a PL end for data processing, the PL end is provided with data interfaces corresponding to the optical fiber channels one to one, and the data interfaces are connected to the optical fiber connector 2 through the corresponding optical fiber channels respectively; the platform further comprises a first VPX connector 4 (namely P1-P5 in FIG. 1), the PL end is also provided with a SATA3.0 interface, and the data interface is connected with an external storage device through the SATA3.0 interface and the first VPX connector 4 in sequence; the FPGA unit 1 further comprises a PS end used for system management, and the PS end is connected with the storage unit 5 and the PL end respectively, so that the PS end starts the operating system and controls the PL end to perform data acquisition or data playback.

In this embodiment, the FPGA unit 1 uses an XCZU17EG chip, the optical fiber connector 2 uses an RPB5F12Q optical fiber backplane connector, the first VPX connector 4 uses a 1410187VPX connector, the storage unit 5 includes an SD card and a FLASH chip, the SD card stores a boot startup program of the PetalLinux system, and the FLASH chip stores a PetalLinux system file.

Through the structure, the PS end of the FPGA unit 1 in this embodiment is responsible for file system management, the PL end is responsible for data processing, the advantages of the PS end and the PL end can be exerted to the maximum, the data interface of the PL end is connected with the optical fiber connector through the optical fiber transceiver module, each data interface is connected with the corresponding optical fiber channel, each channel is independent from each other in the transmission process, and is not affected each other, the optical fiber single channel provides a rate of 10Gbps, and the actual transmission rate of the single optical fiber channel is calculated according to the ratio of 20% of the overhead of the transmission protocol and 20% of the overhead of the data frame structure: 10G × 80% × 80% ═ 6.4Gbit/s = 800MB/s, the fiber transceiver module includes at least 12 fiber channels, 12 channels total theoretical transmission rate: 800MB/s × 12 is 9.6GB/s, which can meet the requirement of users for high transmission data rate.

In this embodiment, the data acquisition control board further includes a USB connector and a network connector, the PL side is further provided with a USB3.0 interface and a first network interface, the USB3.0 interface is connected to an external USB device through the USB connector, and the first network interface is connected to an external network device through the network connector. The first network interface is a gigabit network interface, the theoretical transmission speed is 1.25GB/s, and the USB3.0 interface and the first network interface are respectively connected with external storage equipment through the SATA3.0 interface and the first VPX connector 4 in sequence, so that the data acquisition control board can support high-speed data transmission modes such as USB3.0 and a wired network.

As shown in fig. 1, the data acquisition control board of this embodiment further includes two buffer modules 6 for buffering data, where the buffer modules 6 are respectively connected to the PL end and the PS end. The cache module 6 adopts a group of DDR4 memory, each group comprises 4 DDR4-2400 memory particles, and DDR4 SDRAM is a short for fourth generation double data rate dynamic synchronous random access memory. Each pin of the DDR4 memory can provide 2Gbps (256MB/s) of bandwidth, the DDR4-3200 is 51.2GB/s, which is higher than DDR3-1866 by over 70%, the DDR4-3200 has more reliable transmission specifications, the data reliability is further improved, the working voltage is reduced to 1.2V, and the energy is saved. The specific model of the DDR4-2400 memory particles in this embodiment adopts MT40a512M16LY-083E, 4 pieces to form 4GB capacity. The buffers of the PS end and the PL end can also share the buffers through an on-chip AXI data bus, and the total bandwidth of the system data buffer is 1200MHz multiplied by 2 (rising edge and falling edge) multiplied by 64 (bit width)/8 multiplied by 2 which is 38.4GB/s, so that the requirement on the buffer speed during data high-speed transmission can be met.

As shown in fig. 2, in this embodiment, the PL end includes a data processing module 101, a data channel management module 102, an SATA drive module 103 for reading and writing data from and to an external storage device, and a communication module 104 for interacting with a PS end, where the data interface is connected to the data channel management module 102 through the data processing module 101, the data channel management module 102 is connected to the PS end through the communication module 104, the data channel management module 102 is connected to a cache module 6 corresponding to the PL end and is connected to an SATA3.0 interface through the SATA drive module 103, so that collected data is cached in the cache module 6 and then output to an external storage device through the SATA3.0 interface, and further, played back data of the external storage device is acquired through the SATA3.0 interface and sent to the cache module 6 for caching. Through the structure, the data is cached in the cache module 6 before the data is written into the external storage device or after the data is read, the probability of data errors in the transmission process is reduced, and meanwhile, the data interaction between the PS end and the PL end is realized.

In this embodiment, the SATA drive module 103 includes a RAID controller, and may form a storage array with external storage devices, thereby increasing the rate of reading and writing data to the external storage devices.

Further, as shown in fig. 2, in this embodiment, the data channel management module 102 includes a DDR write interface, a DDR read interface, a SATA read interface, and a SATA write interface, where the DDR write interface is connected to the SATA read interface, the data processing module 101, the communication module 104, and the cache module 6 corresponding to the PL end, the DDR read interface is connected to the SATA write interface, the data processing module 101, the communication module 104, and the cache module 6 corresponding to the PL end, and the SATA read interface and the SATA write interface are connected to the SATA drive module 103. Through the structure, the data channel between the cache module 6 and the external storage device, the data channel between the data interface of the PL terminal and the cache module 6 and the data channel between the cache module 6 and the PS terminal are respectively independent, and the influence between the data channels in the data transmission process is avoided.

As shown in fig. 1, the data acquisition control board of this embodiment further includes a debug connector 7, the PS terminal is provided with a JTAG debug interface, and the JTAG debug interface is connected to an external debug device through the debug connector 7. The debugging connector 7 of the embodiment adopts a J30J-21ZK rectangular connector, and through the structure, an external debugging device can be directly connected with the rectangular connector to debug the data acquisition control board.

As shown in FIG. 1, the data acquisition control board of the present embodiment further comprises a time-sharing module for providing time informationA clock signal Si5341B clock generator 8, the Si5341B clock generator 8 being connected to the PL terminal and the PS terminal clock input terminal. The Si5341B clock generator is an ultra-low jitter clock generator with arbitrary clock input and arbitrary clock output, and supports maximum 10-path clock output. Si5341B clock generator with wideband phase-locked loop, and its usage^TMFractional synthesizer techniques provide a versatile high performance clock generator platform. This highly flexible architecture enables synthesis of up to 10 wide range integer and non-integer frequency differential clocks up to 1GHz while providing phase jitter performance below 100fs rms with an error of 0 ppm. Each clock output can be assigned its own format and output voltage, enabling a single Si5341B clock generator to replace multiple clock ICs and oscillators into a true "clock tree on a chip". The main characteristics of the Si5341B clock generator include: generating any combination of output frequencies from any input frequency; ultra-low jitter 90fs rms; input frequency range: the external crystal is 25 to 54 MHz; the differential clock is 10 to 750 MHz; output frequency range: the difference is 100Hz to 1028 MHz; single ended 100MHz to 250 MHz; the output is compatible with LVDS, LVPECL, LVCMOS, CML, HCSL and programmable signal amplitude; locking the gap clock input; a zero delay mode can be selected; configuration mode I²C or SPI bus; (8) working temperature: -40 to +85 ℃. The Si5341B clock generator can better meet the requirement of the present embodiment for integration level, and can effectively reduce the noise problem caused by inter-stage transmission.

As shown in fig. 1, the data acquisition control board of this embodiment further includes a power module 9 and a second VPX connector 10 (i.e., an interface P0 in fig. 1), an input end of the power module 9 is connected to an external power supply device through the second VPX connector 10, and an output end of the power module 9 is connected to power supply ends of the optical fiber transceiver module 3, the PL end, and the PS end. In this embodiment, the second VPX connector is an 1410189VPX plug connector.

As shown in fig. 1, in this embodiment, the SATA3.0 interface of the PL end only corresponds to a portion of the first VPX connector 4, and for another portion of the first VPX connector 4, the PL end is further provided with a second network interface, an RS232 interface, and an RS242 interface, the second network interface, the RS232 interface, and the RS242 interface are respectively connected to different external devices through the corresponding first VPX connector 4, the second network interface is a gigabit network interface, and a PHY chip is further provided between the gigabit network interface and the corresponding first VPX connector 4, so that the applicability of the data acquisition control board of this embodiment is increased.

In this embodiment, the first VPX connector 4, the optical fiber connector 2, and the second VPX connector 10 are respectively disposed on one side of the data acquisition control board for connecting the VPX backplane, and the USB connector, the network connector, and the debugging connector 7 are respectively disposed on the front panel of the data acquisition control board, so that the layout is reasonable and the connection and debugging are facilitated.

As shown in fig. 3, based on the data acquisition control board, this embodiment further provides a data recorder, which includes a VPX backplane 11, a power board 12, a data acquisition control board 13, and at least five storage boards 14 that are disposed in a chassis, where the power board 12, the data acquisition control board 13, and the storage boards 14 are detachably connected to the VPX backplane 11, the data acquisition control board 13 is connected to the power board 12 and the storage boards 14 through the VPX backplane 11, and the data acquisition control board 13 is the above-mentioned FPGA-based data acquisition control board.

In this embodiment, the power board 12, the data acquisition control board 13, the storage board 14 are detachably connected to the VPX backplane 11, the number of boards with different functions can be reduced according to actual needs to reduce power consumption and reduce cost, or the number of the storage boards 14 can be increased according to actual needs to increase storage space and improve the read-write speed of storage, and meanwhile, because the data acquisition control board 13 and the storage boards 14 are independently arranged respectively, the number of storage media is prevented from being limited by the spatial layout of the data acquisition control board 13.

In this embodiment, the VPX backplane 11 uses a hybrid optical-electrical VPX module connector, wherein the transmission optical fiber signal uses the middle-sized photoelectric rectangular optical fiber connector RPB5F12Q, and two MT optical fiber connectors can be connected, so as to perform transmission of the collected data and the played back data with the optical fiber connector 2 of the data collection control board 13.

In this embodiment, the power panel 12 is used for outputting different voltages for the data acquisition control panel 13 and the storage panel 14 to work so as to meet the power supply requirement, and includes an ac/dc conversion unit, and can convert the input ac into the working voltage of the data acquisition control panel 13 and the storage panel 14 for output.

In this embodiment, the storage board 14 may be a VPX 6U board or a VPX 3U board, and the VPX 6U board can accommodate at most 8 storage media; the VPX 3U card can accommodate 4 storage media at most.

As shown in fig. 4, in the present embodiment, the storage board 14 adopts VPX 6U board cards, which include a VPX 6U board card 140 and a first solid state disk 141 and a second solid state disk 142 disposed on the VPX 6U board card 140, an effective space of the VPX 6U board card is 233mm x 160mm, in order to reduce a volume and enhance connection reliability in consideration of a space of a related interface, in the present embodiment, the second solid state disk 142 and the first solid state disk 141 are in one-to-one correspondence and stacked on an upper portion of the corresponding first solid state disk 141, and the stacked second solid state disk 142 and the first solid state disk 141 are fixed by a fixing member, a height of 2 stacked solid state disks plus a thickness of the fixing member is about 17mm, which meets a requirement of a height of the VPX 6U board card 5HP, and the first solid state disks 141 are grouped two by two, the first solid state disks 141 in each group are disposed oppositely and data ends are connected to each other, the data are stored in a dispersed manner in each group of the first solid state disks 141, the second solid state disks 142 are grouped in pairs, the second solid state disks 142 in each group are arranged oppositely, and data ends of the second solid state disks 142 are connected with each other, so that the data are stored in a dispersed manner in each group of the second solid state disks 142, the storage board 14 corresponds to the first VPX connectors 4 of the data acquisition control board 13 one to one, each first VPX connector 4 corresponds to at least 8 SATA3.0 interfaces, the first solid state disks 141 and the second solid state disks 142 correspond to at least 4 SATA3.0 interfaces one to one, and the data ends of the first solid state disks 141 and the second solid state disks 142 are connected to the corresponding SATA3.0 interfaces through the corresponding first VPX connectors 4.

The data recorder of the embodiment includes at least 5 storage boards 14, each storage board 14 includes at least 4 first solid state disks 141 and at least 4 second solid state disks 142, and at least 8 solid state disks in total, and the data end of each solid state disk is connected to a corresponding SATA3.0 interface, and calculated according to a single SATA3.0 interface writing speed of 300MB/s, the recording rate of each storage board 14 is: 8 multiplied by 300M is 2400MB/s, the theoretical storage rate of 5 storage boards 14 can reach 12GB/s, and the recording rate requirement of more than 82.8Gbps is met. In addition, the power consumption of the data recorder of the embodiment mainly comes from the storage board 14, the maximum power consumption of the solid state disk adopted by the storage board 14 is about 5W, and the maximum power consumption of a single storage board 14 is only 45W, so that lower power consumption can be realized.

The following describes the operation of the data recorder of the present embodiment:

in the recording mode, a data acquisition control board 13 of the data recorder acquires data through the optical fiber connector 2, sends the data to the FPGA unit 1 through the optical fiber channel 12 for data screening and coding, writes the data into a storage board 14, and performs classified management on data files.

In the playback mode, the FPGA unit 1 of the data acquisition control board 13 reads data from the storage board 14, and outputs the data through the optical fiber connector 2 after data recombination and decoding are completed.

In the unloading mode, the data acquisition control board 13 reads data from the storage board 14, and outputs the data through the high-speed interfaces such as the optical fiber connector 2, the gigabit network interface or the USB3.0 interface after finishing data recombination and decoding processing, thereby facilitating unloading of the data.

The foregoing is considered as illustrative of the preferred embodiments of the utility model and is not to be construed as limiting the utility model in any way. Although the present invention has been described with reference to the preferred embodiments, it is not intended to be limited thereto. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical spirit of the present invention should fall within the protection scope of the technical scheme of the present invention, unless the technical spirit of the present invention departs from the content of the technical scheme of the present invention.

Claims

1. The FPGA-based data acquisition control board is characterized by comprising an FPGA unit (1), an optical fiber connector (2) and an optical fiber transceiver module (3) used for transmitting acquired data or played back data, wherein the optical fiber transceiver module (3) comprises at least 12 optical fiber channels, the FPGA unit (1) comprises a PL end used for data processing, the PL end is provided with data interfaces in one-to-one correspondence with the optical fiber channels, and the data interfaces are respectively connected with the optical fiber connector (2) through the corresponding optical fiber channels; the data interface is connected with external storage equipment through the SATA3.0 interface and the first VPX connector (4) in sequence; the PL end is also provided with a USB3.0 interface and a first network interface, the USB3.0 interface is connected with external USB equipment through the USB connector, and the first network interface is connected with external network equipment through the network connector.

2. The FPGA-based data acquisition control board of claim 1, further comprising a storage unit (5) for storing an operating system, wherein the FPGA unit (1) further comprises a PS terminal for system management, and the PS terminal is connected with the storage unit (5) and the PL terminal respectively, so that the PS terminal starts the operating system and controls the PL terminal to perform data acquisition or data playback.

3. The FPGA-based data acquisition control board of claim 2, further comprising two buffer modules (6) for buffering data, wherein the buffer modules (6) are respectively connected to the PL terminal and the PS terminal.

4. The FPGA-based data acquisition control board of claim 3, wherein the PL terminal comprises a data processing module (101), a data channel management module (102), an SATA driving module (103) and a communication module (104) for interacting with the PS terminal, the data interface is connected with the data channel management module (102) through the data processing module (101), the data channel management module (102) is connected with the cache module (6) corresponding to the PL terminal and is connected with the SATA3.0 interface through the SATA driving module (103), so that the acquired data is cached in the cache module (6) and then is output to the external storage device through the SATA3.0 interface, and the played back data of the external storage device is acquired through the SATA3.0 interface and is sent to the cache module (6) for caching.

5. The FPGA-based data acquisition control board of claim 4, wherein the data channel management module (102) comprises a DDR write interface, a DDR read interface, a SATA read interface and a SATA write interface, the DDR write interface is connected with the SATA read interface, the data processing module (101) is connected with the cache module (6) corresponding to the PL terminal, the DDR read interface is connected with the SATA write interface, the data processing module (101) is connected with the cache module (6) corresponding to the PL terminal, and the SATA read interface and the SATA write interface are connected with the SATA drive module (103) respectively.

6. The FPGA-based data acquisition control board as recited in claim 2, further comprising a debug connector (7), wherein the PS terminal is provided with a JTAG debug interface, and the JTAG debug interface is connected with an external debug device through the debug connector (7).

7. The FPGA-based data acquisition control board of claim 1, further comprising a Si5341B clock generator (8) for providing a clock signal, wherein the Si5341B clock generator (8) is connected to a clock input terminal of the PL terminal.

8. The FPGA-based data acquisition control board as claimed in claim 1, further comprising a power module (9) and a second VPX connector (10), wherein an input end of the power module (9) is connected with an external power supply device through the second VPX connector (10), and an output end of the power module (9) is connected with power supply ends of the fiber transceiving module (3) and the PL.

9. The data recorder is characterized by comprising a VPX back plate (11), a power panel (12), a data acquisition control panel (13) and at least five storage panels (14) which are arranged in a case, wherein the power panel (12), the data acquisition control panel (13) and the storage panels (14) are detachably connected with the VPX back plate (11), the data acquisition control panel (13) is connected with the power panel (12) and the storage panels (14) through the VPX back plate (11), and the data acquisition control panel (13) is the FPGA-based data acquisition control panel according to any one of claims 1 to 8.

10. The data recorder according to claim 9, wherein the storage board (14) comprises a VPX 6U board card (140) and a first solid state disk (141) and a second solid state disk (142) which are arranged on the VPX 6U board card (140), the second solid state disk (142) and the first solid state disk (141) are in one-to-one correspondence and are stacked on the upper portion of the corresponding first solid state disk (141), the first solid state disks (141) are grouped in pairs, the first solid state disks (141) in each group are arranged oppositely and have data ends connected with each other, so that the first solid state disks (141) in each group store data dispersedly, the second solid state disks (142) are grouped in pairs, the second solid state disks (142) in each group are arranged oppositely and have data ends connected with each other, so that the second solid state disks (142) in each group store data dispersedly, the first VPX connectors (4) of the storage board (14) and the data acquisition control board (13) are in one-to one correspondence, each first VPX connector (4) corresponds to at least 8 SATA3.0 interfaces, the first solid state disk (141) and the second solid state disk (142) are respectively at least 4 and correspond to the SATA3.0 interfaces one by one, and the data ends of the first solid state disk (141) and the second solid state disk (142) are respectively connected with the corresponding SATA3.0 interfaces through the corresponding first VPX connectors (4).