CN113970896A

CN113970896A - Control device based on FPGA chip and electronic equipment

Info

Publication number: CN113970896A
Application number: CN202111241976.4A
Authority: CN
Inventors: 吴帆; 罗昊; 宋杰; 庄浩然; 鲁晓风; 史兴晨
Original assignee: Shanghai Marine Diesel Engine Research Institute
Current assignee: Shanghai Marine Diesel Engine Research Institute
Priority date: 2021-10-25
Filing date: 2021-10-25
Publication date: 2022-01-25

Abstract

The invention discloses a control device and electronic equipment based on an FPGA chip, wherein the control device comprises: the device comprises an FPGA chip, a DDR memory, a Flash memory, a PCIe interface and an HDMI interface; the FPGA chip is a central processing unit of the control device and comprises a plurality of pairs of differential high-speed serial communication links and is respectively connected with a DDR memory, a Flash memory, a PCIe interface and an HDMI interface through the differential high-speed serial communication links; the DDR memory is used for caching data of the control device; the Flash memory is used for storing the configuration file of the FPGA chip; the PCIe interface is used for providing data transmission between the control device and an external upper computer; the HDMI interface is used for inputting/outputting video data. The scheme aims to improve the video processing capacity, enrich the video processing control function, improve the expandability of the control device and increase the application range of the control device.

Description

Control device based on FPGA chip and electronic equipment

Technical Field

The invention relates to the technical field of ship automation control, in particular to a control device based on an FPGA chip and electronic equipment.

Background

With the development of the industrial control field, the application of the industrial control field is more and more extensive, the control system is more and more complex, and the requirements on control precision, response speed and the like are gradually improved. The requirements for the control device mainly show that more data acquisition channels, higher sampling precision, faster operation speed, richer communication interfaces and the like are required.

The Field-editable Gate Array (FPGA chip for short) is used as a semi-custom Circuit chip in the Field of Application-Specific Integrated circuits (ASIC), abundant on-chip resources are available for development, the design mode is flexible and convenient, the defect that the custom Circuit cannot be upgraded is overcome, and the defect that the number of Gate circuits of the traditional Programmable device is limited is overcome. With the rise of video applications, higher requirements are put forward on the acquisition, transmission, processing and the like of video image signals, so that the FPGA chip plays an increasingly important role in the field of video processing control devices, and the corresponding video applications and services can remarkably improve the operation speed and efficiency by means of the support provided by the FPGA chip. Therefore, the method has wide application in the field of ship automation control.

In view of this, how to implement the function of enriching the video processing control function and improving the scalability of the control system while ensuring the conventional ship industrial automatic control function becomes an important research project for relevant researchers.

Disclosure of Invention

The present invention provides a control device and an electronic device based on an FPGA chip, and aims to improve video processing capability, enrich video processing control functions, improve expandability of the control device, and increase application range of the control device.

According to a first aspect of the present invention, an embodiment of the present invention provides a control device based on an FPGA chip, where the control device includes: the device comprises an FPGA chip, a DDR memory, a Flash memory, a PCIe interface and an HDMI interface; the FPGA chip is a central processing unit of the control device and comprises a plurality of pairs of differential high-speed serial communication links and is respectively connected with a DDR memory, a Flash memory, a PCIe interface and an HDMI interface through the differential high-speed serial communication links; the DDR memory is used for caching data of the control device; the Flash memory is used for storing the configuration file of the FPGA chip; the PCIe interface is used for providing data transmission between the control device and an external upper computer; the HDMI interface is used for inputting/outputting video data.

Optionally, in some embodiments, the FPGA chip includes a DDR controller, and the DDR controller is connected to the DDR memory through a DDR physical interface.

Optionally, in some embodiments, the DDR memory is a memory that employs the DDR3 protocol.

Optionally, in some embodiments, the FPGA chip includes a Flash controller, and the Flash controller is connected to the Flash memory by using an SPI protocol.

Optionally, in some embodiments, the FPGA chip comprises a PCIe controller; and the PCIe controller is connected with the PCIe interface through a SERDES physical interface.

Optionally, in some embodiments, the FPGA chip includes an HDMI controller, and the HDMI controller is connected to the HDMI interface through a multiplexer.

Optionally, in some embodiments, the multiplexer is directly connected to the HDMI interface, or the multiplexer is connected to the HDMI interface via an HDMI transceiver.

Optionally, in some embodiments, the control device comprises a USB interface; the USB interface is used for providing serial control input/output.

Optionally, in some embodiments, the FPGA chip includes a plurality of UART controllers, the FPGA chip is connected to the UART controllers through a low-speed bus, and each of the UART controllers is connected to the USB interface through a USB-to-UART chip.

Optionally, in some embodiments, the USB interface is a MINI B type interface.

Optionally, in some embodiments, the control device further comprises an ethernet interface; the ethernet interface is used to connect the control device with an external device.

Optionally, in some embodiments, the FPGA chip includes a plurality of ethernet controllers, the FPGA chip being connected to the ethernet controllers through a low speed bus; each Ethernet controller is connected with the Ethernet interface through an Ethernet physical chip.

Optionally, in some embodiments, the ethernet interface is an interface using RGMII protocol.

Optionally, in some embodiments, the control device further comprises a CAN bus interface; the CAN bus interface is used for connecting the control device with an external device through a CAN bus protocol.

Optionally, in some embodiments, the FPGA chip includes a plurality of CAN bus controllers, and the FPGA chip is connected with the CAN bus controllers through a low-speed bus; each CAN bus controller is connected with the CAN bus interface through a CAN bus isolation transceiver.

Optionally, in some embodiments, the control apparatus further comprises a JTAG interface; the JTAG interface is used for providing a debugging port of the control device.

Optionally, in some embodiments, the FPGA chip includes a JTAG controller, and the FPGA chip is connected to the JTAG controller through a low-speed bus; the JTAG controller is connected with the JTAG interface.

According to a second aspect of the present invention, an embodiment of the present invention provides an electronic device, which includes the control apparatus according to any embodiment of the present invention.

The control device and the electronic equipment based on the FPGA chip of the embodiment of the invention adopt the FPGA chip as a main control chip to realize the configurability and the expandability of the control device; the control device provided by the embodiment of the invention is a hardware structure, and based on further improvement, such as structural improvement, of the invention, the functions of the control device can be enriched, and the convenience of a system, especially the convenience of a video control system, is improved. In addition, the control device has multiple working modes, and can meet the requirements of different application scenes.

Drawings

The technical solution and other advantages of the present invention will become apparent from the following detailed description of specific embodiments of the present invention, which is to be read in connection with the accompanying drawings.

Fig. 1 is a schematic diagram of a control device based on an FPGA chip according to an embodiment of the present invention.

FIG. 2 is a diagram of an embodiment of the DDR memory of FIG. 1.

FIG. 3 is a schematic diagram of an embodiment of the Flash controller shown in FIG. 1.

FIG. 4 is a diagram of an embodiment of the PCIe controller shown in FIG. 1.

Fig. 5 is a schematic diagram of an embodiment of the HDMI interface shown in fig. 1.

FIG. 6 is a diagram of an embodiment of the USB interface shown in FIG. 1.

Fig. 7 is a schematic diagram of an embodiment of the ethernet interface shown in fig. 1.

Fig. 8 is a schematic diagram of an embodiment of the CAN bus interface shown in fig. 1.

FIG. 9 is a schematic diagram of an embodiment of the JTAG controller shown in FIG. 1

Fig. 10 is a schematic diagram of a bus arrangement in the control device shown in fig. 1.

Fig. 11 is a schematic structural diagram of the control device shown in fig. 1.

Fig. 12 is a schematic diagram of an electronic device according to an embodiment of the invention.

Detailed Description

The technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. It is to be understood that the described embodiments are merely exemplary of the invention, and not restrictive of the full scope of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; may be mechanically connected, may be electrically connected or may be in communication with each other; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.

Referring to fig. 1, fig. 1 is a schematic diagram of a control device based on an FPGA chip according to an embodiment of the present invention.

The embodiment of the present invention provides a control device 1000 based on an FPGA chip, where the control device 1000 includes: the FPGA chip 110, the DDR memory 120, the Flash memory 130, the PCIe interface 140 and the HDMI interface 150; the FPGA chip 110 is a central processing unit of the control device 1000, and is connected to the DDR memory 120, the Flash memory 130, a PCIe interface (i.e., PCIe connector, the same hereinafter) 140, and an HDMI interface (i.e., HDMI connector, the same hereinafter) 150, respectively; the DDR memory 120 is used for caching data of the control device 1000; the Flash memory 130 is used for storing a configuration file of the FPGA chip 110; the PCIe interface 140 is configured to provide data transmission between the control device 1000 and an external upper computer (not shown); the HDMI interface 150 is used to input/output video data.

The FPGA chip-based control device 1000 of the present invention uses the FPGA chip 110 as a main control chip to achieve configurability and expandability of the control device. Further, the control device 1000 can meet the requirements of different application scenarios by providing a plurality of different interfaces (or connectors) to have a plurality of operation modes.

The specific structure of the control device 1000 will be further described below with reference to other figures.

The FPGA chip 110 is a core chip of the control device 1000, and its programmable characteristics enable the control device 1000 to be configurable and expandable, thereby improving the expandability of the control device 1000 and increasing the application range of the control device.

Further, the FPGA chip 110 includes multiple pairs of differential high-speed serial communication links. In the present embodiment, the FPGA chip 110 includes 8 pairs of differential high-speed serial communication links, but in other embodiments, the number of differential high-speed serial communication links may not be limited thereto. The multiple pairs of differential high-speed serial communication link interfaces support the matched connection with multiple serial universal interconnection interface standards, such as USB interfaces, HDMI interfaces, PCIe interfaces and the like, and compared with the prior art in which a large number of parallel links are used, the number of the differential high-speed serial communication links used in the application is relatively small, so that the effects of saving I/O resources and reducing power consumption can be achieved, and the problems of transmission speed bottleneck and signal integrity caused by the use of parallel transmission in the prior art can be effectively solved. Specifically, at least one of the pairs of differential high-speed serial communication links is used for the DDR physical interface to which the DDR memory 120 is connected, and at least one of the other differential high-speed serial communication links is used for the PCIe interface and for the HDMI interface.

Referring to fig. 2, fig. 2 is a schematic diagram of the DDR memory 120 shown in fig. 1 according to an embodiment. In the present embodiment, the DDR memory 120 serves as a main data buffer of the control device 1000. The DDR memory 120 can also be referred to as a double data rate synchronous dynamic random access memory (DDR SDRAM, commonly referred to as DDR). The FPGA chip 110 includes a DDR controller 121, and the DDR controller 121 is connected to the DDR memory 120 through a DDR physical interface (including a DDR physical interface circuit). Further, the DDR memory 120 is a memory using DDR3(Double Data Rate 3, third generation Double Data Rate) protocol. It should be noted that, the DDR3 protocol is a new generation memory specification JESD79-3E (i.e., DDR3 memory specification) issued by JEDEC (Joint Electronic Devices Engineering Council), the DDR3 controller issues commands such as reset, read-write calibration, read-write operation, etc. to the DDR3 memory, and the DDR3 memory responds to the received commands according to the specification definition to complete the read-write operation of data. By using DDR memory supporting DDR3 protocol, the memory access bandwidth and memory capacity of the system can be increased.

Referring to fig. 3, fig. 3 is a schematic diagram of an embodiment of the Flash controller shown in fig. 1. In this embodiment, the Flash memory 130 is used for storing a configuration file of the FPGA chip 110 to meet the requirements of multiple operation modes of the control device. Further, the FPGA chip 110 includes a Flash controller 131, and the Flash controller 131 is connected to the Flash memory 130 by using an SPI protocol 132. The SPI (Serial Peripheral Interface) is a high-speed, full-duplex, synchronous communication bus protocol.

Referring to fig. 4, fig. 4 is a schematic diagram of an embodiment of the PCIe controller shown in fig. 1. In the embodiment, the PCIe interface 140 (or referred to as a PCIe connector) is used to realize high-speed transmission between the control apparatus 1000 and the upper computer. Further, the FPGA chip 110 includes a PCIe controller 141, and the PCIe controller 141 is connected to the PCIe interface 140 through a high-speed PCIe sers physical interface 142, so as to implement other layers required by the PCIe protocol. Wherein the SERDES physical interface 142 is a SERializer/DESerializer, a clock signal does not need to be transmitted by using the high-speed SERDES physical interface 142, and high-speed long-distance transmission can be realized by weighting and equalizing techniques.

Referring to fig. 5, fig. 5 is a schematic diagram of an embodiment of the HDMI interface shown in fig. 1. In the present embodiment, the HDMI interface 150 is used to input/output video data. Illustratively, the control device 1000 includes two HDMI interfaces (or HDMI connectors, hereinafter the same) (151, 152), video image data is input to the control device 1000 through one of the HDMI interfaces 151, and video output is realized through the other HDMI interface 152. Of course, the video image data can also be transmitted to the FPGA chip 110 through an ethernet interface described below, and the video output is realized through the HDMI interface (151, 152) described above after being processed by the FPGA chip 110, where the FPGA chip 110 is used to control the source of the video output to provide different video input services.

Further, HDMI interfaces (151, 152) as described above, wherein one HDMI interface 151 is for video input and the other HDMI interface 152 is for video output. Specifically, the FPGA chip 110 includes HDMI controllers (153, 154), and the HDMI controllers (153, 154) are connected to the HDMI interfaces (151, 152) through multiplexers (155, 156). In some embodiments, the multiplexer (155, 156) may be directly connected to the HDMI interface (151, 152), or the multiplexer (155, 156) may be indirectly connected to the HDMI interface (151, 152) through a corresponding HDMI transceiver (including HDMI receiver 157 or HDMI transmitter 158). When the HDMI interface 151 is used for video input, the multiplexer 155 can be connected to the HDMI interface 151 through the HDMI receiver 157. When HDMI interface 152 is used for video output, the multiplexer 156 may be connected to HDMI interface 152 through an HDMI transmitter 158. In addition, in the present embodiment, the HDMI interface (151, 152) adopts a TYPE a interface, which can reduce the space of the control board occupied by the HDMI interface (socket having the interface).

Referring to fig. 6, fig. 6 is a schematic diagram of an embodiment of the USB interface shown in fig. 1. In this embodiment, the control device 1000 further includes a USB interface (i.e., a USB connector, the same applies hereinafter) (161, 162). The USB interfaces (161, 162) are used for providing serial control input/output so as to further realize the input and output of control signals of the control device 1000. For example, the USB interface may enable access by a mouse or a keyboard, etc. The FPGA chip 110 comprises a plurality of UART controllers (163 and 164), the FPGA chip 110 is connected with the UART controllers (163 and 164) through low-speed buses, and each UART controller (163 and 164) is connected with the USB interfaces (161 and 162) through a USB-to-UART chip (165 and 166). Optionally, in some embodiments, the USB interface (161, 162) is a MINI B type interface, so that the space occupied by the USB interface (the socket with the interface) on the control board can be reduced.

Referring to fig. 7, fig. 7 is a schematic diagram of an embodiment of the ethernet interface shown in fig. 1. In this embodiment, the control device 1000 further includes ethernet interfaces (i.e., ethernet connectors, the same applies hereinafter) (171, 172). The Ethernet interfaces (171, 172) are used for connecting the control device 1000 with external devices. Illustratively, the control device 1000 includes two ethernet interfaces (171, 172). High-speed interconnection of the control device 1000 with external devices can be achieved through the two ethernet interfaces (171, 172).

Further, the FPGA chip 110 includes a plurality of ethernet controllers (173, 174), and the FPGA chip 110 is connected to the ethernet controllers (173, 174) through a low-speed bus. Each of the ethernet controllers (173, 174) is individually connected to the ethernet interface (171, 172) by an ethernet physical chip (i.e., ethernet PHY chip) (175, 176). Optionally, in some embodiments, the ethernet interface (171, 172) is an interface using RGMII protocol. It should be noted that RGMII (Reduced Gigabit Media Independent interface) is Reduced GMII (Gigabit Media Independent interface). The RGMII adopts a 4-bit data interface, the working clock is 125MHz, and data is transmitted simultaneously on the rising edge and the falling edge, so the transmission rate can reach 1000Mbps, and the requirement of high-speed interconnection is met.

Referring to fig. 8, fig. 8 is a schematic diagram of an embodiment of the CAN bus interface shown in fig. 1. The control device 1000 further comprises a CAN bus interface (i.e. CAN bus connector) (181, 182). The CAN bus interfaces (181, 182) are used for connecting the control device 1000 with external devices by a CAN bus protocol.

Further, the FPGA chip 110 includes a plurality of CAN bus controllers (183, 184), and the FPGA chip 110 is connected to the CAN bus controllers (183, 184) through a low-speed bus; each of the CAN bus controllers (183, 184) is connected to the CAN bus interface (181, 182) by a CAN bus isolation transceiver (185, 186). Illustratively, the number of the CAN bus controllers is two, and each CAN bus controller is connected with the CAN bus interface through a CAN bus isolation transceiver. The CAN bus isolation transceivers (185, 186) adopt independent chips to realize level conversion.

Referring to FIG. 9, FIG. 9 is a schematic diagram of an embodiment of the JTAG controller shown in FIG. 1. The control device 1000 also includes a JTAG interface (i.e., JTAG connector) 191. The JTAG interface 191 is used for providing a debugging port of the control device 1000. In this embodiment, the JTAG interface 191 employs a 10-pin JTAG interface.

Further, the FPGA chip 110 includes a JTAG controller 192, and the FPGA chip 110 is connected to the JTAG controller 192 through a low-speed bus; the JTAG controller 192 is connected to the JTAG interface 191.

The control device 1000 of the present invention has a plurality of operation modes by designing the different interfaces or memories, so as to meet the requirements of different application scenarios. The skilled in the art can design a plurality of USB interfaces and HDMI interfaces according to practical requirements, which is helpful for inputting a plurality of video image data, so as to meet the requirement of an individual user to acquire a plurality of different video images, thereby further improving the processing capability of complex video image data.

In the present embodiment, the FPGA chip 110 includes a central processing unit CPU therein, and the central processing unit CPU is connected to the DDR memory 120, the Flash memory 130, the PCIe interface 140, the HDMI interfaces (151, 152), the ethernet interfaces (171, 172), the USB interfaces (161, 162), and the CAN bus interfaces (181, 182) through a bus.

Furthermore, the central processing unit adopts RISCV instructions, and the system bus adopts AMBA2.0 protocol. The amba (advanced Microcontroller Bus architecture) Bus is an open on-chip Bus standard proposed by ARM corporation, and has the characteristics of high speed, low power consumption and the like. The AMBA protocol comprises an AHB, an ASB and an APB, wherein the AHB is an Advanced High-performance Bus and is used for a High-performance and High-clock working frequency module; ASB (Advanced System Bus) used for high-performance System modules; the APB is Advanced Peripheral Bus, and is used for the slow Peripheral module.

Referring to fig. 1 and 10, fig. 10 is a schematic diagram of a bus arrangement in the control device shown in fig. 1. The DDR controller 120, PCIe controller 141, HDMI controller (153, 154) and ethernet controller (173, 174) are connected to the high speed bus (i.e., AHB/ASB), while the CAN bus controller (183, 184), the URART controller (163, 164), the Flash controller 130 (which passes through SPI132) and JTAG controller 192 are connected to the low speed bus (i.e., APB). It should be noted that the differential high-speed serial communication link includes not only a high-speed bus but also a low-speed bus.

In addition, the control device 1000 further includes a GPIO interface 196, as shown in fig. 1, the GPIO interface 196 is used for other extension connections, and the GPIO interface 196 directly outputs through the FPGA chip 110, so as to further enrich the video processing control function and improve the scalability of the control device.

In this embodiment, the control device 1000 further includes a power supply unit 195, and the power supply unit 195 is used for supplying power to the components of the control device 1000.

Referring to fig. 11, fig. 11 is a schematic structural diagram of the control device shown in fig. 1. The front panel 210 of the control device 1000 of the present embodiment may mount a USB interface, an HDMI interface, and an ethernet interface, and the rear panel 220 of the control device 1000 may mount a PCIe interface and a CAN bus interface. With such a design, the convenience of the control device 1000 can be improved, and especially, the external device needs to be connected to the control device 1000 through a USB interface, an HDMI interface or an ethernet interface to provide the related video image data to the control device 1000.

An example of video processing by the control device 1000 will be described below.

The video image data is input to the control apparatus 1000 through one HDMI interface of the control apparatus 1000. The control device 1000 may transmit the video image data to the upper computer or other control device through the PCIe interface 140 or through the ethernet interface, and perform image processing with complicated operations by the upper computer or other control device. When the requirement of the video image data processing is not particularly complex, the video image data processing can be completed inside the FPGA chip 110, and the video image data does not need to be sent to the outside of the FPGA chip 110. The DDR memory 120 is used to store intermediate data for video image data processing. When the processed video image data is returned to the control device 1000, display can be performed through another HDMI interface.

Meanwhile, the two USB interfaces are respectively connected with a mouse and a keyboard and used for controlling the operation of the display of the HDMI interface. The control device 1000 may be directly connected to other devices through a CAN bus to implement control communication. In addition, the SoC system programming program in the FPGA chip is solidified in the Flash memory 130, and the JTAG interface provides a debugging interface of the FPGA chip.

Referring to fig. 12, fig. 12 is a schematic view of an electronic device according to an embodiment of the invention. An embodiment of the present invention provides an electronic device 5000, which includes the control apparatus 1000 according to any one of the above embodiments of the present invention. The electronic device has the same concept as the control device provided in the above embodiment, the control device provided in the above embodiment is used for being disposed in the electronic device and for implementing video image data processing, and other structures of the electronic device may refer to the structure in the prior art, and are not described herein again.

When the electronic equipment adopts the FPGA chip as a main control chip, the configurability and the expandability of the electronic equipment can be improved; the electronic device provided by the embodiment of the invention is a hardware structure, and a person skilled in the art can select the hardware structure according to actual needs, and further improve the structure (for example, add a plurality of functional interfaces) so as to provide a plurality of different functions and improve the convenience of the system, especially the convenience of a video control system. In addition, the electronic equipment has multiple working modes and can meet the requirements of different current application scenes.

In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.

The control device and the electronic device based on the FPGA chip provided by the embodiment of the present invention are described in detail above, a specific example is applied in the description to explain the principle and the implementation of the present invention, and the description of the above embodiment is only used to help understanding the technical scheme and the core idea of the present invention; those of ordinary skill in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.

Claims

1. The utility model provides a controlling means based on FPGA chip which characterized in that includes: the device comprises an FPGA chip, a DDR memory, a Flash memory, a PCIe interface and an HDMI interface; the FPGA chip is a central processing unit of the control device and comprises a plurality of pairs of differential high-speed serial communication links and is respectively connected with a DDR memory, a Flash memory, a PCIe interface and an HDMI interface through the differential high-speed serial communication links; the DDR memory is used for caching data of the control device; the Flash memory is used for storing the configuration file of the FPGA chip; the PCIe interface is used for providing data transmission between the control device and an external upper computer; the HDMI interface is used for inputting/outputting video data.

2. The control device of claim 1, wherein the FPGA chip comprises a DDR controller, and the DDR controller is connected with the DDR memory through a DDR physical interface.

3. The control device according to claim 1 or 2, wherein the DDR memory is a memory using DDR3 protocol.

4. The control device of claim 1, wherein the FPGA chip comprises a Flash controller, and the Flash controller is connected to the Flash memory using an SPI protocol.

5. The control device of claim 1, wherein the FPGA chip comprises a PCIe controller; and the PCIe controller is connected with the PCIe interface through a SERDES physical interface.

6. The control device of claim 1, wherein the FPGA chip comprises an HDMI controller, the HDMI controller being connected to the HDMI interface through a multiplexer.

7. The control device of claim 6, wherein the multiplexer is directly connected to the HDMI interface, or wherein the multiplexer is connected to the HDMI interface via an HDMI transceiver.

8. The control device of claim 1, wherein the control device comprises a USB interface; the USB interface is used for providing serial control input/output.

9. The control device of claim 8, wherein the FPGA chip comprises a plurality of UART controllers, the FPGA chip is connected to the UART controllers through a low-speed bus, and each of the UART controllers is connected to the USB interface through a USB-to-UART chip.

10. The control device according to claim 8 or 9, wherein the USB interface is a MINI B type interface.

11. The control device of claim 1, further comprising an ethernet interface; the ethernet interface is used to connect the control device with an external device.

12. The control device of claim 11, wherein the FPGA chip comprises a plurality of ethernet controllers, the FPGA chip being connected to the ethernet controllers via a low speed bus; each Ethernet controller is connected with the Ethernet interface through an Ethernet physical chip.

13. Control arrangement according to claim 11 or 12, characterized in that the ethernet interface is an interface using RGMII protocol.

14. The control device of claim 1, further comprising a CAN bus interface; the CAN bus interface is used for connecting the control device with an external device through a CAN bus protocol.

15. The control device of claim 14, wherein the FPGA chip includes a plurality of CAN bus controllers, the FPGA chip being connected to the CAN bus controllers via a low speed bus; each CAN bus controller is connected with the CAN bus interface through a CAN bus isolation transceiver.

16. The control apparatus of claim 1, further comprising a JTAG interface; the JTAG interface is used for providing a debugging port of the control device.

17. The control device of claim 16, wherein the FPGA chip includes a JTAG controller, the FPGA chip being connected to the JTAG controller via a low speed bus; the JTAG controller is connected with the JTAG interface.

18. An electronic device, characterized in that it comprises a control device according to any one of claims 1 to 17.