CN114840885A - Intelligent destruction method for storage mainboard based on sailing platform and RAID technology - Google Patents
Intelligent destruction method for storage mainboard based on sailing platform and RAID technology Download PDFInfo
- Publication number
- CN114840885A CN114840885A CN202210376748.6A CN202210376748A CN114840885A CN 114840885 A CN114840885 A CN 114840885A CN 202210376748 A CN202210376748 A CN 202210376748A CN 114840885 A CN114840885 A CN 114840885A
- Authority
- CN
- China
- Prior art keywords
- sailing
- storage
- embedded
- intelligent
- embedded memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000003860 storage Methods 0.000 title claims abstract description 71
- 230000006378 damage Effects 0.000 title claims abstract description 50
- 238000000034 method Methods 0.000 title claims abstract description 37
- 238000005516 engineering process Methods 0.000 title claims abstract description 35
- 230000015654 memory Effects 0.000 claims abstract description 45
- 238000012544 monitoring process Methods 0.000 claims abstract description 4
- 238000012545 processing Methods 0.000 claims description 6
- 230000001960 triggered effect Effects 0.000 claims description 4
- 230000006870 function Effects 0.000 description 19
- 230000001351 cycling effect Effects 0.000 description 7
- 238000010586 diagram Methods 0.000 description 7
- 238000006243 chemical reaction Methods 0.000 description 6
- 230000008569 process Effects 0.000 description 5
- 101100205847 Mus musculus Srst gene Proteins 0.000 description 4
- 238000012536 packaging technology Methods 0.000 description 4
- 238000013500 data storage Methods 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 230000017525 heat dissipation Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000035939 shock Effects 0.000 description 2
- 239000007787 solid Substances 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- 230000009471 action Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000008187 granular material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
- G06F21/78—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data
- G06F21/79—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data in semiconductor storage media, e.g. directly-addressable memories
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
- G06F11/0727—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment in a storage system, e.g. in a DASD or network based storage system
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0751—Error or fault detection not based on redundancy
- G06F11/0754—Error or fault detection not based on redundancy by exceeding limits
- G06F11/0757—Error or fault detection not based on redundancy by exceeding limits by exceeding a time limit, i.e. time-out, e.g. watchdogs
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Quality & Reliability (AREA)
- Computer Security & Cryptography (AREA)
- Computer Hardware Design (AREA)
- Software Systems (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Abstract
The invention provides an intelligent destroying method of a storage mainboard based on a sailing platform and RAID technology, which comprises a sailing processor and an RAID module, wherein the RAID module comprises a plurality of embedded storage chips which are pasted on the sailing platform, the sailing processor comprises an RAID algorithm, the embedded storage chips store data according to the RAID algorithm, and the intelligent destroying method comprises the following steps: a plurality of embedded memory chips receive the destruction signal; monitoring the duration of the destruction signal by a plurality of embedded memory chips; the embedded memory chips judge whether the duration time meets preset time or not; if the duration time meets the preset time, determining to enter an erasing execution state, and erasing the stored data based on the erasing execution state; judging whether the erasing operation is finished or not according to a preset judgment condition; and entering a standby state if the erasing operation is determined to be finished. The invention effectively ensures the data security of the large-capacity storage mainboard.
Description
[ technical field ] A method for producing a semiconductor device
The invention relates to the technical field of storage equipment, in particular to an intelligent destroying method for a storage mainboard based on a sailing platform and an RAID technology.
[ background of the invention ]
With the development of information technology, the demand of large data storage in the information age is also increased. In the storage industry, market demands are diverse.
ZYNQ (All called Zynq-7000 All Programmable SoC), is a new generation of fully Programmable system on chip from Xilinx. ZYNQ combines a dual core ARM Cortex-a9 processor and a conventional Field Programmable Gate Array (FPGA) logic.
An FPGA (Field Programmable Gate Array) device belongs to a semi-custom circuit in the Field of Application Specific Integrated Circuits (ASICs), is a Programmable logic Array, not only solves the defects of the custom circuit, but also overcomes the defect of limited Gate circuit number of the original Programmable device.
RAID (Redundant Array of Independent Disks, simply referred to as a disk Array) is a technology that combines a plurality of Independent hard Disks (physical hard Disks) in different ways to form a hard disk group (logical hard disk), thereby providing higher storage performance than a single hard disk and providing data redundancy. Currently, RAID technology is widely used in various situations of data storage.
RAID techniques are divided into hard RAID and soft RAID. In the hard RAID, a system CPU and a north bridge (in some cases, the north bridge is not included) are hung with a plurality of memories through a RAID controller, and the CPU in the RAID controller calculates each strip check data stored in the storage space of the memories; the soft RAID does not have a RAID controller, but the system CPU and the north bridge (in some cases, the north bridge may not be included) directly hang the memory, the memory is divided into a plurality of storage spaces, and the system CPU calculates the check data of each band in the plurality of storage spaces divided in the memory.
In the related technology of soft RAID, the memory that hangs down generally adopts standard solid state disk, and therefore an external connector is required to be switched with the standard solid state disk, so that the layout space becomes large, the heat dissipation performance is poor, the shock resistance is poor, and the requirements for large-capacity storage and rapid storage of data in the information age cannot be met. And along with the increase of storage capacity, when the saint processor is attacked, the security of self data can not be guaranteed, and the risk of data leakage is increased.
Therefore, there is a need to provide a new method for intelligently destroying a storage motherboard based on a sailing platform and RAID technology to solve the above technical problems.
[ summary of the invention ]
The invention aims to provide an intelligent destroying method for a storage mainboard based on a sailing platform and RAID technology, which can provide data security, so as to solve the problems in the related technology.
In order to achieve the above object, the present invention provides an intelligent destruction method for a storage motherboard based on a sailing platform and a RAID technology, where the storage motherboard based on the sailing platform and the RAID technology includes a sailing processor and a RAID module, the RAID module includes a plurality of embedded storage chips attached to the sailing platform, the sailing processor includes a RAID algorithm, and the embedded storage chips store data according to the RAID algorithm, and the intelligent destruction method includes the steps of: firstly, the embedded memory chips receive destruction signals; secondly, monitoring the duration time of the destruction signal by the embedded memory chips; thirdly, judging whether the duration time meets the preset time or not by the embedded memory chips; step four, if the duration time meets the preset time, determining to enter an erasing execution state, and erasing the stored data based on the erasing execution state; fifthly, judging whether the erasing operation is finished or not according to preset judgment conditions; and sixthly, entering a standby state if the erasing operation is determined to be finished.
Preferably, in the first step, the destroying signal is sent to the embedded memory chip by the sailing shoe processor.
Preferably, the storage mainboard based on the sailing platform and the RAID technology further includes an intelligent destruction socket connected to the embedded storage chip, and in the first step, the destruction signal is sent to the embedded storage chip by short-circuiting the intelligent destruction socket.
Preferably, in the fourth step, when the embedded memory chip is in the erase execution state, if any control signal of the sailing processor is received, the embedded memory chip enters a fault processing state from the erase execution state; any one of the control signals is used for indicating the embedded memory chip to enter a corresponding task execution state; the embedded memory chip generates an error signal responding to any control signal and returns the error signal to the sailing processor, and the error signal is used for indicating that the embedded memory chip fails to enter a corresponding task execution state; and after the error signal is sent, the embedded memory chip enters the erasing execution state from the fault processing state so as to continue the erasing operation.
Preferably, in the fourth step, when the embedded memory chip is in the erase execution state, if a power cycling signal is received, entering an erase pause state from the erase execution state, where the power cycling signal is used to instruct the embedded memory chip to execute a power cycling operation; the embedded memory chip executes power supply cycle operation according to the power supply cycle signal; and when the power supply cycle operation is finished, the embedded memory chip enters the erasing execution state from the erasing pause state so as to continue the erasing operation.
More preferably, embedded memory chip includes encapsulates in its inside control module, flash memory module, buffer memory module and interface module through BGA technique, control module includes bus controller, microprocessor and DMA controller, flash memory module includes flash memory controller, flash memory chip, buffer memory module includes DRAM controller, DDR3 buffer memory, interface module includes SATA interface, UART interface.
More preferably, the sailing processor comprises 8 signal channels, and the number of the embedded memory chips is 2, 4, 6 or 8.
Preferably, the embedded memory chip comprises a QE pin, and when the QE pin is at a low level, intelligent destruction is triggered.
Preferably, the storage motherboard based on the sailing platform and the RAID technology further comprises a power supply module for supplying power to the embedded storage chip.
Preferably, the power supply module includes a voltage timing control circuit, which can output a first voltage to the control module, a second voltage to the flash memory module, a third voltage to the cache module, and a fourth voltage to the interface module according to a preset power-on timing.
The invention has the technical effects that: based on the sailing platform, the large-capacity expansion is realized, the occupied space of the embedded memory chip is small, the anti-seismic performance is good, and the data safety can be ensured along with the increase of the memory capacity.
[ description of the drawings ]
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments are briefly introduced below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without inventive efforts, wherein:
FIG. 1 is a schematic structural diagram of a storage motherboard based on a sailing platform and RAID technology according to the present invention;
FIG. 2 is a schematic step diagram of an intelligent destruction method for a storage motherboard based on a sailing platform and RAID technology according to the present invention;
FIG. 3 is a flowchart of an embodiment of the intelligent destruction method for a storage motherboard based on a sailing platform and RAID technology according to the present invention
FIG. 4 is a schematic diagram of the structure of the embedded chip of the present invention;
FIG. 5 is a schematic structural diagram of an embodiment of an embedded chip of the present invention;
FIG. 6 is a flow chart of the memory motherboard of the present invention;
fig. 7 is a schematic structural diagram of an intelligent destruction socket of the storage motherboard according to the present invention;
FIG. 8 is a schematic diagram of internal pins of the embedded chip shown in FIG. 4;
FIG. 9 is a pin view of the BGA package of FIG. 7;
fig. 10 is a circuit diagram of the voltage timing control of the power supply module of the present invention.
[ detailed description ] embodiments
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1 and 2, the present invention relates to an intelligent destruction method for a storage motherboard based on a sailing platform and a RAID technology, wherein the storage motherboard 100 based on the sailing platform and the RAID technology includes a sailing processor 1 and a RAID module, the RAID module includes a plurality of embedded storage chips 2 attached to the sailing platform, the sailing processor 1 includes a RAID algorithm, the embedded storage chips 2 store data according to the RAID algorithm, and the intelligent destruction method includes the steps of:
firstly, a plurality of embedded memory chips 2 receive a destruction signal;
secondly, monitoring the duration of the destruction signal by a plurality of embedded memory chips 2;
thirdly, judging whether the duration time meets the preset time by a plurality of embedded memory chips 2;
step four, if the duration time meets the preset time, determining to enter an erasing execution state, and erasing the stored data based on the erasing execution state;
fifthly, judging whether the erasing operation is finished or not according to preset judgment conditions;
and sixthly, entering a standby state if the erasing operation is determined to be finished.
In the first step, the saint processor 1 may send a destruction signal to the embedded memory chip 2, where the destruction signal is a low level signal.
In the first step, the intelligent destruction extension socket 4 connected with the embedded memory chip 2 may also be arranged on the saint platform, as shown in fig. 7, the intelligent destruction extension socket 4 is short-circuited to send a destruction signal to the embedded memory chip 2.
In the third step, in order to improve the efficiency of the intelligent destruction, the preset time is preferably one second, and is used for determining whether to perform an erasing operation, that is, the intelligent destruction function is triggered when the duration of the low level signal is one second.
In the sixth step, after the erasing operation is completed, the embedded memory chip 2 becomes the initialization state, i.e. enters the standby state, so as to continue to receive data for storage.
In the fourth step, when the embedded memory chip 2 is in the erasing execution state, if any control signal of the sailing processor 1 is received, the embedded memory chip enters the fault processing state from the erasing execution state; any one of the control signals is used for indicating the embedded memory chip 2 to enter a corresponding task execution state; the embedded memory chip 2 generates an error signal responding to any one of the control signals and returns the error signal to the sailing processor 1, and the error signal is used for indicating that the embedded memory chip 2 fails to enter the corresponding task execution state. After the error signal is sent, the embedded memory chip 2 enters an erase execution state from a failure processing state to continue the erase operation.
In order to improve the security of data, the embedded memory chip 2 sets the erase execution state to the highest level. When the embedded memory chip 2 is in the erase execution state, any processor sending control signals will not be executed. At this time, the embedded memory chip 2 enters a fault handling state, an error signal is generated in the fault handling state and returned to the processor, and the erasing operation is continuously performed after the error signal is returned, so that the stored data are completely erased.
In the fourth step, when the embedded memory chip 2 is in the erase execution state, if a power cycle signal is received, the embedded memory chip 2 enters the erase suspend state from the erase execution state, and the power cycle signal is used for instructing the embedded memory chip 2 to execute the power cycle operation. The embedded memory chip 2 executes power cycling operation according to the power cycling signal. After the power cycling operation is completed, the embedded memory chip 2 enters an erase execution state from an erase pause state to continue the erase operation.
In order to ensure the smooth execution of the erasing operation, a power supply circulation function is configured in the embedded memory chip 2, and when the power consumption of the embedded memory chip 2 is insufficient, the embedded memory chip 2 is supplied with power in time. When the embedded memory chip 2 starts the power circulation function, a power circulation signal or a power circulation instruction is received. At this time, the erase execution state is suspended, the erase suspended state is entered, and after the power cycling operation is completed, the erase execution state is re-entered from the erase suspended state to continue the erase operation.
The saint processor 1 includes a DMA controller (Direct Memory access controller). The DMA controller has 8 signal channels. Each signal channel comprises a first differential signal pin group, the embedded memory chip 2 comprises a second differential signal pin group corresponding to the embedded memory chip, and the first differential signal pin group and the second differential signal pin group are electrically connected to establish the signal channel.
In the present embodiment, the number of the embedded memory chips 2 is 8, but in other embodiments, the number of the embedded memory chips 2 may also be 2, 4, or 6.
The embedded memory chip 2 further comprises a QE pin, namely a quick erase pin, and intelligent destruction can be triggered when the QE pin is at a low level.
In this embodiment, the RAID algorithm is at RAID1 level, that is, when data is written into one embedded storage chip, an image file is generated on another embedded storage chip, as long as at least one embedded storage chip in any pair of image disks can be used, and even when half of the number of embedded storage chips have a problem, the system can operate normally. By the design, the reliability and the repairability of the system can be guaranteed to the maximum extent without affecting the performance.
In other embodiments, however, other levels may be used for RAID algorithms, such as RAID2, RAID3, RAID4, and so on.
The intelligent destroying method can ensure that the plurality of embedded memory chips 2 simultaneously realize the intelligent destroying function, and can effectively protect the data security.
As shown in fig. 3, in this embodiment, the embedded memory chip 2 implements a flow chart of the intelligent destruction function. The specific description is as follows.
Before the embedded memory chip 2 starts the intelligent destruction function, the state is QE0, QE 0: device _ IDLE: when the embedded memory chip 2 is successfully powered on or any command is successfully executed, the embedded memory chip 2 enters the state after completing the initialization process, and the QE1 state is also referred to as a standby state.
Conversion QE 0: QE1 procedure: when the embedded memory chip 2 detects QEE set for at least 1 second, the device should switch to QE 1: quick _ Erase _ Execute. QEE are used to monitor the duration of the low level.
QE 1: quick _ Erase _ Execute state: QE1 is the erase execution state, entered when QEE-was asserted for the last 1 second. In the erasing execution state, the embedded storage chip starts to search for the storage data in all the data blocks and then erases the storage data. When the erase execution state is entered QEB-asserted by the device, QEB is used to determine if the erase operation is complete.
Conversion QE 1: QE1 procedure: in the suspend state, when power is cycled, the embedded memory chip 2 should continue the erase process after the initialization process is completed.
Conversion QE 1: QE2 procedure: when all data blocks are successfully erased, the embedded memory chip 2 should switch to QE 2: quick _ Erase _ Finish.
Conversion QE 1: QE3 procedure: when any command is issued by the saint processor or other processor in the erase execution state, the command may be understood as a control signal, and the embedded memory chip 2 should be converted to QE 3: command _ Error, failure handling status.
QE 2: quick _ Erase _ Finish state: to erase the end state, the state is entered after all data blocks have been successfully erased. When this state is entered, QEB will be cancelled by the embedded memory chip.
Conversion QE 2: QE0 procedure: after all data blocks are erased, the embedded memory chip 2 should be converted to QE 0: device _ IDLE state.
QE 3: command _ Error status: when the sailing processor 1 sends any command through the connected control pin or HRST/SRST command sent by CF/PATA hard disk equipment through the parallel port or SRST/COMREST command sent by SATA hard disk equipment through the serial port, if the embedded memory chip 2 is in the erasing execution state of erasing all data blocks, the embedded memory chip 2 enters the pause state, the erasing process is regarded as the highest priority, and the ABRT is used for returning the ERR state (fault state) to the sailing processor, wherein the ABRT is a stop signal.
Conversion QE 3: QE 1: when the ERR state is returned, the embedded memory chip should continue to perform the erase process and transition to QE 1: quick _ Erase _ Execute.
The embedded memory chip 2 needs to pay attention to when the intelligent destruction function is started:
(1) before the embedded memory chip 2 executes the intelligent destroying function, the program of the erasing function is led into the embedded memory chip through the MPtool, and the embedded memory chip 2 is set not to enter the sleep mode all the time when the erasing function is realized. The MPtool can perform formatting, mass production and other operations on the storage device.
(2) The erase function of the embedded memory chip 2 has the highest priority, so in this state, the embedded memory chip 2 does not stop executing the erase function when receiving any command from any processor, including a command directly transmitted through the saint processor 1, an HRST/SRST command transmitted through the parallel port of the CF/PATA hard disk device, and an SRST/COMREST command transmitted through the serial port of the SATA hard disk device. The serial port and the parallel port are input and output modules.
(3) If the pin QEE-is controlled by a GPIO (General-purpose input/output) pin of the sailing processor 1, the embedded memory chip 2 enters an idle state and activates the pin QEE for at least 1 second to perform an erase function, and the idle state can be understood as a standby state.
(4) If pin QEE-is manually controlled, e.g., the pin is inadvertently pressed, etc., pin QEE-is activated for at least 3 seconds to enter into performing the erase function.
(5) The busy time to erase all data blocks depends on the flash configuration:
busy time ═ erase time block number) + (program time block number) + (cleaning vs. time now logarithmically). The erasing time is the erasing time of a single data block tested in advance; the block number is the number of the data block which needs to be erased currently; the program time is the time for starting an erasing function program when each data block is erased; clean pair time is the time at which each data pair is erased; the number of the matching pairs is the number of the existing data pairs in the embedded memory chip, the data pairs comprise a plurality of data blocks, and some data need to be stored by the plurality of data blocks when the data are stored to form the data pairs.
In this embodiment, the busy time of the erasing function can be controlled to be at least five seconds, so as to improve the erasing efficiency.
(6) And state description:
after the intelligent destruction is completed, the lba (logical Block address) logical Block address of the embedded memory chip 2 is all 0, and a WinHex tool may be used to check whether the embedded memory chip is completely destroyed, so as to ensure that the embedded memory chip 2 cannot be recovered after being destroyed and returns to an unused (before factory shipment) state. The WinHex tool is used for checking and repairing various files, recovering deleted files, data loss caused by hard disk damage and the like.
(7) Before realizing intelligent destruction function, weld the GPIO interface pin of sailing platform and the QE pin of embedded memory chip, sailing treater provides the destruction signal for embedded chip through GPIO interface pin, set up to satisfy the low level for the QE pin and effectively just can trigger intelligent destruction function, even also can erase all previous storage data during power cycle, and equipment can continue to be used for storage data and reformatted by the host computer after the function is accomplished.
As shown in fig. 4, the embedded memory chip 2 includes a control module 21, a flash memory module 22, a cache module 23, and an interface module 24. The control module 21, the flash memory module 22, the cache module 23 and the interface module 24 are packaged inside the embedded memory chip 2 by BGA technology.
The bga (ball Grid array) packaging technology is a ball Grid array packaging technology, which is a high-density surface mount packaging technology. The embedded memory chip adopting the BGA packaging technology has smaller volume, faster and more effective heat radiation performance and electrical performance under the same capacity.
As shown in fig. 5, in the present embodiment, the control module includes a bus controller, a microprocessor, and a DMA controller, the flash memory module includes a flash memory controller, a flash memory chip array, and the cache module includes a DRAM controller and a DDR3 cache. The interface module comprises a SATA interface and a UART interface. The embedded memory chip also includes a secure encoder/decoder, a main system buffer, and JTAG.
The microprocessor is connected to the bus controller and JTAG. The bus controller is respectively connected with the safety encoder/decoder, the UART interface, the main system buffer, the DMA controller, the DRAM controller and the flash memory controller. The flash memory controller is connected with the flash memory chip array, the DRAM controller is connected with the DDR3 cache, and the safety encoder/decoder is connected with the SATA interface.
JTAG is Joint Test Action Group, which is used for chip internal Test. The UART interface is a Universal Asynchronous Receiver/Transmitter, namely a Universal Asynchronous Receiver/Transmitter, and is a serial communication interface. The SATA interface is Serial Advanced Technology Attachment, a Serial hardware driver interface based on industry standards.
As shown in fig. 6, the storage motherboard 100 based on the sailing platform and the RAID technology further includes a power supply module 3 for supplying power to the embedded storage chip 2.
The differential signal pin of the saint-si processor 1 is connected with the differential signal pin of the embedded memory chip 2 to form a signal channel, so that data can be transmitted between the saint-si processor 1 and the embedded memory chip 2.
The embedded memory chip 2 further includes a plurality of power pins, and the power pins are respectively connected to the control module 21, the memory module 22, the cache module 23, and the interface module 24.
The power supply module 3 outputs a first voltage, a second voltage, a third voltage and a fourth voltage to the control module 21, the storage module 22, the cache module 23 and the interface module 24, respectively.
As shown in fig. 8 to 10, in the present embodiment, it is preferable that the first voltage is 1.1V, the second voltage is 1.8V, the third voltage is 1.5V, and the fourth voltage is 3.3V.
The power supply module 3 further comprises a voltage sequence control circuit, which comprises a plurality of capacitors for time delay, and the voltage sequence control circuit can supply a first voltage, a second voltage, a third voltage and a fourth voltage to the embedded memory chip 2 according to a preset power-on sequence. If the timing sequence is correct, the disk can be identified, and if the timing sequence is incorrect, the disk cannot be identified.
The preset power-on time sequence is 1.1V >1.5V >1.8V >3.3V, namely the power-on time sequence is preset to be that the power-on of the voltage of 1.1V is earlier than the voltage of 1.5V, the power-on of the voltage of 1.5V is earlier than the voltage of 1.8V, and the power-on of the voltage of 1.8V is earlier than the voltage of 3.3V. If the preset power-on time sequence is not met, the situation that the disk cannot be identified occurs, namely the sailing processor 1 cannot identify the embedded memory chip 2. Through the design, the stability of the connection between the saint processor 1 and the embedded memory chip 2 is ensured, so that the saint processor 1 can normally read the data of the embedded memory chip 2. The voltage time sequence control circuit can ensure that an external power supply circuit can supply power to each module of the embedded memory chip according to a preset power-on time sequence, uniformly and effectively manages the power-on of each module of the embedded memory chip, effectively reduces the granules of a power supply grid at the moment when each module is powered on simultaneously, and ensures the stability and safety of power utilization.
In the present embodiment, the sailing processor 1 is used with model number XC7Z045-2FFFG900I, but is not limited thereto. The model of the embedded memory chip 2 is AS619GEE, which is a BGA packaged embedded memory chip that is independently developed by the applicant and integrates a NAND flash memory, a DRAM cache, and an independently developed controller, but is not limited thereto.
When the embedded memory chip 2 is mounted on the saints platform through the board, the size of the embedded memory chip 2 is 16X20mm, so that the layout space is greatly reduced, the heat dissipation performance is good, and the shock resistance is good because the embedded memory chip 2 is a BGA type package and the board is mounted on the saints platform.
In conclusion, the invention has the following beneficial effects: based on the Sailing platform, the high-capacity expansion is realized, the occupied space of the embedded memory chip is small, the anti-seismic performance is good, and along with the increase of the memory capacity, when the Sailing processor is attacked, the safety of data can be ensured.
Finally, it should be noted that: the above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not necessarily depart from the spirit and scope of the corresponding technical solutions.
Claims (10)
1. The intelligent destroying method for the storage mainboard based on the sailing platform and the RAID technology is characterized in that the storage mainboard based on the sailing platform and the RAID technology comprises a sailing processor and an RAID module, the RAID module comprises a plurality of embedded storage chips pasted to the sailing platform, the sailing processor comprises an RAID algorithm, the embedded storage chips store data according to the RAID algorithm, and the intelligent destroying method comprises the following steps: firstly, the embedded memory chips receive destruction signals;
secondly, monitoring the duration time of the destruction signal by the embedded memory chips;
thirdly, judging whether the duration time meets the preset time or not by the embedded memory chips;
step four, if the duration time meets the preset time, determining to enter an erasing execution state, and erasing the stored data based on the erasing execution state;
fifthly, judging whether the erasing operation is finished or not according to preset judgment conditions;
and sixthly, entering a standby state if the erasing operation is determined to be finished.
2. The intelligent destruction method for the storage motherboard based on the sailing platform and the RAID technology according to claim 1, wherein in the first step, the sailing processor sends the destruction signal to the embedded storage chip.
3. The intelligent destruction method for the storage mainboard based on the sailing platform and the RAID technology as claimed in claim 1, wherein the storage mainboard based on the sailing platform and the RAID technology further comprises an intelligent destruction socket connected with the embedded storage chip, and in the first step, the destruction signal is sent to the embedded storage chip by short-circuiting the intelligent destruction socket.
4. The intelligent destruction method for a storage motherboard based on a sailing platform and a RAID technology according to claim 2, wherein in the fourth step, when the embedded memory chip is in the erase execution state, if any one of the control signals of the sailing processor is received, the embedded memory chip enters a fault processing state from the erase execution state; any one of the control signals is used for indicating the embedded memory chip to enter a corresponding task execution state; the embedded memory chip generates an error signal responding to any control signal and returns the error signal to the sailing processor, and the error signal is used for indicating that the embedded memory chip fails to enter a corresponding task execution state; and after the error signal is sent, the embedded memory chip enters the erasing execution state from the fault processing state so as to continue the erasing operation.
5. The intelligent destruction method for a storage motherboard based on a sailing platform and a RAID technology according to claim 2, wherein in the fourth step, when the embedded storage chip is in the erase execution state, if a power cycle signal is received, an erase pause state is entered from the erase execution state, and the power cycle signal is used to instruct the embedded storage chip to execute a power cycle operation; the embedded memory chip executes power supply cycle operation according to the power supply cycle signal; and when the power supply cycle operation is completed, the embedded memory chip enters the erasing execution state from the erasing pause state so as to continue the erasing operation.
6. The method as claimed in claim 1, 2 or 5, wherein the embedded memory chip includes a control module, a flash memory module, a cache module and an interface module, the control module includes a bus controller, a microprocessor and a DMA controller, the flash memory module includes a flash memory controller and a flash memory chip, the cache module includes a DRAM controller and a DDR3 cache, and the interface module includes a SATA interface and a UART interface.
7. The intelligent destruction method for a storage motherboard based on a sailing platform and a RAID technology according to claim 6, wherein the sailing processor includes 8 signal channels, and the number of the embedded storage chips is 2, 4, 6, or 8.
8. The intelligent destruction method for the storage mainboard based on the sailing platform and the RAID technology as claimed in claim 7, wherein the embedded storage chip comprises a QE pin, and when the QE pin is at a low level, intelligent destruction is triggered.
9. The intelligent destruction method for the storage mainboard based on the sailing platform and the RAID technology as claimed in claim 8, wherein the storage mainboard based on the sailing platform and the RAID technology further comprises a power supply module for supplying power to the embedded storage chip.
10. The intelligent destruction method for a storage motherboard based on a sailing platform and a RAID technology according to claim 9, wherein the power supply module includes a voltage timing control circuit that outputs a first voltage to the control module, a second voltage to the flash memory module, a third voltage to the cache module, and a fourth voltage to the interface module according to a preset power-on timing.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210376748.6A CN114840885A (en) | 2022-04-12 | 2022-04-12 | Intelligent destruction method for storage mainboard based on sailing platform and RAID technology |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210376748.6A CN114840885A (en) | 2022-04-12 | 2022-04-12 | Intelligent destruction method for storage mainboard based on sailing platform and RAID technology |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN114840885A true CN114840885A (en) | 2022-08-02 |
Family
ID=82564072
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210376748.6A Pending CN114840885A (en) | 2022-04-12 | 2022-04-12 | Intelligent destruction method for storage mainboard based on sailing platform and RAID technology |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114840885A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2024040928A1 (en) * | 2022-08-24 | 2024-02-29 | 苏州元脑智能科技有限公司 | Data destruction method and apparatus, and computer device and storage medium |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101465164A (en) * | 2009-01-12 | 2009-06-24 | 成都市华为赛门铁克科技有限公司 | Method, device and system for obliterating data |
| CN113704834A (en) * | 2021-08-17 | 2021-11-26 | 深圳市安信达存储技术有限公司 | Intelligent destroying method based on Feiteng processor |
| CN217085738U (en) * | 2022-04-12 | 2022-07-29 | 深圳市安信达存储技术有限公司 | Storage mainboard based on sailing platform and RAID technique |
-
2022
- 2022-04-12 CN CN202210376748.6A patent/CN114840885A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101465164A (en) * | 2009-01-12 | 2009-06-24 | 成都市华为赛门铁克科技有限公司 | Method, device and system for obliterating data |
| CN113704834A (en) * | 2021-08-17 | 2021-11-26 | 深圳市安信达存储技术有限公司 | Intelligent destroying method based on Feiteng processor |
| CN217085738U (en) * | 2022-04-12 | 2022-07-29 | 深圳市安信达存储技术有限公司 | Storage mainboard based on sailing platform and RAID technique |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2024040928A1 (en) * | 2022-08-24 | 2024-02-29 | 苏州元脑智能科技有限公司 | Data destruction method and apparatus, and computer device and storage medium |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9804794B2 (en) | Techniques for providing data redundancy after reducing memory writes | |
| TWI451435B (en) | Non-volatile memory storage apparatus, memory controller and data storage method | |
| US20040078663A1 (en) | Information processing system and disk control method used in the same | |
| KR20180065423A (en) | Storage Device comprising repairable volatile memory and operating method of storage device | |
| US8103939B2 (en) | Storage system and data storage method | |
| US7124244B2 (en) | Storage system and a method of speeding up writing data into the storage system | |
| JP5353887B2 (en) | Disk array device control unit, data transfer device, and power recovery processing method | |
| CN110795027A (en) | Solid state storage device and electronic system including the same | |
| US9747200B1 (en) | Memory system with high speed non-volatile memory backup using pre-aged flash memory devices | |
| CN217085738U (en) | Storage mainboard based on sailing platform and RAID technique | |
| US11733883B2 (en) | Storage device initiating maintenance operation actively without instruction of host and electronic system including the same | |
| CN113704834B (en) | Intelligent destroying method based on Feiteng processor | |
| US8883521B2 (en) | Control method of multi-chip package memory device | |
| CN114840885A (en) | Intelligent destruction method for storage mainboard based on sailing platform and RAID technology | |
| US20220187987A1 (en) | Temperature control method and data storage system | |
| TWI798680B (en) | Method for managing host memory buffer, memory storage apparatus and memory control circuit unit | |
| KR20210038753A (en) | Data Storage Apparatus and Operating Method Thereof | |
| WO2021088368A1 (en) | Method and device for repairing memory | |
| CN113050896A (en) | Domestic Feiteng server supporting NVDIMM and data protection method | |
| CN113704836B (en) | Intelligent destroying method based on Loongson processor | |
| US10861576B2 (en) | Nonvolatile memory device, operating method thereof and data storage device including the same | |
| US11593242B2 (en) | Method of operating storage device for improving reliability, storage device performing the same and method of operating storage using the same | |
| CN116264100A (en) | Fast memory ECC error correction | |
| EP4286987A1 (en) | Storage system including battery module and method for operating the same | |
| CN220137656U (en) | SATA solid state disk restarting power-down protection circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |