CN103618618A - Line card fault recovery method and related device based on distributed PCIE system - Google Patents
Line card fault recovery method and related device based on distributed PCIE system Download PDFInfo
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Abstract
The invention discloses a line card fault recovery method and device based on a distributed PCIE system and a line card. The line card fault recovery method based on the distributed PCIE system comprises the steps that after a faulted line card in the distributed PCIE system is automatically restarted, and a PCIE port on the faulted line card is closed to inform an exchange chip in the distributed PCIE system of abandoning data, wherein the exchange chip is arranged in the distributed PCIE system, and is connected with the faulted line card, and a destination address of the data is the address of the faulted line card; after prestored PCIE configuration information of the faulted line card is obtained, configuration is carried out according to the obtained PCIE configuration information; the PCIE port is opened to inform the exchange chip of recovering sending of the data, wherein the destination address of the data is the address of the faulted line card. According to the scheme, congestion of the whole PCIE system can be effectively prevented from happening, and software resources of a master control card are saved.
Description
Technical field
The present invention relates to communication technical field, espespecially a kind of line card fault recovery method, device and line card based on distributed quick peripheral component interconnect (Peripheral Component Interconnect Express, PCIE) system.
Background technology
PCIE bus is the high performance bus that is applied to transmit between each assembly in communication system data.In PCIE system, adopt point-to-point interconnection, all have independently PCIE bus between the assembly of every a pair of interconnection, between each assembly, the concurrent transfer of data of carrying out is independent of each other.Owing to adopting point-to-point interconnection technique, by the topological structure of all right flexible expansion PCIE system of PCIE exchange chip (Switch, SW).
PCIE system generally comprises root assembly (Root Complex, RC), PCIE SW and end points (End Point, EP).RC is generally integrated in central processing unit (Central Processing Unit, CPU), except common data-transformation facility, can also realize whole PCIE system is scanned, configures, manages etc. function.PCIE SW at least comprises plural port, allows data from a port transmission to another port, and its major function is the topology of expansion PCIE system.EP is the various integrated equipment of PCIE port, and EP can realize and other EP or the transfer of data between RC by PCIE bus.Be illustrated in figure 1 the structure of a simple PCIE system.
Introduce several characteristics of PCIE system below.
The firstth, scanning, when PCIE system has just powered on, RC can't see other assemblies in PCIE system, therefore must scan.During scanning, RC can send special packet, and the assembly that receives this special packet can send response message to RC, and RC just confirms that this assembly exists after receiving response message.After having scanned, RC just can confirm the information such as assembly that whole PCIE system exists and connected mode thereof.
The secondth, configuration, after scanning completes, RC also needs each assembly in PCIE system to be configured, and the object of configuration is for the register in each assembly is rationally set, and makes whole PCIE system can carry out normal transfer of data.For example, RC will arrange the base register of each EP inside, and base register storage is the memory headroom that RC distributes to each EP, and EP is exactly according to the content in base register, judges whether receive to appear at data in PCIE bus.
The 3rd is Flow Control, and PCIE system is a kind of reliable data transmission system, and the Flow Control that all transfer of data all must be observed based on credit guarantees that data are not arbitrarily abandoned in PCIE system.Credit is corresponding with the data that can send, and credit is many, represents that the data that can send are many, otherwise, represent that the data that can send are few.Suppose that assembly A and assembly B are two assemblies in PCIE system, the basic principle that assembly A sends message to assembly B as shown in Figure 2.
First assembly B can be according to the size of own inner freebuf, and the message that regularly credit information is carried in transmission, to assembly A, can upgrade the credit pool of oneself after assembly A receives.Assembly A sends before message to assembly B, first inquire about the credit pool of self, judges whether enough credit, if credit is enough, to assembly B, sends message, and the credit in credit pool will reduce accordingly simultaneously; If credit is inadequate, can not send message to equipment B.Due to the credit pool reflection in assembly is the size of opposite end assembly freebuf, thereby the freebuf that guarantees to only have opposite end assembly is enough greatly time, could send message to opposite end assembly, avoid opposite end assembly that packet loss occurs because of out of buffers, guarantee the reliability of transfer of data.
Generally, RC is integrated in CPU inside, has independently software systems, PCIE SW exists with the form of chip, the form of EP is more flexible, can be the general interface chip that there is no independent operating software systems, and can be also has independent operating software systems the integrated CPU of EP function.If the form of EP is the latter, PCIE system has at least two CPU and software systems, and such PCIE system is called distributed PCIE system.In distributed PCIE system, the board at RC place is called main control card, and the board at EP place is called line card, is the distributed PCIE system that has three CPU as shown in Figure 3.
At present, along with the fast development of the network communications technology, distributed PCIE system applies, in the increasing network equipment, particularly requires the core network device of high-performance and powerful disposal ability.
Owing to there are a plurality of CPU in distributed PCIE system, handling property is very high, and reliability is poor.Because each CPU has the software systems of oneself, be easy to because the reason of software aspect breaks down, for example, when software is absorbed in endless loop, occur runs while flying etc. situation and all can break down, line card detects after the cpu fault of oneself, can restart CPU, configuration information on the line card at this CPU place is all lost, and cannot continue normal transmission data.Line card wants to recover to transmit normally data, need to main control card detect that line card breaks down and it is re-started to scanning and configuration after.Because the main control card that breaks down from line card detects line card, break down and re-start scanning and configuration one long period of needs, during this period of time, likely because of fault line card, trigger whole PCIE system generation congested, and then affect the transfer of data of other normal line cards; And, in the process of fault recovery, need main control card to re-start scanning and configuration, also can waste the software resource of main control card.
Summary of the invention
The embodiment of the present invention provides a kind of line card fault recovery method, device and line card based on distributed PCIE system, in order to solve in the existing process of fault wire card being recovered based on distributed PCIE system, may trigger whole PCIE system occurs congested and then affects the transfer of data of other normal line cards and the problem of the software resource of waste main control card.
Therefore, according to the embodiment of the present invention, provide a kind of line card fault recovery method based on distributed PCIE system, comprising:
After fault line card autoboot in described distributed PCIE system, close the PCIE port on described fault line card, take to notify and in described distributed PCIE system, link with described fault wire the exchange chip connecing and abandon destination address as the data of the address of described fault line card;
Obtain after the PCIE configuration information of the described fault line card of preserving in advance, according to the PCIE configuration information obtaining, be configured;
Open described PCIE port, take and notify described exchange chip to recover the data that sending destination location is the address of described fault line card.
Concrete, preserve in advance the PCIE configuration information of described fault line card, specifically comprise:
Before described fault line card breaks down, in memory, preserve described PCIE configuration information.
Concrete, obtain the PCIE configuration information of the described fault line card of preservation in advance, specifically comprise:
From described memory, obtain described PCIE configuration information.
Concrete, described memory is nonvolatile storage.
A kind of line card fault recovery device based on distributed PCIE system is also provided, comprises:
Closing unit, after fault line card autoboot for the described distributed PCIE system at self place, close the PCIE port on described fault line card, take and notify fault wire described in described distributed PCIE system to link the exchange chip connecing to abandon destination address as the data of the address of described fault line card;
Dispensing unit, for obtaining after the PCIE configuration information of the described fault line card of preserving in advance, is configured according to the PCIE configuration information obtaining;
Open unit, for opening described PCIE port, take, notify described exchange chip to recover the data that sending destination location is the address of described fault line card.
Concrete, described dispensing unit, for preserving in advance the PCIE configuration information of described fault line card, specifically for:
Before described fault line card breaks down, in memory, preserve described PCIE configuration information.
Concrete, described dispensing unit, for obtaining the PCIE configuration information of the described fault line card of preserving in advance, specifically for:
From described memory, obtain described PCIE configuration information.
Concrete, described memory is nonvolatile storage.
A kind of line card is also provided, comprises the above-mentioned line card fault recovery device based on distributed PCIE system.
The line card fault recovery method based on distributed PCIE system that the embodiment of the present invention provides, device and line card, owing to having preserved PCIE configuration information before online card failure, thereby can guarantee line card break down and autoboot after, self can be configured, and realize and in distribution of notifications formula PCIE system, link with fault wire the exchange chip connecing and abandon or recover the data that sending destination location is the address of fault line card by closing and open PCIE port, in the process of fault recovery, can effectively avoid whole PCIE system to occur congested, and then guarantee the transfer of data of other normal line cards, and failover procedure just can complete without the participation of main control card, has saved the software resource of main control card.
Accompanying drawing explanation
Fig. 1 is the structural representation of prior art PCIE system;
Fig. 2 is the schematic diagram based on credit transmission data between assembly A and assembly B in prior art;
Fig. 3 is the structural representation of distributed PCIE system in prior art;
Fig. 4 is the schematic diagram of two data flow based on Fig. 3 in prior art;
Fig. 5 is the flow chart of the line card fault recovery method based on distributed system in the embodiment of the present invention;
Fig. 6 is the structural representation of the line card fault recovery device based on distributed system in the embodiment of the present invention.
Embodiment
In the existing process of fault wire card being recovered based on distributed PCIE system, may trigger whole PCIE system and occur congested and then affect the transfer of data of other normal line cards and the problem of the software resource of waste main control card.Inventor has carried out conscientious research and has found:
As shown in Figure 4, suppose to have two data flow, be respectively line card 1 and arrive the data flow 1 of line card 2 and the data flow 2 that line card 1 arrives main control card, when distributed PCIE system is normally moved, these two data flow can normal transmission.When line card 2 break down and autoboot after, the configuration register in line card 2 can be reset, original PCIE configuration information is lost, line card 2 cannot normally receive data again.
Because other line cards cannot be learnt fault of line card 2, so also can continue to send data to line card 2.Line card 1 can continue to line card 2, to send data by the port 2 of PCIE SW and port 3, because line card 2 cannot normally receive data, data can be accumulated in the freebuf of line card 2, thereby exhaust the freebuf of line card 2, cause the credit pool of 3 li of ports of PCIE SW depleted, port 3 cannot continue to send data to line card 2.
When line card 1 continues to send data by the port 2 of PCIE SW to line card 2, because data cannot be sent from the port 3 of PCIE SW, data can be accumulated in the freebuf of port 2 of PCIE SW, finally cause the freebuf of port 2 depleted, the credit pool of line card 1 is also depleted, and line card 1 cannot be again sends data to the port 2 of PCIE SW.
Because line card 1 cannot send data to the port 2 of PCIE SW, cause data flow 2 also to occur cutout, data are all deposited in exchange chip, at this moment distributed PCIE system has just occurred congested, after congested generation, although line card 1 is normal line card, still cannot carry out normal transfer of data.
In order to reduce erroneous judgement, main control card just can detect line card 2 and break down after line card 2 breaks down in one longer period, and can re-start scanning and configuration to line card 2, after line card 2 fault recoveries, congested could releasing gradually, whole distributed PCIE system recovers normal.
Based on above-mentioned analysis, the embodiment of the present invention provides a kind of line card fault recovery method based on distributed PCIE system, and the flow process of the method as shown in Figure 5, performs step as follows:
S50: after the fault line card autoboot in distributed PCIE system, the PCIE port on closing fault line card, take and link with fault wire the exchange chip connecing in distribution of notifications formula PCIE system and abandon destination address as the data of the address of fault line card.
Continue to continue to use the example of Fig. 4, meeting autoboot after line card 2 some fault of generation, fault may fly, hang and wait indefinitely for software runs, data in the configuration register of line card 2 all can be reset to original default state, PCIE configuration information while being also just equivalent to line card 2 normal operation has been lost, and line card 2 cannot continue to receive data.
After line card 2 autoboots, can carry out initialization, first close PCIE port, that is to say that the state of PCIE port is set to close (Disable) state, the PCIE bus that this PCIE port connects is in disconnecting (Link down) state.The port 3 of the PCIE SW of the PCIE bus other end that this PCIE port connects also will be in Link down state.
According to PCIE standard, PCIE SW detects port 3 when Link down, the all data that mail to line card 2 by port 3 can be abandoned, the freebuf of port 2 can be just the data exhaustion of the address of line card 2 by destination address like this, data flow 2 just can keep normal transmission so, has so just reached line card 2 faults and has restarted but do not affect the object that other line cards work.
S51: obtain after the PCIE configuration information of the fault line card of preserving in advance, be configured according to the PCIE configuration information obtaining.
In line card 2 initialization procedures, obtain the PCIE configuration information of the line card 2 of preserving in advance, be used for configuring the configuration register of line card 2, so just can, after line card 2 is restarted, not need main control card again to initiate the scanning of line card 2 and configuration.
S52: open port, take and notify exchange chip to recover the data that sending destination location is the address of fault line card.
After having configured, line card 2 will reopen PCIE port, and namely the state of PCIE port is set to open (Enable) state, and the PCIE bus that PCIE port connects is in being communicated with (Link up) state.
PCIE SW detects port 3 after Link up state, will recover to line card 2, to send data by port 3 ports, and line card 2 also will normally receive data, and whole distributed PCIE system recovers normal.
In this scheme, owing to having preserved PCIE configuration information before online card failure, thereby can guarantee line card break down and autoboot after, self can be configured, and realize and in distribution of notifications formula PCIE system, link with fault wire the exchange chip connecing and abandon or recover the data that sending destination location is the address of fault line card by closing and open PCIE port, in the process of fault recovery, can effectively avoid whole PCIE system to occur congested, and then guarantee the transfer of data of other normal line cards; And failover procedure just can complete without the participation of main control card, has saved the software resource of main control card.
Concrete, the PCIE configuration information of preserving in advance fault line card in above-mentioned S51, specifically comprises: before fault line card breaks down, preserve PCIE configuration information in memory.
When line card normally moves, can regularly the PCIE configuration information in configuration register be kept in memory, thereby be convenient to can obtain voluntarily and be configured after line card fault.
Concrete, the PCIE configuration information that obtains the fault line card of preserving in advance in above-mentioned S51, specifically comprises: from memory, obtain PCIE configuration information.
Concrete, above-mentioned memory is nonvolatile storage, be specially EEPROM (Electrically Erasable Programmable Read Only Memo) (Electrically Erasable Programmable Read-Only Memory, EEPROM), flash memory (FLASH) etc., owing to adopting nonvolatile storage, can guarantee that institute's canned data is not lost when line card reset or lower electricity.
Based on same inventive concept, the embodiment of the present invention provides a kind of line card fault recovery device based on distributed PCIE system, and this device can be arranged in line card, and structure as shown in Figure 6, comprising:
Closing unit 60, after fault line card autoboot for the distributed PCIE system at self place, PCIE port on closing fault line card, take and link with fault wire the exchange chip connecing in distribution of notifications formula PCIE system and abandon destination address as the data of the address of fault line card.
Dispensing unit 61, for obtaining after the PCIE configuration information of the fault line card of preserving in advance, is configured according to the PCIE configuration information obtaining.
Concrete, above-mentioned dispensing unit 61, for preserving in advance the PCIE configuration information of fault line card, specifically for: before fault line card breaks down, in memory, preserve PCIE configuration information.
Concrete, above-mentioned dispensing unit 61, for obtaining the PCIE configuration information of the fault line card of preserving in advance, specifically for: from memory, obtain PCIE configuration information.
Concrete, above-mentioned memory is nonvolatile storage.
The present invention is with reference to describing according to flow chart and/or the block diagram of the method for the embodiment of the present invention, equipment (system) and computer program.Should understand can be in computer program instructions realization flow figure and/or block diagram each flow process and/or the flow process in square frame and flow chart and/or block diagram and/or the combination of square frame.Can provide these computer program instructions to the processor of all-purpose computer, special-purpose computer, Embedded Processor or other programmable data processing device to produce a machine, the instruction of carrying out by the processor of computer or other programmable data processing device is produced for realizing the device in the function of flow process of flow chart or a plurality of flow process and/or square frame of block diagram or a plurality of square frame appointments.
These computer program instructions also can be stored in energy vectoring computer or the computer-readable memory of other programmable data processing device with ad hoc fashion work, the instruction that makes to be stored in this computer-readable memory produces the manufacture that comprises command device, and this command device is realized the function of appointment in flow process of flow chart or a plurality of flow process and/or square frame of block diagram or a plurality of square frame.
These computer program instructions also can be loaded in computer or other programmable data processing device, make to carry out sequence of operations step to produce computer implemented processing on computer or other programmable devices, thereby the instruction of carrying out is provided for realizing the step of the function of appointment in flow process of flow chart or a plurality of flow process and/or square frame of block diagram or a plurality of square frame on computer or other programmable devices.
Although described optional embodiment of the present invention, once those skilled in the art obtain the basic creative concept of cicada, can make other change and modification to these embodiment.So claims are intended to be interpreted as all changes and the modification that comprise optional embodiment and fall into the scope of the invention.
Obviously, those skilled in the art can carry out various changes and modification and not depart from the spirit and scope of the embodiment of the present invention the embodiment of the present invention.Like this, if within these of the embodiment of the present invention are revised and modification belongs to the scope of the claims in the present invention and equivalent technologies thereof, the present invention is also intended to comprise these changes and modification interior.
Claims (9)
1. the line card fault recovery method based on distributed PCIE system, is characterized in that, comprising:
After fault line card autoboot in described distributed quick peripheral component interconnect PCIE system, close the PCIE port on described fault line card, take to notify and in described distributed PCIE system, link with described fault wire the exchange chip connecing and abandon destination address as the data of the address of described fault line card;
Obtain after the PCIE configuration information of the described fault line card of preserving in advance, according to the PCIE configuration information obtaining, be configured;
Open described PCIE port, take and notify described exchange chip to recover the data that sending destination location is the address of described fault line card.
2. the method for claim 1, is characterized in that, preserves in advance the PCIE configuration information of described fault line card, specifically comprises:
Before described fault line card breaks down, in memory, preserve described PCIE configuration information.
3. method as claimed in claim 2, is characterized in that, obtains the PCIE configuration information of the described fault line card of preserving in advance, specifically comprises:
From described memory, obtain described PCIE configuration information.
4. method as claimed in claim 2 or claim 3, is characterized in that, described memory is nonvolatile storage.
5. the line card fault recovery device based on distributed PCIE system, is characterized in that, comprising:
Closing unit, after fault line card autoboot for the described distributed quick peripheral component interconnect PCIE system at self place, close the PCIE port on described fault line card, take and notify fault wire described in described distributed PCIE system to link the exchange chip connecing to abandon destination address as the data of the address of described fault line card;
Dispensing unit, for obtaining after the PCIE configuration information of the described fault line card of preserving in advance, is configured according to the PCIE configuration information obtaining;
Open unit, for opening described PCIE port, take, notify described exchange chip to recover the data that sending destination location is the address of described fault line card.
6. device as claimed in claim 5, is characterized in that, described dispensing unit, and for preserving in advance the PCIE configuration information of described fault line card, specifically for:
Before described fault line card breaks down, in memory, preserve described PCIE configuration information.
7. device as claimed in claim 6, is characterized in that, described dispensing unit, and for obtaining the PCIE configuration information of the described fault line card of preserving in advance, specifically for:
From described memory, obtain described PCIE configuration information.
8. the device as described in claim 6 or 7, is characterized in that, described memory is nonvolatile storage.
9. a line card, is characterized in that, comprises the line card fault recovery device based on distributed PCIE system as described in as arbitrary in claim 5-8.
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| CN111767242A (en) * | 2020-05-28 | 2020-10-13 | 西安广和通无线软件有限公司 | PCIE equipment control method and device, computer equipment and storage medium |
| CN112187395A (en) * | 2020-11-02 | 2021-01-05 | 上海欣诺通信技术股份有限公司 | Time synchronization method and device in distributed system |
| CN112187395B (en) * | 2020-11-02 | 2022-07-15 | 上海欣诺通信技术股份有限公司 | Time synchronization method and device in distributed system |
| WO2022155919A1 (en) * | 2021-01-22 | 2022-07-28 | 华为技术有限公司 | Fault handling method and apparatus, and system |
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