CN111767242A - PCIE equipment control method and device, computer equipment and storage medium - Google Patents

PCIE equipment control method and device, computer equipment and storage medium Download PDF

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Publication number
CN111767242A
CN111767242A CN202010466067.XA CN202010466067A CN111767242A CN 111767242 A CN111767242 A CN 111767242A CN 202010466067 A CN202010466067 A CN 202010466067A CN 111767242 A CN111767242 A CN 111767242A
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pcie
state
interface
equipment
abnormal
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CN111767242B (en
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桂永林
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Xian Fibocom Wireless Software Inc
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Xian Fibocom Wireless Software Inc
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G06F13/4081—Live connection to bus, e.g. hot-plugging
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0026—PCI express

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  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Debugging And Monitoring (AREA)

Abstract

The application relates to a PCIE equipment control method, a PCIE equipment control device, computer equipment and a storage medium. The method comprises the following steps: monitoring the state of the PCIE equipment through the universal interface, and receiving a state exception message reported by the universal interface when the state of the PCIE equipment is abnormal; responding to the abnormal state message, sending a scanning command to the PCIE controller, so that the PCIE controller scans the PCIE bus according to the scanning command to obtain a scanning result of the PCIE equipment; and receiving a scanning result sent by the PCIE controller, and establishing communication connection with the PCIE equipment when the scanning result indicates that the PCIE equipment exists. By adopting the method, the host can support the hot plug of the PCIE equipment, can know whether the state of the PCIE equipment is abnormal or not, can establish communication connection with the PCIE equipment again under the condition of not needing to be restarted, realizes the uninterrupted operation and maintenance of the system, improves the operation and maintenance efficiency of the system and improves the stability of the system.

Description

PCIE equipment control method and device, computer equipment and storage medium
Technical Field
The present application relates to the field of computer technologies, and in particular, to a PCIE device control method and apparatus, a computer device, and a storage medium.
Background
With the rapid development of 5G communication technology, higher requirements are put on the communication rate of the interface between chips, and a PCIE (peripheral component interconnect express) interface is gradually becoming a main interface in the 5G era under this background.
However, in a host supporting a PCIE interface at present, the PCIE interface does not support a hot-plug function of a PCIE device, that is, hot-plugging. When the PCIE device is restarted or abnormally reset, the host must recover communication with the PCIE device after being restarted, so that uninterrupted operation and maintenance of the system cannot be implemented, the operation and maintenance efficiency of the system is seriously affected, and even a high-speed signal and power supply abnormality of the whole system may be caused, so that the system is down, and the stability of the system cannot be ensured.
Disclosure of Invention
Therefore, it is necessary to provide a PCIE device control method, an apparatus, a computer device, and a storage medium, which can support the hot plug of a PCIE device and improve the system stability, in order to solve the above technical problems.
A PCIE device control method, the method comprising:
monitoring the state of the PCIE equipment through a general interface, and receiving a state exception message reported by the general interface when the state of the PCIE equipment is abnormal;
responding to the state exception message, sending a scanning command to the PCIE controller, so that the PCIE controller scans the PCIE bus according to the scanning command to obtain a scanning result of the PCIE equipment;
and receiving a scanning result sent by the PCIE controller, and establishing communication connection with the PCIE equipment when the scanning result is that the PCIE equipment exists.
In one embodiment, the general purpose interface includes a GPIO interface, and before the monitoring of the state of the PCIE device through the general purpose interface and when the state of the PCIE device is abnormal, receiving a state abnormality message reported by the general purpose interface, the method further includes:
calling a GPIO (general purpose input/output) driven setting interface, and setting the GPIO interface into an interrupt mode through the GPIO driven setting interface, so that when the state of the PCIE (peripheral component interface express) equipment is abnormal, the GPIO interface is triggered to be interrupted;
the monitoring of the state of the PCIE device through the universal interface, and when the state of the PCIE device is abnormal, the receiving of a state abnormality message reported by the universal interface includes:
and when the GPIO interface is interrupted, receiving an interruption message reported by the GPIO interface, and determining that the state of the PCIE equipment is abnormal according to the interruption message.
In one embodiment, after the receiving the scan result sent by the PCIE controller, and when the scan result indicates that the PCIE device exists, and after establishing communication connection with the PCIE device, the method further includes:
and calling a setting interface driven by the GPIO, and setting the GPIO interface to be in a non-interrupt state.
In one embodiment, the universal interface includes a USB interface, the monitoring the state of the PCIE device through the universal interface, and when the state of the PCIE device is abnormal, the receiving a state abnormality message reported by the universal interface includes:
monitoring data of the USB interface, wherein the USB interface is reset when the state of the PCIE equipment is abnormal;
and receiving a reset message of the USB interface, and determining that the state of the PCIE equipment is abnormal according to the reset message.
In one embodiment, the method further comprises:
and when the abnormal state message is received, sending a warning message to an external device, and sending a warning through the external device, wherein the external device comprises at least one of a display device and an audio device.
In one embodiment, the method further comprises:
and when the scanning result indicates that the PCIE equipment does not exist, sending a warning message to external equipment, and sending a warning through the external equipment, wherein the external equipment comprises at least one of display equipment and audio equipment.
In one embodiment, the method further comprises:
and when the scanning result is that the PCIE equipment does not exist, sending a scanning command to the PCIE controller again after a preset time interval, returning to execute the step of receiving the scanning result sent by the PCIE controller, and when the scanning result is that the PCIE equipment exists, establishing communication connection with the PCIE equipment.
A PCIE device control apparatus, the apparatus comprising:
the PCIE equipment state monitoring module is used for monitoring the state of the PCIE equipment through a general interface, and receiving a state exception message reported by the general interface when the state of the PCIE equipment is abnormal;
a scan command sending module, configured to send a scan command to the PCIE controller in response to the status exception message, so that the PCIE controller scans the PCIE bus according to the scan command to obtain a scan result of the PCIE device;
and the communication connection establishing module is used for receiving a scanning result sent by the PCIE controller, and establishing communication connection with the PCIE equipment when the scanning result indicates that the PCIE equipment exists.
A computer device comprising a memory storing a computer program and a processor implementing the steps of the method described above when executing the computer program.
A computer-readable storage medium, on which a computer program is stored which, when being executed by a processor, carries out the steps of the above-mentioned method.
According to the PCIE equipment control method, the PCIE equipment control device, the computer equipment and the storage medium, the state of the PCIE equipment is monitored through the universal interface, and when the state of the PCIE equipment is abnormal, a state abnormal message reported by the universal interface is received; responding to the abnormal state message, sending a scanning command to the PCIE controller, so that the PCIE controller scans the PCIE bus according to the scanning command to obtain a scanning result of the PCIE equipment; the method comprises the steps of receiving a scanning result sent by a PCIE controller, and when the scanning result indicates that the PCIE equipment exists, establishing communication connection with the PCIE equipment, so that a host can support hot plug of the PCIE equipment, can know whether the state of the PCIE equipment is abnormal or not, and can establish communication connection with the PCIE equipment again under the condition that restarting is not needed, thereby realizing uninterrupted operation and maintenance of the system, improving the operation and maintenance efficiency of the system and improving the stability of the system.
Drawings
Fig. 1 is an application environment diagram of a PCIE device control method in an embodiment;
fig. 2 is a schematic flow chart of a PCIE device control method in an embodiment;
fig. 3 is a schematic flowchart illustrating a control method for a PCIE device whose general purpose interface is a GPIO interface in an embodiment;
fig. 4 is a schematic flowchart of a PCIE device control method in which a general interface is a USB interface in one embodiment;
fig. 5 is a schematic flow chart of a PCIE device control method in another embodiment;
fig. 6 is a block diagram of a control apparatus of a PCIE device in one embodiment;
FIG. 7 is a diagram illustrating an internal structure of a computer device according to an embodiment.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.
The PCIE device control method provided in the present application may be applied to an application environment shown in fig. 1. The host 102 communicates with the PCIE device 104 through the PCIE bus. The host 102 includes a processor 106 and a PCIE controller 108, and the processor 106 and the PCIE controller 108 are connected through a system bus. In other embodiments, the PCIE controller 108 may also be integrated within the processor 106. The PCIE device 104 includes a common interface 110. The host 102 may be connected to the generic interface 110, and control the PCIE device 104 through the generic interface 110.
Specifically, the processor 106 monitors the status of the PCIE device 104 through the generic interface 110. When the state of the PCIE device 104 is abnormal, the processor 106 receives a state abnormal message reported by the universal interface 110. In response to the status exception message, the processor 106 sends a scan command to the PCIE controller 108. The PCIE controller 108 scans the PCIE bus according to the scan command, and obtains a scan result of the PCIE device 104. Further, the processor 106 receives a scanning result sent by the PCIE controller 108, and establishes a communication connection with the PCIE device 104 when the scanning result indicates that the PCIE device 104 exists.
In an embodiment, as shown in fig. 2, a PCIE device control method is provided, which is described by taking the example that the method is applied to the processor in fig. 1, and includes the following steps:
step 202, monitoring the state of the PCIE device through the universal interface, and receiving a state exception message reported by the universal interface when the state of the PCIE device is abnormal.
Among them, PCIE (peripheral component interconnect express, high-speed serial computer expansion bus standard) is the latest bus and interface standard, and can provide a higher data transmission rate, and meet the requirement of 5G communication. A PCIE device is a device conforming to the PCIE standard, such as a network card, a display card, and the like. In General, a PCIE device supports a General purpose interface, such as a GPIO (General-purpose input/output) interface, in addition to its own PCIE interface.
Specifically, the host establishes a communication connection with the PCIE device through the PCIE bus. In the prior art, when a PCIE device is abnormal, because a host does not support hot plug, a processor on the host cannot recognize an abnormal state of the PCIE device, a PCIE device link cannot be recovered, so that the host cannot communicate with the PCIE device, the host must perform rescan and enumeration on a PCIE bus after being restarted, and the processor reestablishes communication connection with the PCIE device after recognizing the PCIE device. Therefore, in the method, the host is connected to the universal interface on the PCIE device, and the state of the PCIE device is monitored through the universal interface. When the state of the PCIE equipment is abnormal, the state of the universal interface is triggered to change. When the state of the universal interface changes, a state exception message is reported to the host (i.e., a processor on the host), so that the processor on the host can identify the exception state of the PCIE device. The abnormal state of the PCIE device may be a restart, a reset, or another failure.
Step 204, in response to the status exception message, sending a scan command to the PCIE controller, so that the PCIE controller scans the PCIE bus according to the scan command to obtain a scan result of the PCIE device.
The PCIE controller is arranged between the processor and the PCIE equipment and connected with the PCIE equipment through a PCIE bus. The processor may control the PCIE device by issuing a command to the PCIE controller.
Specifically, when the state of the PCIE device is abnormal, the processor may receive a state exception message through the general interface. The processor learns that the state of the PCIE equipment is abnormal after receiving the state abnormal message, and sends a scanning command to the PCIE controller in response to the state abnormal message. The scanning command is used for instructing the PCIE controller to scan and enumerate the PCIE bus, so as to obtain a scanning result of the PCIE device. When the state of the PCIE device is recovered to be normal, the PCIE controller may identify the PCIE device when scanning and enumerating the PCIE bus. When the state of the PCIE device is still in an abnormal state, the PCIE controller cannot identify the PCIE device.
In one embodiment, the processor sends a scan command to the PCIE controller after a certain time interval when receiving the status exception message. When the PCIE device is simply restarted and reset, the PCIE device may recover to the normal state within a certain time interval, and scan the PCIE bus after the certain time interval, which can ensure that the processor effectively identifies the PCIE device.
And step 206, receiving a scanning result sent by the PCIE controller, and establishing a communication connection with the PCIE device when the scanning result indicates that the PCIE device exists.
Specifically, after the PCIE controller finishes scanning and enumeration of the PCIE bus, a scanning result may be obtained. And the PCIE controller sends the scanning result to the processor. The processor detects the scanning result, and when the scanning result indicates that the PCIE device is in a normal state, the processor may reestablish the communication connection with the PCIE device.
In the control method of the PCIE device, the state of the PCIE device is monitored through the general interface, and when the state of the PCIE device is abnormal, a state abnormal message reported by the general interface is received; responding to the abnormal state message, sending a scanning command to the PCIE controller, so that the PCIE controller scans the PCIE bus according to the scanning command to obtain a scanning result of the PCIE equipment; the method comprises the steps of receiving a scanning result sent by a PCIE controller, and when the scanning result indicates that the PCIE equipment exists, establishing communication connection with the PCIE equipment, so that a host can support hot plug of the PCIE equipment, can know whether the state of the PCIE equipment is abnormal or not, and can establish communication connection with the PCIE equipment again under the condition that restarting is not needed, thereby realizing uninterrupted operation and maintenance of the system, improving the operation and maintenance efficiency of the system and improving the stability of the system.
In one embodiment, as shown in fig. 3, when the general purpose interface is a GPIO interface, the PCIE device control method includes:
step 302, calling a setting interface driven by a GPIO, and setting the GPIO to be in an interrupt mode through the setting interface driven by the GPIO, so that when the state of the PCIE equipment is abnormal, the GPIO is triggered to be interrupted;
step 304, when the GPIO interface is interrupted, receiving an interrupt message reported by the GPIO interface, and determining that the state of the PCIE device is abnormal according to the interrupt message;
step 306, in response to the interrupt message, sending a scan command to the PCIE controller, so that the PCIE controller scans the PCIE bus according to the scan command to obtain a scan result of the PCIE device;
step 308, receiving a scanning result sent by the PCIE controller, and establishing a communication connection with the PCIE device when the scanning result indicates that the PCIE device exists;
and step 310, calling a setting interface driven by the GPIO, setting the GPIO interface to be in a non-interrupt state, and returning to step 304.
The GPIO interface is used as a general input/output interface, the PCIE equipment is provided with the GPIO interface, the working mode of the GPIO comprises an interrupt mode, and the processor can know the abnormal state of the PCIE equipment by triggering GPIO interrupt, so that the state of the PCIE equipment can be monitored through the GPIO interface.
Specifically, the host is connected with a GPIO interface on the PCIE device, the processor on the host calls the GPIO-driven setting interface, sets the operating mode of the GPIO interface through the GPIO-driven setting interface, and sets the operating mode as the interrupt mode. When the GPIO interface is in the interrupt mode, the GPIO interface waits for an interrupt event, and when the interrupt event occurs, the GPIO interface is triggered to interrupt. In this embodiment, the interrupt event is an abnormal state of the PCIE device. And when the GPIO interface is interrupted, the processor receives an interrupt message reported by the GPIO interface. After receiving the interrupt message of the GPIO interface, the processor may determine that the state of the PCIE device is abnormal.
Further, the processor sends a scan command to the PCIE controller to instruct the PCIE controller to scan and enumerate the PCIE bus, so as to obtain a scan result of the PCIE device. When the state of the PCIE device is recovered to be normal, the scan result may be obtained as that the PCIE device exists, and at this time, the processor may establish communication connection with the PCIE device again, recover the data link of the PCIE device, and implement communication between the host and the PCIE device.
After the processor and the PCIE equipment reestablish the communication connection, the processor calls the GPIO driving setting interface, the GPIO interface is set to be in a non-interrupt state, and the occurrence of an interrupt event is waited again.
In this embodiment, the state of the PCIE device is monitored by using the interrupt mode of the GPIO through connection with the GPIO interface on the PCIE device and setting the GPIO interface to the interrupt mode, so that the processor on the host can know the abnormal state of the PCIE device, identify the PCIE device without restarting the host, establish communication connection with the PCIE device again, and ensure the stability of the system.
In an embodiment, as shown in fig. 4, when the universal interface is a USB interface, the PCIE device control method includes:
step 402, performing data monitoring on a USB interface, wherein the USB interface is reset when the state of the PCIE device is abnormal;
step 404, receiving a reset message of the USB interface, and determining that the state of the PCIE device is abnormal according to the reset message;
step 406, in response to the reset message, sending a scan command to the PCIE controller, so that the PCIE controller scans the PCIE bus according to the scan command to obtain a scan result of the PCIE device;
step 408, receiving a scanning result sent by the PCIE controller, establishing a communication connection with the PCIE device when the scanning result indicates that the PCIE device exists, and returning to step 402.
The m.2 interface standard supports a PCIE interface and a USB (Universal Serial Bus) interface, and in the m.2 form, the host may be connected to the USB interface on the PCIE device, and detect the state of the PCIE device through the USB interface.
Specifically, the USB interface is a universal mature control interface, and can support hot plug of the USB device. When the state of the PCIE equipment is abnormal, the PCIE equipment can be reset, and meanwhile, the USB interface on the PCIE is triggered to be reset. The host is connected with the USB interface on the PCIE to monitor the data of the PCIE, and when the state of the PCIE equipment is abnormal, the processor can receive the reset message of the USB interface. After receiving the reset message of the USB interface, the processor may determine that the state of the PCIE device is abnormal. The data monitoring may be any one of the commonly used data monitoring methods, and the application is not limited herein.
Further, the processor sends a scan command to the PCIE controller to instruct the PCIE controller to scan and enumerate the PCIE bus, so as to obtain a scan result of the PCIE device. When the state of the PCIE device is recovered to be normal, the scan result may be obtained as that the PCIE device exists, and at this time, the processor may establish communication connection with the PCIE device again, recover the data link of the PCIE device, and implement communication between the host and the PCIE device.
In this embodiment, the PCIE device is connected to the USB interface on the PCIE device, and the state of the PCIE device is monitored by using the USB interface, so that the processor on the host can know the abnormal state of the PCIE device, identify the PCIE device without restarting the host, establish communication connection with the PCIE device again, and ensure the stability of the system.
In one embodiment, the processor may also monitor the state of the PCIE device through another general-purpose interface such as a USB to serial interface.
In one embodiment, the method further comprises: and when the abnormal state message is received, sending a warning message to an external device, and sending a warning through the external device, wherein the external device comprises at least one of a display device and an audio device.
Specifically, when the processor receives the status exception message, a warning message may be sent to the external device, and a warning may be issued by the external device. When the external device is a display device, a warning message may be popped up on the display device, and the warning message may be a text message, and the text message informs the user that the state of the PCIE device is abnormal. When the external device is an audio device, the audio device sends out an alarm sound, and the alarm sound informs a user that the state of the PCIE device is abnormal.
In other embodiments, when the external device is a display device, the warning information may also be presented in an animated or other form.
In this embodiment, when the status exception message is received, a warning is sent to notify the user that the status of the PCIE device is abnormal, so that the situation that the user blindly checks a module in the host and consumes labor and time when the user cannot communicate with the PCIE device because the reason for the incapability of communicating is not clear is avoided.
In one embodiment, the method further comprises: and when the scanning result shows that the PCIE equipment does not exist, sending a warning message to the external equipment, and sending a warning through the external equipment, wherein the external equipment comprises at least one of display equipment and audio equipment.
Specifically, when the scanning result does not have a PCIE device, it indicates that the PCIE device has not recovered to the normal state. If the cause of the abnormal state of the PCIE device is only simple restart or reset, or the abnormal state that other PCIE devices can autonomously recover is caused, the processor may identify the PCIE device after the PCIE device recovers the normal state, so as to establish communication connection with the PCIE device. However, when a failure that the PCIE device is unrecoverable, no matter how many times the PCIE controller performs scanning, the PCIE device cannot be obtained through scanning. Therefore, when the scanning result indicates that the PCIE device does not exist, the processor sends a warning message to the external device, and sends a warning through the external device to notify the user that the PCIE device cannot be identified, so as to remind the user to repair or replace the PCIE device in time.
In this embodiment, when the PCIE device cannot be identified, a warning is sent to notify a user that the state of the PCIE device is abnormal, so as to remind the user to check the PCIE device, and the PCIE device is repaired or replaced in time when the PCIE device fails, so that the security and reliability of the system are improved.
In one embodiment, the method further comprises: and when the scanning result is that the PCIE equipment does not exist, re-sending the scanning command to the PCIE controller after a preset time interval, returning to execute and receive the scanning result sent by the PCIE controller, and when the scanning result is that the PCIE equipment exists, establishing communication connection with the PCIE equipment.
Specifically, when the scanning result indicates that there is no PCIE device, it indicates that when the PCIE controller scans the PCIE bus, the PCIE device has not recovered to the normal state (for example, a failure of the PCIE device has not been repaired), and after a preset time interval, the scanning command is sent to the PCIE controller again to instruct the PCIE controller to scan and enumerate the PCIE bus again, so that it can be ensured that the PCIE device identifies and obtains the PCIE device after recovering to the normal state, and establishes communication connection with the PCIE device again.
In this embodiment, by sending the scan command to the PCIE controller again after the preset time interval, it can be ensured that the PCIE device identifies and obtains the PCIE device after recovering to the normal state, and establishes communication connection with the PCIE device again, so as to improve the effectiveness of communication between the host and the PCIE device.
In an embodiment, as shown in fig. 5, another PCIE device control method is provided, which is described by taking the example that the method is applied to the processor in fig. 1, and includes the following steps:
step 502, judging the type of a general interface on the PCIE device, entering step 504 when the type of the general interface is a GPIO interface, and entering step 508 when the type of the general interface is a USB interface;
step 504, a setting interface driven by the GPIO is called, and the GPIO is set to be in an interrupt mode through the setting interface driven by the GPIO, so that when the state of the PCIE equipment is abnormal, the GPIO is triggered to be interrupted;
step 506, when the GPIO interface is interrupted, receiving an interrupt message reported by the GPIO interface, determining that the state of the PCIE device is abnormal according to the interrupt message, and entering step 512;
step 508, data monitoring is performed on the USB interface, and the USB interface is reset when the state of the PCIE device is abnormal;
step 510, receiving a reset message of the USB interface, determining that the state of the PCIE device is abnormal according to the reset message, and entering step 512;
step 512, when it is determined that the state of the PCIE device is abnormal, sending a warning message to the external device, and sending a warning through the external device;
step 514, sending a scan command to the PCIE controller, so that the PCIE controller scans the PCIE bus according to the scan command to obtain a scan result of the PCIE device;
step 516, receiving a scanning result sent by the PCIE controller, determining whether there is a PCIE device, entering step 518 when there is a PCIE device, and entering step 520 when there is no PCIE device;
step 518, establishing communication connection with the PCIE device, entering step 520 when the type of the general interface is a GPIO interface, and returning to step 510 when the type of the general interface is a USB interface;
step 520, calling a setting interface driven by the GPIO, setting the GPIO interface to be in a non-interrupt state, and returning to step 506;
step 522, sending a warning message to an external device, and sending a warning through the external device, wherein the external device comprises at least one of a display device and an audio device;
in step 524, after a preset time interval, the scan command is sent to the PCIE controller again, and the process returns to step 516.
In this embodiment, the state of the PCIE device is monitored through the GPIO interface and/or the USB interface and other general interfaces, an abnormal state of the PCIE device can be known when the state of the PCIE device is abnormal, the PCIE bus is scanned, the PCIE device is identified, the communication connection with the PCIE device is reestablished, and when the state of the PCIE device is abnormal or the processor fails to identify the PCIE device, a warning is sent out to inform a user that the state of the PCIE device is abnormal, prompt the user to check the PCIE device, the PCIE device is maintained or replaced in time when the PCIE device fails, and the security and reliability of the system are improved.
It should be understood that although the various steps in the flow charts of fig. 2-5 are shown in order as indicated by the arrows, the steps are not necessarily performed in order as indicated by the arrows. The steps are not performed in the exact order shown and described, and may be performed in other orders, unless explicitly stated otherwise. Moreover, at least some of the steps in fig. 2-5 may include multiple steps or multiple stages, which are not necessarily performed at the same time, but may be performed at different times, which are not necessarily performed in sequence, but may be performed in turn or alternately with other steps or at least some of the other steps.
In one embodiment, as shown in fig. 6, there is provided a PCIE device control apparatus 600, including: a PCIE device status monitoring module 601, a scan command sending module 602, and a communication connection establishing module 603, where:
a PCIE device status monitoring module 601, configured to monitor a status of a PCIE device through a general interface, and receive a status exception message reported by the general interface when the status of the PCIE device is abnormal;
a scan command sending module 602, configured to send a scan command to the PCIE controller in response to the status exception message, so that the PCIE controller scans the PCIE bus according to the scan command to obtain a scan result of the PCIE device;
the communication connection establishing module 603 is configured to receive a scanning result sent by the PCIE controller, and establish a communication connection with the PCIE device when the scanning result indicates that the PCIE device exists.
In one embodiment, the PCIE device control 600 includes a GPIO interrupt mode setting module 604, configured to invoke a GPIO-driven setting interface, and set the GPIO interface to an interrupt mode through the GPIO-driven setting interface, so that when the state of the PCIE device is abnormal, the GPIO interface is triggered to be interrupted.
In an embodiment, the PCIE device state monitoring module 601 is further configured to receive an interrupt message reported by the GPIO interface when the GPIO interface is interrupted, and determine that the state of the PCIE device is abnormal according to the interrupt message.
In one embodiment, the PCIE device control apparatus 600 includes a GPIO state setting module 605, configured to invoke a GPIO-driven setting interface and set the GPIO interface to an uninterrupted state.
In one embodiment, the PCIE device state monitoring module 601 is further configured to perform data monitoring on a USB interface, where the USB interface is reset when the state of the PCIE device is abnormal; and receiving a reset message of the USB interface, and determining that the state of the PCIE equipment is abnormal according to the reset message.
In one embodiment, the PCIE device control apparatus 600 includes an alert module 606, configured to send an alert message to an external device when the status exception message is received, and send an alert through the external device, where the external device includes at least one of a display device and an audio device.
In one embodiment, the warning module 606 is further configured to send a warning message to an external device and issue a warning through the external device when the scanning result indicates that the PCIE device is not present, where the external device includes at least one of a display device and an audio device.
In an embodiment, the scan command sending module 602 is further configured to, when the scan result indicates that there is no PCIE device, send the scan command to the PCIE controller again after a preset time interval, return to execute receiving the scan result sent by the PCIE controller, and establish a communication connection with the PCIE device when the scan result indicates that there is a PCIE device.
For specific limitations of the PCIE device control apparatus, refer to the above limitations on the PCIE device control method, which is not described herein again. Each module in the PCIE device control apparatus may be implemented wholly or partially by software, hardware, or a combination thereof. The modules can be embedded in a hardware form or independent from a processor in the computer device, and can also be stored in a memory in the computer device in a software form, so that the processor can call and execute operations corresponding to the modules.
In one embodiment, a computer device is provided, which may be a terminal, and its internal structure diagram may be as shown in fig. 7. The computer device includes a processor, a memory, a communication interface, a display screen, and an input device connected by a system bus. Wherein the processor of the computer device is configured to provide computing and control capabilities. The memory of the computer device comprises a nonvolatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of an operating system and computer programs in the non-volatile storage medium. The communication interface of the computer device is used for carrying out wired or wireless communication with an external terminal, and the wireless communication can be realized through WIFI, an operator network, NFC (near field communication) or other technologies. The computer program is executed by a processor to implement a PCIE device control method. The display screen of the computer equipment can be a liquid crystal display screen or an electronic ink display screen, and the input device of the computer equipment can be a touch layer covered on the display screen, a key, a track ball or a touch pad arranged on the shell of the computer equipment, an external keyboard, a touch pad or a mouse and the like.
Those skilled in the art will appreciate that the architecture shown in fig. 7 is merely a block diagram of some of the structures associated with the disclosed aspects and is not intended to limit the computing devices to which the disclosed aspects apply, as particular computing devices may include more or less components than those shown, or may combine certain components, or have a different arrangement of components.
In one embodiment, a computer device is provided, comprising a memory and a processor, the memory having a computer program stored therein, the processor implementing the following steps when executing the computer program: monitoring the state of the PCIE equipment through the universal interface, and receiving a state exception message reported by the universal interface when the state of the PCIE equipment is abnormal; responding to the abnormal state message, sending a scanning command to the PCIE controller, so that the PCIE controller scans the PCIE bus according to the scanning command to obtain a scanning result of the PCIE equipment; and receiving a scanning result sent by the PCIE controller, and establishing communication connection with the PCIE equipment when the scanning result indicates that the PCIE equipment exists.
In one embodiment, the processor, when executing the computer program, further performs the steps of: calling a GPIO (general purpose input/output) driven setting interface, and setting the GPIO interface into an interrupt mode through the GPIO driven setting interface, so that when the state of the PCIE (peripheral component interface express) equipment is abnormal, the GPIO interface is triggered to be interrupted; and when the GPIO interface is interrupted, receiving an interruption message reported by the GPIO interface, and determining that the state of the PCIE equipment is abnormal according to the interruption message.
In one embodiment, the processor, when executing the computer program, further performs the steps of: and calling a GPIO driving setting interface, and setting the GPIO interface to be in an uninterrupted state.
In one embodiment, the processor, when executing the computer program, further performs the steps of: carrying out data monitoring on a USB interface, wherein the USB interface is reset when the state of the PCIE equipment is abnormal; and receiving a reset message of the USB interface, and determining that the state of the PCIE equipment is abnormal according to the reset message.
In one embodiment, the processor, when executing the computer program, further performs the steps of: and when the abnormal state message is received, sending a warning message to an external device, and sending a warning through the external device, wherein the external device comprises at least one of a display device and an audio device.
In one embodiment, the processor, when executing the computer program, further performs the steps of: and when the scanning result shows that the PCIE equipment does not exist, sending a warning message to the external equipment, and sending a warning through the external equipment, wherein the external equipment comprises at least one of display equipment and audio equipment.
In one embodiment, the processor, when executing the computer program, further performs the steps of: and when the scanning result is that the PCIE equipment does not exist, re-sending the scanning command to the PCIE controller after a preset time interval, returning to execute and receive the scanning result sent by the PCIE controller, and when the scanning result is that the PCIE equipment exists, establishing communication connection with the PCIE equipment.
In one embodiment, a computer-readable storage medium is provided, having a computer program stored thereon, which when executed by a processor, performs the steps of: monitoring the state of the PCIE equipment through the universal interface, and receiving a state exception message reported by the universal interface when the state of the PCIE equipment is abnormal; responding to the abnormal state message, sending a scanning command to the PCIE controller, so that the PCIE controller scans the PCIE bus according to the scanning command to obtain a scanning result of the PCIE equipment; and receiving a scanning result sent by the PCIE controller, and establishing communication connection with the PCIE equipment when the scanning result indicates that the PCIE equipment exists.
In one embodiment, the computer program when executed by the processor further performs the steps of: calling a GPIO (general purpose input/output) driven setting interface, and setting the GPIO interface into an interrupt mode through the GPIO driven setting interface, so that when the state of the PCIE (peripheral component interface express) equipment is abnormal, the GPIO interface is triggered to be interrupted; and when the GPIO interface is interrupted, receiving an interruption message reported by the GPIO interface, and determining that the state of the PCIE equipment is abnormal according to the interruption message.
In one embodiment, the computer program when executed by the processor further performs the steps of: and calling a GPIO driving setting interface, and setting the GPIO interface to be in an uninterrupted state.
In one embodiment, the computer program when executed by the processor further performs the steps of: carrying out data monitoring on a USB interface, wherein the USB interface is reset when the state of the PCIE equipment is abnormal; and receiving a reset message of the USB interface, and determining that the state of the PCIE equipment is abnormal according to the reset message.
In one embodiment, the computer program when executed by the processor further performs the steps of: and when the abnormal state message is received, sending a warning message to an external device, and sending a warning through the external device, wherein the external device comprises at least one of a display device and an audio device.
In one embodiment, the computer program when executed by the processor further performs the steps of: and when the scanning result shows that the PCIE equipment does not exist, sending a warning message to the external equipment, and sending a warning through the external equipment, wherein the external equipment comprises at least one of display equipment and audio equipment.
In one embodiment, the computer program when executed by the processor further performs the steps of: and when the scanning result is that the PCIE equipment does not exist, re-sending the scanning command to the PCIE controller after a preset time interval, returning to execute and receive the scanning result sent by the PCIE controller, and when the scanning result is that the PCIE equipment exists, establishing communication connection with the PCIE equipment.
It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by hardware instructions of a computer program, which can be stored in a non-volatile computer-readable storage medium, and when executed, can include the processes of the embodiments of the methods described above. Any reference to memory, storage, database or other medium used in the embodiments provided herein can include at least one of non-volatile and volatile memory. Non-volatile Memory may include Read-Only Memory (ROM), magnetic tape, floppy disk, flash Memory, optical storage, or the like. Volatile Memory can include Random Access Memory (RAM) or external cache Memory. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM), among others.
The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.

Claims (10)

1. A PCIE device control method is characterized in that the method comprises the following steps:
monitoring the state of the PCIE equipment through a general interface, and receiving a state exception message reported by the general interface when the state of the PCIE equipment is abnormal;
responding to the state exception message, sending a scanning command to the PCIE controller, so that the PCIE controller scans the PCIE bus according to the scanning command to obtain a scanning result of the PCIE equipment;
and receiving a scanning result sent by the PCIE controller, and establishing communication connection with the PCIE equipment when the scanning result is that the PCIE equipment exists.
2. The method according to claim 1, wherein the generic interface includes a GPIO interface, and before the monitoring of the state of the PCIE device via the generic interface and when the state of the PCIE device is abnormal, receiving a state exception message reported by the generic interface, the method further includes:
calling a GPIO (general purpose input/output) driven setting interface, and setting the GPIO interface into an interrupt mode through the GPIO driven setting interface, so that when the state of the PCIE (peripheral component interface express) equipment is abnormal, the GPIO interface is triggered to be interrupted;
the monitoring of the state of the PCIE device through the universal interface, and when the state of the PCIE device is abnormal, the receiving of a state abnormality message reported by the universal interface includes:
and when the GPIO interface is interrupted, receiving an interruption message reported by the GPIO interface, and determining that the state of the PCIE equipment is abnormal according to the interruption message.
3. The method according to claim 2, wherein after the receiving of the scan result sent by the PCIE controller and when the scan result is that the PCIE device exists, and after establishing a communication connection with the PCIE device, the method further comprises:
and calling a setting interface driven by the GPIO, and setting the GPIO interface to be in a non-interrupt state.
4. The method according to claim 1, wherein the generic interface includes a USB interface, the monitoring the state of the PCIE device through the generic interface, and when the state of the PCIE device is abnormal, the receiving a state exception message reported by the generic interface includes:
monitoring data of the USB interface, wherein the USB interface is reset when the state of the PCIE equipment is abnormal;
and receiving a reset message of the USB interface, and determining that the state of the PCIE equipment is abnormal according to the reset message.
5. The method of claim 1, further comprising:
and when the abnormal state message is received, sending a warning message to an external device, and sending a warning through the external device, wherein the external device comprises at least one of a display device and an audio device.
6. The method of claim 1, further comprising:
and when the scanning result indicates that the PCIE equipment does not exist, sending a warning message to external equipment, and sending a warning through the external equipment, wherein the external equipment comprises at least one of display equipment and audio equipment.
7. The method of claim 1, further comprising:
and when the scanning result is that the PCIE equipment does not exist, sending a scanning command to the PCIE controller again after a preset time interval, returning to execute the step of receiving the scanning result sent by the PCIE controller, and when the scanning result is that the PCIE equipment exists, establishing communication connection with the PCIE equipment.
8. A PCIE device control apparatus, comprising:
the PCIE equipment state monitoring module is used for monitoring the state of the PCIE equipment through a general interface, and receiving a state exception message reported by the general interface when the state of the PCIE equipment is abnormal;
a scan command sending module, configured to send a scan command to the PCIE controller in response to the status exception message, so that the PCIE controller scans the PCIE bus according to the scan command to obtain a scan result of the PCIE device;
and the communication connection establishing module is used for receiving a scanning result sent by the PCIE controller, and establishing communication connection with the PCIE equipment when the scanning result indicates that the PCIE equipment exists.
9. A computer device comprising a memory and a processor, the memory storing a computer program, characterized in that the processor, when executing the computer program, implements the steps of the method of any of claims 1 to 7.
10. A computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, carries out the steps of the method of any one of claims 1 to 7.
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