JP2022185768A - Information processing device and recovery method - Google Patents

Abstract

To continue utilization of an information processing device when recovering a management unit that manages the information processing device from a failure.SOLUTION: A management unit includes an image processing part which performs image processing and manages an information processing device. A monitoring unit monitors the management unit and outputs an abnormality detection signal when an abnormality in the management unit is detected. An information processing unit performs information processing, separates the image processing part on the basis of the abnormality detection signal when the abnormality detection signal is output from the monitoring unit and reboots the management unit.SELECTED DRAWING: Figure 2

Description

The present invention relates to recovery technology.

2. Description of the Related Art During operation of a server system, a failure may occur in which a BMC (Baseboard Management Controller) in the server hangs up due to a firmware or hardware problem. The frequency of BMC failures is, for example, about several per year.

BMC is a control IC (Integrated Circuit) chip for managing the server from a remote terminal. A remote terminal can acquire information about the hardware in the server and remotely operate the hardware via the BMC. Even if the BMC hangs up, the operation of the server will not be hindered, but it will hinder acquisition of hardware information and remote operation.

A system for resetting the BMC or another component of the server system is known in connection with the BMC recovery operation (see, for example, Patent Document 1). There is also known a stall monitoring device that allows a computer system to continue operating even when a stall occurs in a controller such as BMC without duplicating a controller such as BMC (see, for example, Patent Document 2).

JP 2019-125339 A JP 2011-204046 A

In the BMC recovery work, the BMC is reset. Since the BMC also incorporates a VGA (Video Graphics Array) chip used by the operating system (OS), resetting the BMC affects the OS as well, causing anomalies in server system operations. Therefore, the BMC is reset after stopping the entire server system including the OS.

Thus, the BMC restoration work is a large-scale work. In the customer's server system, when the BMC hangs up, a worker goes to the installation location of the server system and performs the BMC restoration work. Therefore, every time the BMC hangs up, the worker has to go to the customer's site, and it takes a long time to restore the BMC. If the operation of the server system is stopped for a long time due to recovery work, the impact on the customer's business will be great.

This problem is not limited to failure of the BMC, but occurs when failure occurs in various management units that manage the information processing apparatus (computer).

An object of the present invention is to continue the operation of an information processing device when restoring a management unit that manages the information processing device from a failure.

In one scheme, the information processing device includes a management unit, a monitoring unit, and an information processing unit. The management unit includes an image processing unit that performs image processing, and manages the information processing device. The monitoring unit monitors the management unit, and outputs an abnormality detection signal when detecting an abnormality in the management unit. The information processing section performs information processing, and when an abnormality detection signal is output from the monitoring section, disconnects the image processing section based on the abnormality detection signal, and restarts the management section.

According to one aspect, the operation of the information processing device can be continued when the management unit that manages the information processing device recovers from the failure.

It is a hardware block diagram of the server in the server system of a comparative example. 1 is a functional configuration diagram of an information processing apparatus according to an embodiment; FIG. 4 is a flowchart of recovery processing; 1 is a hardware configuration diagram of a server system according to an embodiment; FIG. 3 is a hardware configuration diagram of a server in the server system of the embodiment; FIG. It is a figure which shows the restoration processing of BMC. 10 is a flowchart (part 1) of a first recovery process; FIG. 11 is a flowchart (part 2) of the first recovery process; FIG. FIG. 11 is a flowchart (part 3) of the first recovery process; FIG. FIG. 11 is a flowchart (part 4) of the first recovery process; FIG. FIG. 11 is a flowchart (part 1) of second recovery processing; FIG. FIG. 11 is a flowchart (part 2) of a second recovery process; FIG. FIG. 11 is a flowchart (part 1) of a third recovery process; FIG. FIG. 11 is a flowchart (part 2) of the third recovery process; FIG. FIG. 11 is a flowchart (part 3) of a third recovery process; FIG. FIG. 11 is a flowchart (part 4) of the third recovery process; FIG. FIG. 11 is a flowchart (part 1) of a fourth recovery process; FIG. FIG. 11 is a flowchart (part 2) of a fourth recovery process; FIG. FIG. 11 is a flowchart (part 3) of a fourth recovery process; FIG. FIG. 11 is a flowchart (part 4) of a fourth recovery process; FIG.

Hereinafter, embodiments will be described in detail with reference to the drawings.

FIG. 1 shows an example hardware configuration of a server in a server system of a comparative example. The server 101 of FIG. 1 includes a BMC 111 , a chipset 112 and a CPU (Central Processing Unit) 113 , and the BMC 111 includes a VGA 121 . These components are hardware. The VGA 121 and chipset 112 are connected by a PCI-E (Peripheral Component Interconnect-Express) bus 122 .

In addition to the server 101, the server system may include other devices such as RAID (Redundant Arrays of Inexpensive Disks) devices and tape devices.

The CPU 113 executes a basic input/output system (BIOS) 131 and an OS 132 . OS 132 includes VGA driver 141 . The OS 132 accesses the VGA 121 using the VGA driver 141 to cause the VGA 121 to perform image processing such as video redirection.

In the recovery work of the BMC 111, when the BMC 111 is reset, the VGA 121 is also reset. When the VGA 121 is reset, the CPU 113 connected to the VGA 121 via the PCI-E bus 122 and the chipset 112 detects timeout of access to the VGA 121 and stops the execution of the OS 132 . Therefore, the screen of the OS 132 is no longer displayed on the display device of the remote terminal.

Although it is possible to disconnect the VGA 121 from the OS 132 using the PCI Hotplug function, the OS 132 does not detect that the BMC 111 has hung up, so the VGA 121 is not disconnected. Also, since the BMC 111 has a role of monitoring the server 101 independently of the OS 132, there is no mechanism for separating the BMC 111 from the OS 132. FIG.

Therefore, in the server 101 of FIG. 1, the recovery work of the BMC 111 is performed in the following procedure.

(P1) A problem occurs in the Web UI (User Interface) of the remote terminal, and the operator notices the occurrence of an abnormality.

(P2) The worker goes to the installation place (server room, etc.) of the server system and checks the LED (Light Emitting Diode) of the server 101 . Since the LED has changed from lit to extinguished, it is found that the BMC 111 is abnormal.

(P3) The operator stops the OS 132 after finishing all processes being executed by the server 101 .

(P4) The operator shuts down the server system by turning off the power of each device other than the server 101 .

(P5) The operator resets the BMC 111 .

(P6) The operator confirms the result of resetting on the monitoring screen. If the result is normal, proceed to the work of (P7), and if the result is abnormal, request maintenance work.

(P7) The operator activates the server system by turning on the power of each device.

Since the BMC 111 is reset after stopping the entire server system including the OS 132 in this manner, the operator has to go to a server room or the like, and it takes a long time until the BMC 111 is restored.

FIG. 2 shows a functional configuration example of the information processing apparatus according to the embodiment. The information processing device 201 in FIG. 2 includes a management unit 211 , a monitoring unit 212 and an information processing unit 213 . The management unit 211 includes an image processing unit 221 that performs image processing, and manages the information processing device 201 .

FIG. 3 is a flowchart showing an example of recovery processing performed by the information processing apparatus 201 of FIG. The information processing section 213 performs information processing (step 301). The monitoring unit 212 monitors the management unit 211 and outputs an abnormality detection signal when detecting an abnormality in the management unit 211 .

When the abnormality detection signal is output from the monitoring section 212, the information processing section 213 disconnects the image processing section 221 based on the abnormality detection signal (step 302), and restarts the management section 211 (step 303).

According to the information processing device 201 of FIG. 2, the operation of the information processing device 201 can be continued when the management unit 211 that manages the information processing device 201 is restored from a failure.

FIG. 4 shows a hardware configuration example of the server system of the embodiment. The server system of FIG. 4 includes a server 401 and RAID devices 402 . A server 401 corresponds to the information processing apparatus 201 in FIG. The server 401 and RAID device 402 are connected by a communication network.

RAID device 402 stores data used by server 401 . The RAID device 402 is an example of an auxiliary storage device. The server 401 performs information processing using data stored in the RAID device 402 and stores the processing result in the RAID device 402 .

FIG. 5 shows a hardware configuration example of the server 401 in FIG. The server 401 of FIG. 5 includes a BMC 511 , a chipset 512 , a CPU 513 , a monitoring circuit 514 , a memory 515 and a communication circuit 516 . BMC511 includes VGA521. These components are hardware. The CPU 513 may also be called a processor.

The BMC 511, CPU 513, monitoring circuit 514, and VGA 521 correspond to the management unit 211, information processing unit 213, monitoring unit 212, and image processing unit 221 in FIG. 2, respectively. The monitoring circuit 514 is, for example, a CPLD (Complex Programmable Logic Device).

The CPU 513 , memory 515 and communication circuit 516 are connected to the chipset 512 , and the monitoring circuit 514 is connected to the BMC 511 and chipset 512 . VGA 521 and chipset 512 are connected by PCI-E bus 522 .

The memory 515 is, for example, a semiconductor memory such as a RAM (Random Access Memory), and stores programs and data used for information processing. Communication circuitry 516 is connected to a communication network and communicates with RAID device 402 .

The CPU 513 acquires data from the RAID device 402 via the communication circuit 516 and stores the acquired data in the memory 515 . The CPU 513 then performs information processing by executing a program using the data stored in the memory 515 and transmits the processing result to the RAID device 402 via the communication circuit 516 .

BMC 511 manages server 401 . A remote terminal (not shown) can acquire information about the hardware in the server 401 and remotely operate the hardware via the BMC 511 . The VGA 521 performs image processing such as video redirection.

The CPU 513 executes the BIOS 531 and the OS 532 when performing information processing. The BIOS 531 is an example of the first program, and the OS 532 is an example of the second program.

BIOS 531 includes an interrupt handling routine 541 . The interrupt processing routine 541 includes processing for generating an interrupt request to the OS 532 and processing for checking the state of communication between the CPU 513 and the VGA 521 . The interrupt handling routine 541 is sometimes called an interrupt service routine.

OS 532 includes VGA driver 542 . The OS 532 accesses the VGA 521 using the VGA driver 542 to cause the VGA 521 to perform image processing. Also, the OS 532 can disconnect the VGA 521 from the OS 532 using the PCI Hotplug function of the VGA driver 542 .

Since the BIOS 531 can communicate with the OS 532, when the BMC 511 hangs up, the BIOS 531 can notify the OS 532 of the BMC 511 abnormality. However, the BIOS 531 does not monitor the BMC 511 and does not recognize the state of the BMC 511 . Therefore, a monitoring circuit 514 is provided to detect an abnormality in the BMC 511 .

A monitoring circuit 514 monitors the BMC 511 with a watchdog function. The monitoring circuit 514 transmits an inquiry signal to the BMC 511 and checks whether or not a response signal is received from the BMC 511 within a predetermined period. When the response signal is not received within the predetermined period, the monitoring circuit 514 determines that an abnormality has occurred in the BMC 511 . Thereby, an abnormality of the BMC 511 can be detected.

When an abnormality of the BMC 511 is detected, the monitoring circuit 514 outputs an interrupt request to the BIOS 531 to the CPU 513 via the chipset 512 . The interrupt request to the BIOS 531 is an example of the first interrupt request to the first program and corresponds to the abnormality detection signal.

The CPU 513 generates an interrupt request to the OS 532 by executing the interrupt processing routine 541 of the BIOS 531 based on the interrupt request from the monitor circuit 514 . The interrupt request to OS 532 is an example of a second interrupt request to the second program.

The CPU 513 disconnects the VGA 521 from the PCI-E bus 522 by using the VGA driver 542 of the OS 532 based on the interrupt request from the interrupt processing routine 541 .

The process of disconnecting the VGA 521 from the CPU 513 represents the process of changing the communication state between the CPU 513 and the VGA 521 from a communicable state to a communicable state. A state in which communication is possible corresponds to link up, and a state in which communication is not possible corresponds to link down.

By outputting an interrupt request to the BIOS 531 by the monitoring circuit 514 , it is possible to notify the BIOS 531 of an abnormality in the BMC 511 . Further, the interrupt processing routine 541 of the BIOS 531 generates an interrupt request to the OS 532, so that the OS 532 can be notified of the abnormality of the BMC 511. FIG.

After outputting the interrupt request to the BIOS 531 , the monitor circuit 514 outputs the next interrupt request to the BIOS 531 to the CPU 513 via the chipset 512 . The next interrupt request to BIOS 531 is an example of the third interrupt request to the first program.

The CPU 513 checks the communication state between the CPU 513 and the VGA 521 by executing the interrupt processing routine 541 based on the next interrupt request from the monitoring circuit 514 . Then, when the communication state is communication disabled, the CPU 513 restarts the BMC 511 by resetting the BMC 511 .

When the monitor circuit 514 outputs the next interrupt request to the BIOS 531, the interrupt processing routine 541 can check whether the VGA 521 has been disconnected. By resetting the BMC 511 when the VGA 521 is disconnected, the BMC 511 can be restarted without affecting the OS 532 .

FIG. 6 shows an example of recovery processing of the BMC 511 in the server 401 of FIG. The recovery process is performed in the following procedure.

(P11) The monitoring circuit 514 periodically monitors the BMC 511 by the watchdog function.

(P12) An abnormality occurs in the BMC 511 and the BMC 511 hangs up.

(P13) Since no response signal is received from the BMC 511 within the predetermined period, the monitoring circuit 514 determines that an abnormality has occurred in the BMC 511 and outputs the first interrupt request for the BIOS 531 to the CPU 513 . After that, the monitor circuit 514 periodically outputs an interrupt request for the BIOS 531 to the CPU 513 .

(P14) The CPU 513 generates an interrupt request to the OS 532 by executing the interrupt processing routine 541 based on the first interrupt request from the monitoring circuit 514 . As a result, the CPU 513 requests the OS 532 to disconnect the VGA 521 .

(P15) The CPU 513 disconnects the VGA 521 from the CPU 513 using the VGA driver 542 of the OS 532 based on the interrupt request from the interrupt processing routine 541 .

(P16) The CPU 513 checks whether or not the communication between the CPU 513 and the VGA 521 is linked down by executing the interrupt processing routine 541 based on the interrupt request periodically output from the monitoring circuit 514. do.

(P17) When the communication between the CPU 513 and the VGA 521 is linked down, the CPU 513 determines that the VGA 521 is disconnected and resets the BMC 511 to restart the BMC 511 . The BMC 511 then resets the monitoring circuit 514 to stop outputting the interrupt request.

(P18) After being restarted, the BMC 511 outputs an interrupt request for the BIOS 531 to the CPU 513 . As a result, the BMC 511 requests the BIOS 531 to connect the VGA 521 .

(P19) The CPU 513 generates an interrupt request to the OS 532 by executing the interrupt processing routine 541 based on the interrupt request from the BMC 511 . As a result, the CPU 513 requests the OS 532 to connect the VGA 521 .

(P20) Based on the interrupt request from the interrupt processing routine 541, the CPU 513 connects the VGA 521 to the CPU 513 by incorporating the VGA 521 into the PCI-E bus 522 using the VGA driver 542 of the OS 532.

At (P16), the CPU 513 can check whether or not the communication link between the CPU 513 and the VGA 521 is down by the following procedure.

(P21) The CPU 513 acquires a list of PCI devices using commands such as lspci and PCI device info, or library functions. A PCI device represents a device that is incorporated into the PCI-E bus 522 .

(P22) The CPU 513 searches for the VGA 521 from the list of PCI devices.

(P23) When the VGA 521 is included in the list of PCI devices, the CPU 513 determines that the communication is not linked down, and repeats the processing after (P21).

(P24) If the VGA 521 is not included in the list of PCI devices, the CPU 513 determines that the communication link is down.

According to the server 401 of FIG. 5, by providing the monitoring circuit 514 and the interrupt processing routine 541, an abnormality of the BMC 511 can be detected and notified to the OS 532, and the BMC 511 can be automatically recovered from the failure. Become.

Since it is not necessary for the worker to go to a server room or the like to perform the restoration work when performing the restoration processing, there is no waiting time until the start of the restoration work. In addition, since the server system does not need to be stopped and the BMC 511 is reset when active, the server system can continue to operate even during recovery processing.

Since it is enough to add the monitoring circuit 514 as new hardware, the restoration process of FIG. 6 can be easily applied to the existing server system. In addition, recovery processing can be easily implemented by using interrupt processing of the BIOS 531 and OS 532 .

Next, restoration processing of the BMC 511 in the server 401 of FIG. 5 will be described in more detail with reference to FIGS. 7A to 10D. Hereinafter, processing performed by the CPU 513 executing the OS 532 may be described as processing performed by the OS 532 . Also, the processing performed by the CPU 513 executing the interrupt processing routine 541 of the BIOS 531 may be described as processing performed by the interrupt processing routine 541 .

7A to 7D are flowcharts showing an example of the first restoration process when the OS 532 is running. First, the user turns on the server 401 (step 701). This activates the BMC 511 (step 702), and the server 401 checks whether or not activation of the BMC 511 has failed (step 703).

If the activation of the BMC 511 fails (step 703, YES), the server 401 outputs an alarm (step 724) and terminates the process. On the other hand, if the BMC 511 is successfully activated (step 703 , NO), the BMC 511 starts managing the server 401 . The BMC 511 then activates the monitoring circuit 514 (step 704) and checks whether activation of the monitoring circuit 514 has failed (step 705).

If the activation of the monitoring circuit 514 fails (step 705, YES), the server 401 outputs an alarm (step 724) and terminates the process. On the other hand, if the monitor circuit 514 is successfully activated (step 705, NO), the monitor circuit 514 starts the watchdog function (step 706) and checks whether the start of the watchdog function has failed (step 706). 707).

If the watchdog function fails to start (step 707, YES), the server 401 outputs an alarm (step 724) and terminates the process. On the other hand, if the watchdog function has successfully started (step 707, NO), the CPU 513 activates the OS 532 (step 708). As a result, the OS 532 is activated (step 731), and the CPU 513 checks whether or not activation of the OS 532 has failed (step 732).

If the OS 532 fails to boot (step 732, YES), the CPU 513 outputs an alarm (step 736) and terminates the process. On the other hand, if the OS 532 has successfully started (step 732 , NO), the CPU 513 executes the OS 532 .

Next, monitor circuit 514 transmits an inquiry signal to BMC 511 (step 709), and checks whether or not a response signal is received from BMC 511 within a predetermined period (step 710). If the response signal is received within the predetermined period (step 710, YES), the monitoring circuit 514 repeats the processing from step 709 onwards.

On the other hand, if the response signal is not received within the predetermined period (step 710, NO), the monitor circuit 514 outputs an interrupt request for the BIOS 531 to the CPU 513 (step 711). The interrupt processing routine 541 activated by the interrupt request to the BIOS 531 outputs an interrupt request to the OS 532 (step 712).

The OS 532 accepts the interrupt request to the OS 532 (step 733), and disconnects the VGA 521 from the PCI-E bus 522 using the VGA driver 542 (step 734).

Next, an interrupt processing routine 541 is activated by an interrupt request periodically output from the monitoring circuit 514 . The activated interrupt processing routine 541 activates a timer and repeatedly determines whether or not the communication between the CPU 513 and the VGA 521 is linked down for a certain period of time.

In determining link down, the interrupt processing routine 541 obtains a list of PCI devices using a command or library function (step 713), and checks whether or not timeout has occurred (step 714).

If it has not timed out (step 714, NO), the interrupt processing routine 541 searches for the VGA 521 from the list of PCI devices (step 715). If the VGA 521 is included in the list of PCI devices (step 715, YES), the interrupt processing routine 541 repeats the processing from step 713 onwards.

On the other hand, if VGA 521 is not included in the list of PCI devices (step 715, NO), interrupt processing routine 541 determines that communication between CPU 513 and VGA 521 is down, and resets BMC 511 ( step 716). Then, the server 401 checks whether the reset of the BMC 511 has failed (step 717).

If the reset of the BMC 511 fails (step 717, YES), the server 401 outputs an alarm (step 724) and terminates the process. On the other hand, if the reset of the BMC 511 succeeds (step 717, NO), the BMC 511 resets the monitoring circuit 514 (step 718) and checks whether the resetting of the monitoring circuit 514 has failed (step 719).

If the reset of the monitoring circuit 514 fails (step 719, YES), the server 401 outputs an alarm (step 724) and terminates the process. On the other hand, if the monitor circuit 514 has been successfully reset (step 719, NO), the monitor circuit 514 starts the watchdog function (step 720) and checks whether the start of the watchdog function has failed (step 721).

If the watchdog function fails to start (step 721, YES), the server 401 outputs an alarm (step 724) and terminates the process. On the other hand, if the watchdog function has successfully started (step 721, NO), the BMC 511 outputs an interrupt request for the BIOS 531 to the CPU 513 (step 722). The interrupt processing routine 541 activated by the interrupt request to the BIOS 531 outputs an interrupt request to the OS 532 (step 723).

OS 532 incorporates VGA 521 into PCI-E bus 522 using VGA driver 542 based on the interrupt request to OS 532 (step 735).

If a timeout has occurred in determining whether the link is down (step 714, YES), the server 401 forcibly resets the BMC 511 by performing the processing from step 716 onward.

8A and 8B are flowcharts showing an example of the second recovery process when the OS 532 has stopped. The processing of steps 801 to 823 is the same as the processing of steps 701 to 707 and 709 to 715 in FIG. 7A and steps 716 to 724 in FIG. 7B.

Unlike the first recovery process, when the watchdog function has successfully started (step 807, NO), the OS 532 is not activated and remains stopped. Therefore, when an interrupt request to the OS 532 is output from the interrupt processing routine 541 in step 811, the interrupt request is pending. Then, when the OS 532 is booted, the pending interrupt request is cleared.

Similarly, when an interrupt request to the OS 532 is output from the interrupt processing routine 541 in step 822, the interrupt request is also pending. Then, when the OS 532 is booted, the pending interrupt request is cleared.

Since the OS 532 is stopped, the disconnection of the VGA 521 is not performed, and a timeout occurs in determining whether the link is down (step 813, YES). Therefore, the processing after step 815 is performed, and the BMC 511 is forcibly reset.

9A to 9D are flowcharts showing an example of the third restoration process when there is no response from the OS 532. FIG. The processing of steps 901 to 924 is similar to the processing of steps 701 to 715 in FIG. 7A and steps 716 to 724 in FIG. 7B. Also, the processing of steps 931, 932, and 934 is the same as the processing of steps 731 and 732 in FIG. 7C and step 736 in FIG. 7D.

Unlike the first recovery process, if the OS 532 is successfully booted (step 932, NO), the booted OS 532 hangs up (step 933) and becomes unresponsive. Therefore, when an interrupt request to the OS 532 is output from the interrupt processing routine 541 in step 912, the interrupt request is pending. Then, the next time OS 532 is booted, the pending interrupt request is cleared.

Similarly, when an interrupt request to the OS 532 is output from the interrupt processing routine 541 in step 923, the interrupt request is also pending. Then, the next time OS 532 is booted, the pending interrupt request is cleared.

Since the OS 532 is hung up, the disconnection of the VGA 521 is not performed, and a timeout occurs in determining whether the link is down (step 914, YES). Therefore, the processing after step 916 is performed, and the BMC 511 is forcibly reset.

10A to 10D are flowcharts showing an example of the fourth recovery process when disconnection of the VGA 521 fails. The processing of steps 1001 to 1024 is the same as the processing of steps 701 to 715 in FIG. 7A and steps 716 to 724 in FIG. 7B. Also, the processing of steps 1031 to 1036 is the same as the processing of steps 731 to 734 in FIG. 7C and steps 735 and 736 in FIG. 7D.

Unlike the first recovery process, OS 532 attempts to disconnect VGA 521 from PCI-E bus 522 using VGA driver 542 after accepting an interrupt request to OS 532 (step 1033), but fails to disconnect. (step 1034). Therefore, a time-out occurs in determining whether the link is down (step 1014, YES), and the processing from step 1016 onwards is performed, and the BMC 511 is forcibly reset.

After that, when an interrupt request to the OS 532 is output from the interrupt processing routine 541 (step 1023 ), the OS 532 uses the VGA driver 542 to try to incorporate the VGA 521 into the PCI-E bus 522 . However, since the VGA 521 has not been disconnected, the OS 532 fails to incorporate the VGA 521 (step 1035).

The configuration of the information processing apparatus 201 in FIG. 2 is merely an example, and some components may be omitted or changed according to the application or conditions of the information processing apparatus 201. FIG. The configuration of the server system in FIG. 4 is merely an example, and some components may be omitted or changed according to the usage or conditions of the server system. For example, a server system may include multiple servers and may include other devices such as tape devices.

The configurations of the server 101 in FIG. 1 and the server 401 in FIG. 5 are merely examples, and some components may be omitted or changed according to the configuration or conditions of the server system. For example, if the server 401 in FIG. 5 does not communicate with the RAID device 402, the communication circuit 516 can be omitted.

The flowcharts of FIGS. 3 and 7A to 10D are merely examples, and some of the processes may be omitted or changed according to the configuration or conditions of the server system. The recovery processing of the BMC 511 shown in FIG. 6 is merely an example, and part of the processing may be omitted or changed according to the configuration or conditions of the server system.

Although the disclosed embodiments and their advantages have been described in detail, those skilled in the art can make various modifications, additions and omissions without departing from the scope of the invention as defined in the claims. deaf.

The following remarks are further disclosed with respect to the embodiments described with reference to FIGS. 1-10D.
(Appendix 1)
An information processing device that performs information processing,
a management unit that includes an image processing unit that performs image processing and manages the information processing device;
a monitoring unit that monitors the management unit and outputs an abnormality detection signal when an abnormality in the management unit is detected;
an information processing unit that performs the information processing and, when the abnormality detection signal is output from the monitoring unit, disconnects the image processing unit based on the abnormality detection signal and restarts the management unit;
An information processing device comprising:
(Appendix 2)
The information processing unit executes a first program and a second program,
The monitoring unit outputs a first interrupt request for the first program to the information processing unit as the abnormality detection signal,
Supplementary Note 1, wherein the information processing section generates a second interrupt request for the second program based on the first interrupt request, and disconnects the image processing section based on the second interrupt request. information processing equipment.
(Appendix 3)
After outputting the first interrupt request, the monitoring unit outputs a third interrupt request for the first program to the information processing unit,
The information processing unit checks a communication state between the information processing unit and the image processing unit based on the third interrupt request, and restarts the management unit when the communication state indicates that communication is impossible. The information processing apparatus according to Supplementary Note 2, wherein:
(Appendix 4)
The information processing apparatus according to appendix 2 or 3, wherein the first program is a basic input/output system, and the second program is an operating system.
(Appendix 5)
The monitoring unit transmits an inquiry signal to the management unit, and if it does not receive a response signal from the management unit within a predetermined period, determines that an abnormality has occurred in the management unit, and outputs the abnormality detection signal. The information processing apparatus according to any one of Appendices 1 to 4, characterized by:
(Appendix 6)
process information,
A management unit that manages an information processing apparatus including an image processing unit that performs image processing is monitored by a monitoring unit, and if the monitoring unit detects an abnormality in the management unit and outputs an abnormality detection signal, the abnormality disconnecting the image processing unit based on the detection signal;
restarting the management unit;
A recovery method characterized in that a processor executes processing.
(Appendix 7)
The process of performing information processing includes a process of executing a first program and a second program,
The monitoring unit outputs a first interrupt request to the first program as the abnormality detection signal,
The process of separating the image processing unit includes:
a process of generating a second interrupt request for the second program based on the first interrupt request;
7. The recovery method according to claim 6, further comprising a process of disconnecting the image processing unit based on the second interrupt request.
(Appendix 8)
After outputting the first interrupt request, the monitoring unit outputs a third interrupt request for the first program,
based on the third interrupt request, the processor further performs a process of checking a communication state between the processor and the image processing unit;
The recovery method according to appendix 7, wherein the process of restarting the management unit includes a process of restarting the management unit when the communication state indicates that communication is impossible.
(Appendix 9)
The recovery method according to appendix 7 or 8, wherein the first program is a basic input/output system, and the second program is an operating system.
(Appendix 10)
The monitoring unit transmits an inquiry signal to the management unit, and if it does not receive a response signal from the management unit within a predetermined period, determines that an abnormality has occurred in the management unit, and outputs the abnormality detection signal. 10. The recovery method according to any one of appendices 6 to 9, characterized by:

101, 401 Server 111, 511 BMC
112, 512 Chipset 113, 513 CPU
121, 521 VGA
122, 522 PCI-E bus 131, 531 BIOS
132, 532 OS
141, 542 VGA driver 201 information processing device 211 management unit 212 monitoring unit 213 information processing unit 221 image processing unit 401 server 402 RAID device 514 monitoring circuit 515 memory 516 communication circuit 541 interrupt processing routine

Claims (6)

An information processing device that performs information processing,
a management unit that includes an image processing unit that performs image processing and manages the information processing device;
a monitoring unit that monitors the management unit and outputs an abnormality detection signal when an abnormality in the management unit is detected;
an information processing unit that performs the information processing and, when the abnormality detection signal is output from the monitoring unit, disconnects the image processing unit based on the abnormality detection signal and restarts the management unit;
An information processing device comprising: The information processing unit executes a first program and a second program,
The monitoring unit outputs a first interrupt request for the first program to the information processing unit as the abnormality detection signal,
2. The information processing section generates a second interrupt request for the second program based on the first interrupt request, and disconnects the image processing section based on the second interrupt request. The information processing device described. After outputting the first interrupt request, the monitoring unit outputs a third interrupt request for the first program to the information processing unit,
The information processing unit checks a communication state between the information processing unit and the image processing unit based on the third interrupt request, and restarts the management unit when the communication state indicates that communication is impossible. 3. The information processing apparatus according to claim 2, wherein: 4. An information processing apparatus according to claim 2, wherein said first program is a basic input/output system, and said second program is an operating system. The monitoring unit transmits an inquiry signal to the management unit, and if it does not receive a response signal from the management unit within a predetermined period, determines that an abnormality has occurred in the management unit, and outputs the abnormality detection signal. 5. The information processing apparatus according to any one of claims 1 to 4, characterized by: process information,
A management unit that manages an information processing apparatus including an image processing unit that performs image processing is monitored by a monitoring unit, and if the monitoring unit detects an abnormality in the management unit and outputs an abnormality detection signal, the abnormality disconnecting the image processing unit based on the detection signal;
restarting the management unit;
A recovery method characterized in that a processor executes processing.

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