CN111198704A - FPGA remote upgrading system based on TCP protocol - Google Patents
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Abstract
The invention discloses a TCP (transmission control protocol) -based FPGA (field programmable gate array) remote upgrading system, which comprises a client application program, a client side module and a server side module, wherein the client application program is used for sending an FPGA configuration file to a server side raspberry group 3B + upper computer module; the server-side raspberry pi 3B + upper computer module is used for receiving the FPGA configuration file and forwarding the FPGA configuration file to the server-side FPGA; the server side FPGA embedded soft core MicroBlaze module is used for receiving the FPGA configuration file and writing the FPGA configuration file into the server side Flash module; the server side Flash storage module is used for storing the FPGA configuration program; the server-side FPGA reconfiguration module is used for sending an FPGA reconfiguration instruction; the server-side DDR3 memory module is used as a memory of the server-side FPGA embedded soft core MicroBlaze module; the power supply module is used for supplying power to the raspberry group 3B + upper computer module and the server end FPGA; and the clock module is used for providing a system clock for the FPGA at the server end. The invention remotely upgrades the FPGA through the Internet based on the TCP protocol, saves manpower and material resources, and has higher flexibility, practicability and universality.
Description
Technical Field
The invention belongs to the field of communication, and particularly relates to a TCP (transmission control protocol) -based FPGA (field programmable gate array) remote upgrading system.
Background
With the increasing number of logic units of the FPGA and the increasing speed, more and more products use the FPGA as a main processing chip or an acceleration chip. Because the FPGA can be programmed for many times, the product can be upgraded subsequently after being released. The traditional method for upgrading the FPGA program is to solidify the FPGA configuration program into Flash through a JTAG interface, however, the method needs technicians to upgrade each product on site, so that not only is the efforts of the technicians consumed, but also the timely upgrading of all products is difficult. Thus, there is an urgent need for a technique to remotely upgrade FPGA-based products.
The TCP protocol is a protocol of a transport layer in a TCP/IP protocol cluster, is widely applied to the current Internet, is a connection-oriented transport layer communication protocol based on byte streams, and has high reliability. Compared with another protocol UDP in the transport layer, the TCP protocol is characterized in that the client and the server are required to establish connection through three-way handshake, and the connection-oriented characteristic provides guarantee for the reliability of the TCP protocol. TCP may be implemented through socket programming.
The transmission of the FPGA configuration program is not allowed to have a little error, otherwise, the configuration will fail, and therefore, it is very suitable to use the TCP protocol with high reliability as the transport layer protocol.
Disclosure of Invention
The invention aims to provide the FPGA remote upgrading system which can realize the configuration of the server FPGA by multiple clients and has the characteristics of low cost, high flexibility, practicability, universality and the like.
The technical solution for realizing the purpose of the invention is as follows: a FPGA remote upgrading system based on a TCP protocol comprises a client application program, a server-side raspberry pi 3B + upper computer module, a server-side FPGA embedded soft core MicroBlaze module, a server-side Flash storage module, a server-side FPGA reconfiguration module, a server-side DDR3 storage module, a power supply module and a clock module;
the client application program is used for sending the FPGA configuration file to the server-side raspberry sending 3B + upper computer module;
the server-side raspberry pi 3B + upper computer module is used for receiving the FPGA configuration file sent by the client-side application program and forwarding the FPGA configuration file to the server-side FPGA;
the server-side FPGA embedded soft core MicroBlaze module is used for receiving an FPGA configuration file sent by the server-side raspberry pi 3B + upper computer module and writing the FPGA configuration file into the server-side Flash module;
the server-side Flash storage module is used for storing an FPGA configuration program;
the server-side FPGA reconfiguration module is used for sending an FPGA reconfiguration instruction, and then the server-side FPGA reads an FPGA configuration program from the server-side Flash storage module to realize reconfiguration;
the server-side DDR3 memory module is used as a memory of the server-side FPGA embedded soft core MicroBlaze module;
the power supply module is used for supplying power to the server-side raspberry pi 3B + upper computer module and the server-side FPGA;
and the clock module is used for providing a stable system clock for the FPGA at the server end.
Compared with the prior art, the invention has the following remarkable advantages: 1) by adopting a client/server mode, a plurality of clients can configure the server FPGA, so that the practicability and the universality of the system are improved; 2) compared with local upgrading and upgrading in the same local area network, the remote upgrading is carried out by adopting the Internet, the upgrading can be carried out at any time and any place, the flexibility is higher, and manpower and material resources are saved; 3) and the raspberry pi 3B + is used as a server-side upper computer, so that the cost of the system is saved.
The present invention is described in further detail below with reference to the attached drawing figures.
Drawings
FIG. 1 is a block diagram of a TCP protocol-based FPGA remote upgrade system of the present invention.
Fig. 2 is a block diagram of a clock module according to the present invention.
FIG. 3 is a block diagram of a server-side FPGA embedded soft core MicroBlaze module according to the present invention.
FIG. 4 is a connection block diagram of a server-side Flash storage module and an FPGA configuration circuit in the invention.
Detailed Description
With reference to fig. 1, the present invention provides a TCP protocol-based FPGA remote upgrade system, which includes a client application program, a server-side raspberry pi 3B + upper computer module, a server-side FPGA embedded soft core MicroBlaze module, a server-side Flash storage module, a server-side FPGA reconfiguration module, a server-side DDR3 storage module, a power supply module, and a clock module;
the client application program is used for sending the FPGA configuration file to the server-side raspberry sending 3B + upper computer module;
the server-side raspberry pi 3B + upper computer module is used for receiving the FPGA configuration file sent by the client-side application program and forwarding the FPGA configuration file to the server-side FPGA;
the server-side FPGA embedded soft core MicroBlaze module is used for receiving an FPGA configuration file sent by the server-side raspberry pi 3B + upper computer module and writing the FPGA configuration file into the server-side Flash module;
the server side Flash storage module is used for storing the FPGA configuration program;
the server-side FPGA reconfiguration module is used for sending an FPGA reconfiguration instruction, and then the server-side FPGA reads an FPGA configuration program from the server-side Flash storage module to realize reconfiguration;
the server-side DDR3 memory module is used as a memory of the server-side FPGA embedded soft core MicroBlaze module;
the power supply module is used for supplying power to the server-side raspberry group 3B + upper computer module and the server-side FPGA;
and the clock module is used for providing a stable system clock for the FPGA at the server end.
Further, in one embodiment, the client application program runs in a Windows operating system, and is responsible for reading in the FPGA configuration file generated by Vivado in a binary form, and sending the FPGA configuration file to the server-side raspberry pi 3B + upper computer module through the internet by using a TCP protocol.
As a specific example, the workflow of the client application is:
(1) reading an FPGA configuration file generated by Vivado in a binary system mode;
(2) creating a socket and connecting the socket to an address of a server side;
(3) dividing the FPGA configuration file into a plurality of configuration data packets, sequentially sending the configuration data packets to a server side, and returning a packet for displaying the configuration progress by the server side after the sending is finished;
(4) the client application closes the socket after configuration is complete.
Further, in one embodiment, the server-side raspberry pi 3B + host module includes a piece of raspberry pi 3B +, the raspberry pi 3B + has a WiFi network and a gigabit ethernet interface. The server-side raspberry 3B + upper computer module receives the FPGA configuration file sent by the client-side application program through WiFi, reads the FPGA configuration file in a binary system mode, divides the FPGA configuration file into a plurality of configuration data packets, and sends the configuration data packets to the server-side FPGA packet by packet through gigabit Ethernet.
As a specific example, the workflow of the server-side raspberry pi 3B + upper computer module is as follows:
(1) the raspberry pi 3B + is connected to the Internet by using a WiFi network, and serves as a server to receive the FPGA configuration file sent by the client application program and store the configuration file locally;
(2) after the whole FPGA configuration file is received and the error is confirmed, the configuration file is read in a binary mode and is divided into a plurality of 1024-byte packets;
(3) the data packets are sent to the FPGA through the gigabit Ethernet one by one as an upper computer, a response packet of the FPGA needs to be waited for each time one data packet is sent, the response packet contains information whether the FPGA successfully receives the data packet, if the response packet is successfully received, the upper computer starts to send the next data packet, and if the reception fails, the upper computer resends the current data packet.
(4) And (4) repeating the step (3) until all the data packets are sent.
As a specific example, the server-side FPGA adopts a main control board which takes an FPGA with a Xilinx Virtex-7 model as a main chip.
Further, in one embodiment, in conjunction with fig. 2, the clock module comprises:
the clock chip is used for generating a stable clock;
the configuration module of the clock chip is used for configuring the working parameters of the clock chip;
and the reset module is used for restoring the clock chip to the original state.
As a specific example, the clock module specifically employs a Si5344H chip.
As a specific example, the clock module works as follows:
(1) the FPGA board card provides a 25MHz clock crystal oscillator as a global clock of the main control chip;
(2) the FPGA chip accesses the clock into a clock buffer in the chip to increase the driving capability of the clock; then the clock is used as a driving clock on the SPI bus and is used for configuring a Si5344H clock chip;
(3) after the Si5344H clock chip is configured with working parameters, an externally input clock signal is used as an input signal, a system clock is output to the FPGA chip through a frequency multiplier and a frequency divider inside the chip, and a 125MHz clock is provided for the FPGA GTH.
Further, in one embodiment, the power module provides 1.0V and 1.8V for the server-side FPGA, and provides 5V for the server-side raspberry pi 3B + upper computer module.
Further, in one embodiment, the lwip protocol stack is transplanted to the server-side FPGA embedded soft core MicroBlaze module, and is responsible for establishing a TCP connection with the server-side raspberry pi 3B + upper computer module, receiving the FPGA configuration data packet sent by the server-side raspberry pi 3B + upper computer module through the gigabit ethernet, and writing the received configuration data packet into the server-side Flash storage module according to the received sequence.
Further, in one embodiment, with reference to fig. 3, the server-side FPGA embedded soft core MicroBlaze module includes:
the MicroBlaze kernel module is used for running an embedded program;
the clock reset management module is used for providing a clock and resetting for the whole MicroBlaze module;
the peripheral comprises an AXI SPI controller module, an AXI SPI controller module and an AXI MIG memory interface module;
the AXI Ethernet MAC module is used for receiving and transmitting data of a gigabit Ethernet data link layer;
the AXI SPI controller module is used for controlling an SPI time sequence so as to write the configuration data packet into the Flash storage module at the server end;
the AXI MIG memory interface module is used for realizing conversion between a DDR3 interface and an AXI interface and mounting DDR3 on a memory AXI bus.
As a specific example, each module in the server-side FPGA embedded soft core MicroBlaze module specifically has the following functions:
(1) MicroBlaze kernel module: the MicroBlaze core is a RISC processor soft core optimized by Xilinx corporation and capable of being embedded in an FPGA, and has strong configurability and expandability. The MicroBlaze kernel can realize the main functions of the TCP by transplanting a lwip protocol stack, wherein the lwip is a small TCP/IP protocol stack, occupies less memory and is suitable for embedded development.
(2) The clock reset management module: the clock reset module provides 100MHz clock for the MicroBlaze kernel, the interconnection module, the AXI SPI controller module and the AXI Ethernet MAC module and 200MHz clock for the AXI MIG memory interface module by multiplying the frequency of the system clock.
(3) An interconnection module: the interconnection module mounts an AXI SPI controller module and an AXI Ethernet MAC module onto an AXI peripheral bus of a MicroBlaze kernel, and mounts an AXI MIG memory interface module onto a data bus of the MicroBlaze kernel.
(4) AXI Ethernet MAC module: the AXI Ethernet MAC module realizes the transceiving of Ethernet MAC frames, the interface of the module and the PHY chip is an SGMII interface, and the SGMII interface needs to be realized by using an FPGA high-speed serial transceiver GTH. Since TCP packets are transmitted in IP packets, and IP packets are transmitted in MAC frames, the axithernet MAC module provides a basis for TCP packet transmission.
(5) AXI SPI controller module: the AXI SPI module is provided with two groups of interfaces, namely an AXI Lite interface and an SPI interface, wherein the AXI Lite interface is connected to an AXI peripheral bus of the MicroBlaze embedded soft core, and the SPI interface is connected to a pin of the serial SPIFlash. And the AXI SPI controller module outputs the FPGA configuration data in a time sequence of SPI serial for writing into the Flash storage module at the server end.
(6) AXI MIG memory interface module: the MIG memory interface module realizes the control of DDR3 interface time sequence and encapsulates the DDR3 interface time sequence into an AXI interface.
Further, in one embodiment, the server-side Flash storage module provides the FPGA configuration program when the system is powered on or after the server-side FPGA reconfiguration module gives a reconfiguration instruction.
Further, in one embodiment, with reference to fig. 4, the server-side Flash storage module includes a serial SPI Flash chip.
The serial SPI interface of Flash is used for writing data into and reading data out of a Flash chip in a serial mode, the SPI interface is provided with 4 pins which are D, Q, C and S respectively, a D pin of the SPI serial Flash is a serial data input pin, a Q pin of the SPI serial Flash is a serial data output pin, a C pin of the SPI serial Flash is a clock input pin, and an S pin of the SPI serial Flash is a chip selection pin. Configuring the FPGA by using a Master SPI configuration mode, wherein a pin D of the SPI serial Flash is required to be connected to a pin MOSI/D [00] on the FPGA chip, a pin Q of the SPI serial Flash is required to be connected to a pin DIN/D [01] on the FPGA chip, a pin C of the SPI serial Flash is required to be connected to a pin CCLK on the FPGA chip, a pin S of the SPI serial Flash is required to be connected to a pin FCS _ B on the FPGA chip, and meanwhile, the value M [2:0] on the FPGA chip is required to be set to be 001.
Further, in one embodiment, the server-side FPGA reconfiguration module specifically writes the complete FPGA configuration file into the server-side Flash module and then sends out the FPGA reconfiguration instruction.
Further, in one embodiment, the server-side FPGA reconfiguration module uses the ICAPE2 port to issue an internal reconfiguration instruction IPROG, the ICAPE2 is an FPGA internal configuration access port, and has 5 ports, which are O, CLK, CSIB, I, and RDWRB, respectively, the port CLK is a clock input port, the port I is a 32-bit data write-in port, the port O is a 32-bit data read-out port, the port RDWRB is a read-write selection port, and the port CSIB is an enable port. The server-side FPGA reconfiguration module starts to work after the AXI SPI controller module finishes writing configuration data into the serial SPI Flash chip, and sends out a series of instructions through an ICAPE2 port, wherein the sent instruction words are as follows:
(1)Dummy Word；
(2)Sync Word；
(3)Type 1NO OP；
(4)Type 1Write 1Words to WBSTAR；
(5)Warm Boot Start Address
(6)Type 1Write 1Words to CMD；
(7)IPROG Command；
(8)Type 1NO OP；
the commands (1) to (2) are used for sending synchronization words for data synchronization, the commands (3) to (5) are used for reading the initial address of the FPGA configuration data from the SPI Flash chip during writing reconfiguration, and the commands (6) to (8) are used for sending reconfiguration commands. When the FPGA configuration logic receives the IPROG command, resetting all resources except the reconfiguration special logic in the FPGA, pulling down the INIT _ B pin and the DONE pin, and after the resetting is completed, pulling up the INIT _ B pin again by the FPGA. When INIT _ B is pulled high, FPGA samples the value of M2: 0, and different configuration modes can be adopted according to the difference of M2: 0 values. Since the Flash chip used is read and written through the serial SPI interface, the value of M [2:0] is set to 001. After reading the value of M [2:0], the FPGA enters a Master SPI configuration mode. Pulling down the FCS _ B pin by the FPGA, and selecting the corresponding serial SPI Flash chip. Then, a command is sent to Flash through an MOSI/D [00] pin, an 8-bit read command is written first, then a 24-bit read address is written, and then a configuration data stream sent by a Flash chip is received through a DIN/D [01] pin. When the configuration is complete, the FPGA will pull up the FCS _ B pin, the MOSI/D [00] pin, and the DONE pin.
Further, in one embodiment, the server-side DDR3 memory module comprises one DDR3 granule.
In summary, the invention remotely upgrades the FPGA through the Internet based on the TCP protocol, and compared with local upgrading and upgrading in the same local area network, the invention can upgrade at any time and any place, has higher flexibility and saves manpower and material resources. In addition, through a client/server mode, a plurality of clients can configure the server FPGA, and the practicability and the universality of the system are improved.
Claims (10)
1. A TCP-protocol-based FPGA remote upgrading system is characterized by comprising a client application program, a server-side raspberry pi 3B + upper computer module, a server-side FPGA embedded soft core MicroBlaze module, a server-side Flash storage module, a server-side FPGA reconfiguration module, a server-side DDR3 storage module, a power supply module and a clock module;
the client application program is used for sending the FPGA configuration file to the server-side raspberry sending 3B + upper computer module;
the server-side raspberry pi 3B + upper computer module is used for receiving the FPGA configuration file sent by the client-side application program and forwarding the FPGA configuration file to the server-side FPGA;
the server-side FPGA embedded soft core MicroBlaze module is used for receiving an FPGA configuration file sent by the server-side raspberry pi 3B + upper computer module and writing the FPGA configuration file into the server-side Flash module;
the server-side Flash storage module is used for storing an FPGA configuration program;
the server-side FPGA reconfiguration module is used for sending an FPGA reconfiguration instruction, and then the server-side FPGA reads an FPGA configuration program from the server-side Flash storage module to realize reconfiguration;
the server-side DDR3 memory module is used as a memory of the server-side FPGA embedded soft core MicroBlaze module;
the power supply module is used for supplying power to the server-side raspberry pi 3B + upper computer module and the server-side FPGA;
and the clock module is used for providing a stable system clock for the FPGA at the server end.
2. The FPGA remote upgrading system based on the TCP protocol of claim 1, wherein the client application program runs in a Windows operating system and is responsible for reading in the FPGA configuration file generated by Vivado in a binary form and sending the FPGA configuration file to the server-side raspberry pi 3B + upper computer module in the TCP protocol through the Internet.
3. The FPGA remote upgrading system based on the TCP protocol of claim 1, wherein the server-side raspberry pi 3B + upper computer module receives the FPGA configuration file sent by the client application program through WiFi, reads the FPGA configuration file in a binary system form, then divides the FPGA configuration file into a plurality of configuration data packets, and sends the configuration data packets to the server-side FPGA packet by packet through gigabit Ethernet.
4. The FPGA remote upgrading system based on the TCP protocol of claim 1, wherein the server-side FPGA embedded soft core MicroBlaze module is transplanted with a lwip protocol stack and is responsible for establishing TCP connection with the server-side raspberry group 3B + upper computer module, receiving the FPGA configuration data packet sent by the server-side raspberry group 3B + upper computer module through a gigabit Ethernet, and writing the received configuration data packet into the server-side Flash storage module according to the received sequence.
5. The FPGA remote upgrading system based on the TCP protocol of claim 1 or 4, characterized in that the server-side FPGA embedded soft core MicroBlaze module comprises:
the MicroBlaze kernel module is used for running an embedded program;
the clock reset management module is used for providing a clock and resetting for the whole MicroBlaze module;
the peripheral comprises an AXI SPI controller module, an AXI SPI controller module and an AXI MIG memory interface module;
the AXI Ethernet MAC module is used for receiving and transmitting data of a gigabit Ethernet data link layer;
the AXI SPI controller module is used for controlling an SPI time sequence so as to write the FPGA configuration data packet into a Flash storage module at the server end;
the AXI MIG memory interface module is used for realizing conversion between a DDR3 interface and an AXI interface and mounting DDR3 on a memory AXI bus.
6. The FPGA remote upgrading system based on the TCP protocol of claim 1, characterized in that the server-side Flash storage module provides an FPGA configuration program when the system is powered on or after the server-side FPGA reconfiguration module gives a reconfiguration instruction.
7. The FPGA remote upgrade system based on the TCP protocol as claimed in claim 1, wherein the server-side FPGA reconfiguration module is specifically configured to issue the FPGA reconfiguration instruction after the server-side FPGA embedded soft core MicroBlaze module writes the complete FPGA configuration file into the server-side Flash module.
8. The FPGA remote upgrade system based on TCP protocol as claimed in claim 1, wherein the server DDR3 memory module comprises one DDR3 granule.
9. The FPGA remote upgrading system based on the TCP protocol of claim 1, wherein the power module provides 1.0V and 1.8V voltage for the FPGA at the server end and 5V voltage for the raspberry pi 3B + upper computer module at the server end.
10. The FPGA remote upgrade system based on TCP protocol of claim 1, characterized in that the clock module comprises:
the clock chip is used for generating a stable clock;
the configuration module of the clock chip is used for configuring the working parameters of the clock chip;
and the reset module is used for restoring the clock chip to the original state.
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| CN114327660A (en) * | 2021-12-30 | 2022-04-12 | 浙江大立科技股份有限公司 | External memory initialization method based on FPGA |
| CN114327660B (en) * | 2021-12-30 | 2024-01-30 | 浙江大立科技股份有限公司 | Initialization method of external memory based on FPGA |
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