CN112600937A - FPGA logic remote downloading method - Google Patents

Abstract

The invention discloses a remote downloading method for FPGA (field programmable gate array) logic, which comprises a server and a client, wherein the client is connected with the server through an Ethernet, the client is connected with the FPGA through a circuit, and the FPGA is also connected with a Flash memory; the method comprises the following steps: step (1), the client runs on a Windows operating system and sends an FPGA logic remote downloading request to the server; and (2) the server runs on a PowerPC chip and a VxWorks operating system, analyzes the FPGA logic remote downloading request sent by the client after receiving the FPGA logic remote downloading request, sends a command to the client, and returns a response state to the client after the command is sent. The invention can solve the problem of inflexible FPGA configuration brought by local FPGA logic downloading based on the JTAG mode at present to a certain extent.

Description

FPGA logic remote downloading method

Technical Field

The invention belongs to the field of electronic engineering and computer science, and particularly relates to a remote FPGA logic downloading method.

Background

As a highly parallel chip, FPGA is widely used in situations where real-time requirements are stringent. In the aspect of downloading FPGA logic programs, a JTAG local downloading method is generally adopted at present, but for many occasions without local downloading, the JTAG mode brings inconvenience, and therefore the invention provides an FPGA logic remote downloading method which can solve the problem of inflexible FPGA configuration brought by the current JTAG mode-based local FPGA logic downloading to a certain extent.

Disclosure of Invention

The technical problem to be solved by the invention is as follows: the invention provides a method for remotely downloading FPGA (field programmable gate array) logic, which is used for solving the problem of inflexible FPGA configuration brought by local FPGA logic downloading based on a JTAG (joint test action group) mode to a certain extent.

The technical problem to be solved by the invention is realized by adopting the following technical scheme: a remote FPGA logic downloading method comprises a server and a client, wherein the client is connected with the server through an Ethernet, the client is connected with an FPGA through a circuit, and the FPGA is also connected with a Flash memory; the method comprises the following steps:

step (1), the client runs on a Windows operating system and sends an FPGA logic remote downloading request to the server;

the server side runs on a PowerPC chip and a VxWorks operating system, analyzes the FPGA logic remote downloading request sent by the client side after receiving the FPGA logic remote downloading request, sends a command to the client side, and returns a response state to the client side after the command is sent;

and (3) the client side performs information returning, logic erasing, logic writing and reading operations on the FPGA according to the command.

Further, the server communicates with the client based on a predetermined protocol, where the predetermined protocol includes a frame header field, an operation code field, a data length field, a data field, a check code field, and a frame tail field, where the frame header field is hexadecimal 5AA5, and the length is two bytes; the operation code fields are hexadecimal 80, 81, 82 and 83 and respectively represent four functions of FPGA information, logic erasing, logic writing and logic reading; the data length field is two bytes and represents the length of the data field; the content of the data field is the effective load of the frame, and the unit is byte; the check code field is the lower sixteen bits of the mathematical sum of the operation code field, the data length field and the data field, and the length is 2 bytes; the end of frame field is hexadecimal a 55A.

Has the advantages that:

compared with the prior art, the invention has the advantages that: compared with a local FPGA logic downloading mode based on a JTAG mode, the method can realize the configuration of the FPGA in a remote mode and improve the flexibility of FPGA program downloading.

Drawings

FIG. 1 is a block diagram of the system architecture of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, rather than all embodiments, and all other embodiments obtained by a person skilled in the art based on the embodiments of the present invention belong to the protection scope of the present invention without creative efforts.

The invention provides a FPGA logic remote downloading method, as shown in figure 1, a system comprises a server and a client, wherein the client is connected with the server through an Ethernet, the client is connected with the FPGA through a circuit, and the FPGA is also connected with a Flash memory; the method comprises the following steps:

step (1), the client runs on a Windows operating system and sends an FPGA logic remote downloading request to the server;

the server side runs on a PowerPC chip and a VxWorks operating system, analyzes the FPGA logic remote downloading request sent by the client side after receiving the FPGA logic remote downloading request, sends a command to the client side, and returns a response state to the client side after the command is sent;

and (3) the client side performs information returning, logic erasing, logic writing and reading operations on the FPGA according to the command.

The server side and the client side communicate based on a predetermined protocol, wherein the predetermined protocol comprises a frame header field, an operation code field, a data length field, a data field, a check code field and a frame tail field, the frame header field is hexadecimal 5AA5, and the length of the frame header field is two bytes; the operation code fields are hexadecimal 80, 81, 82 and 83 and respectively represent four functions of FPGA information, logic erasing, logic writing and logic reading; the data length field is two bytes and represents the length of the data field; the content of the data field is the effective load of the frame, and the unit is byte; the check code field is the lower sixteen bits of the mathematical sum of the operation code field, the data length field and the data field, and the length is 2 bytes; the end of frame field is hexadecimal a 55A.

In summary, the present invention discloses a method for downloading FPGA logic remotely, which can solve the problem of inflexible FPGA configuration caused by the current local FPGA logic downloading based on the JTAG method to a certain extent.

Those skilled in the art will appreciate that the invention may be practiced without these specific details.

The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.

Claims (2)

1. A remote FPGA logic downloading method comprises a server and a client, wherein the client is connected with the server through an Ethernet, the client is connected with an FPGA through a circuit, and the FPGA is also connected with a Flash memory; the method is characterized by comprising the following steps:

step (1), the client runs on a Windows operating system and sends an FPGA logic remote downloading request to the server;

the server side runs on a PowerPC chip and a VxWorks operating system, analyzes the FPGA logic remote downloading request sent by the client side after receiving the FPGA logic remote downloading request, sends a command to the client side, and returns a response state to the client side after the command is sent;

and (3) the client side performs information returning, logic erasing, logic writing and reading operations on the FPGA according to the command.

2. The FPGA logic remote downloading method of claim 1,

the server side and the client side communicate based on a predetermined protocol, wherein the predetermined protocol comprises a frame header field, an operation code field, a data length field, a data field, a check code field and a frame tail field, the frame header field is hexadecimal 5AA5, and the length of the frame header field is two bytes; the operation code fields are hexadecimal 80, 81, 82 and 83 and respectively represent four functions of FPGA information, logic erasing, logic writing and logic reading; the data length field is two bytes and represents the length of the data field; the content of the data field is the effective load of the frame, and the unit is byte; the check code field is the lower sixteen bits of the mathematical sum of the operation code field, the data length field and the data field, and the length is 2 bytes; the end of frame field is hexadecimal a 55A.

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