CN115878351B

CN115878351B - Message transmission method and device, storage medium and electronic device

Info

Publication number: CN115878351B
Application number: CN202310199164.0A
Authority: CN
Inventors: 张海仑; 赵龙; 钟戟
Original assignee: Suzhou Inspur Intelligent Technology Co Ltd
Current assignee: Suzhou Inspur Intelligent Technology Co Ltd
Priority date: 2023-03-03
Filing date: 2023-03-03
Publication date: 2023-07-21
Anticipated expiration: 2043-03-03
Also published as: CN115878351A

Abstract

The embodiment of the application provides a message transmission method and device, a storage medium and an electronic device, wherein the message transmission method comprises the following steps: acquiring a target memory address, wherein the target memory address is a buffer area address of a target buffer area transmitted by a target transmission message to be transmitted; determining an identification value of an address identification corresponding to the target memory address according to the base address and the address unit size to obtain a target identification value; writing the target identification value into a message structure body of the target transmission message, and transmitting the target transmission message to a receiving end of the target transmission message. By the method, the device and the system for transmitting the inter-process communication messages, the problem that message transmission efficiency is low due to overlong messages to be transmitted in the related technology is solved.

Description

Message transmission method and device, storage medium and electronic device

Technical Field

The embodiment of the application relates to the field of computers, in particular to a message transmission method and device, a storage medium and an electronic device.

Background

Currently, for communication between different FUs (Function units), an Inter-process communication mode is generally adopted, and IPC (Inter-Process Communication ) messages are used as basic units. Each IPC message contains several parameters, where the memory address occupies a larger number of bits.

However, with the development of NAND (Not AND, NAND, i.e. computer flash memory device) technology, the number of memory addresses that need to be transferred by a multi-plane (i.e. memory matrix) read-write message is increasing, AND the length of the IPC message is correspondingly increased, so that the resources consumed when the IPC message is read-written are increased, thereby affecting the transmission efficiency of the message.

As can be seen, the transmission method of the inter-process communication message in the related art has a problem of low message transmission efficiency due to the excessively long message to be transmitted.

Disclosure of Invention

The embodiment of the application provides a message transmission method and device, a storage medium and an electronic device, which at least solve the problem of low message transmission efficiency caused by overlong message to be transmitted in the transmission method of an inter-process communication message in the related technology.

According to one embodiment of the present application, there is provided a method for transmitting a message, including: acquiring a target memory address, wherein the target memory address is a buffer area address of a target buffer area transmitted by a target transmission message to be transmitted; determining an identification value of an address identification corresponding to the target memory address according to the base address and the address unit size to obtain a target identification value; writing the target identification value into a message structure body of the target transmission message, and transmitting the target transmission message to a receiving end of the target transmission message.

According to another aspect of the embodiments of the present application, there is also provided a method for transmitting a message, including: receiving a target transmission message sent by a sending end; extracting a target identification value from a message structure body of the target transmission message, wherein the target identification value is an identification value of an address identification corresponding to a target memory address; and determining the target memory address according to the target identification value, the base address and the address unit size.

According to still another embodiment of the present application, there is provided a transmission apparatus for a message, including: the first acquisition unit is used for acquiring a target memory address, wherein the target memory address is a buffer area address of a target buffer area transmitted by a target transmission message to be transmitted; the first determining unit is used for determining an identification value of an address identification corresponding to the target memory address according to the base address and the size of the address unit to obtain a target identification value; and the first execution unit is used for writing the target identification value into a message structure body of the target transmission message and transmitting the target transmission message to a receiving end of the target transmission message.

According to still another embodiment of the present application, there is also provided a transmission apparatus for a message, including: the receiving unit is used for receiving the target transmission message sent by the sending end; an extracting unit, configured to extract a target identification value from a message structure body of the target transmission message, where the target identification value is an identification value of an address identifier corresponding to a target memory address; and the third determining unit is used for determining the target memory address according to the target identification value, the base address and the address unit size.

According to a further embodiment of the present application, there is also provided a computer readable storage medium having stored therein a computer program, wherein the computer program is arranged to perform the steps of any of the method embodiments described above when run.

According to a further embodiment of the present application, there is also provided an electronic device comprising a memory having stored therein a computer program and a processor arranged to run the computer program to perform the steps of any of the method embodiments described above.

By means of the method, a mode of reconstructing a storage format of a memory address stored in a message is adopted, and a target memory address is obtained, wherein the target memory address is a buffer address of a target buffer, transmitted by a target transmission message to be transmitted; determining an identification value of an address identification corresponding to a target memory address according to the base address and the size of the address unit to obtain a target identification value; the method comprises the steps of writing a target identification value into a message structure body of a target transmission message, and transmitting the target transmission message to a receiving end of the target transmission message, wherein the original memory address is stored in the message, but the identification value corresponding to the memory address is determined according to the predefined base address and address unit size (the original memory address can be restored according to the base address and address unit size), so that occupied space in the memory address can be effectively compressed, the purpose of shortening the length of the message to be transmitted can be achieved, the technical effect of improving the message transmission efficiency is achieved, and the problem that the message transmission efficiency is low due to overlong message to be transmitted in the inter-process communication message transmission method in the related technology is solved.

Drawings

FIG. 1 is a schematic diagram of a hardware environment of a method for transmitting messages according to an embodiment of the present application;

FIG. 2 is a flow chart of a method of transmitting a message according to an embodiment of the present application;

FIG. 3 is a flow chart of another method of message transmission according to an embodiment of the present application;

fig. 4 is a block diagram of a message transmission apparatus according to an embodiment of the present application;

fig. 5 is a block diagram of a transmission apparatus of another message according to an embodiment of the present application.

Detailed Description

Embodiments of the present application will be described in detail below with reference to the accompanying drawings in conjunction with the embodiments.

It should be noted that the terms "first," "second," and the like in the description and the claims of the embodiments of the present application and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order.

The method embodiments provided in the embodiments of the present application may be performed in a mobile terminal, a computer terminal or similar computing device. Taking a computer terminal as an example, fig. 1 is a schematic diagram of a hardware environment of a message transmission method according to an embodiment of the present application. As shown in fig. 1, the computer terminal may include one or more (only one is shown in fig. 1) processors 102 (the processor 102 may include, but is not limited to, a microprocessor MCU or a processing device such as a programmable logic device FPGA) and a memory 104 for storing data, wherein the computer terminal may further include a transmission device 106 for communication functions and an input-output device 108. It will be appreciated by those skilled in the art that the configuration shown in fig. 1 is merely illustrative and is not intended to limit the configuration of the computer terminal described above. For example, the computer terminal may also include more or fewer components than shown in FIG. 1, or have a different configuration than shown in FIG. 1.

The memory 104 may be used to store a computer program, for example, a software program of application software and a module, such as a computer program corresponding to a method of transmitting a message in the embodiment of the present application, and the processor 102 executes the computer program stored in the memory 104, thereby performing various functional applications and data processing, that is, implementing the method described above. Memory 104 may include high-speed random access memory, and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some examples, the memory 104 may further include memory remotely located relative to the processor 102, which may be connected to the mobile terminal via a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.

The transmission device 106 is used to receive or transmit data via a network. Specific examples of the network described above may include a wireless network provided by a communication provider of a computer terminal. In one example, the transmission device 106 includes a network adapter (Network Interface Controller, simply referred to as NIC) that can connect to other network devices through a base station to communicate with the internet. In one example, the transmission device 106 may be a Radio Frequency (RF) module, which is configured to communicate with the internet wirelessly.

According to an aspect of the embodiments of the present application, there is provided a method for transmitting a message, taking a method for transmitting a message in the present embodiment performed by a computer terminal as an example, fig. 2 is a flowchart of a method for transmitting a message according to the embodiments of the present application, as shown in fig. 2, the flowchart includes the following steps:

step S202, a target memory address is obtained, wherein the target memory address is a buffer address of a target buffer transmitted by a target transmission message to be transmitted.

The transmission method of the message in the present embodiment can be applied to a scenario in which communication is performed between different functional units FU within the same device. For Firmware FW (Firmware), communication between different FUs mainly adopts an inter-process communication manner, and different pipeline FIFOs (First Input First Output, first-in first-out) are defined by the FUs. IPC messages are used as the basic unit of inter-process communication, and their length is typically in dwords (Double words, each Word being 2 bytes long, 32 bits). Each IPC message may include a number of Dwords (e.g., 16 Dwords), where parameters such as a message source, a message destination, a message unique identifier, a message type, a message address, a plurality of buffers (memory addresses for storing data when reading and writing data), and the like are included.

In this embodiment, the target memory address may be acquired before the message is transmitted between the different functional units. Here, the target memory address may be a buffer address of the target buffer, i.e. the buffer address, transmitted by the target transmission message to be transmitted. The targeted transfer message may be the IPC message described previously.

Step S204, determining the identification value of the address identification corresponding to the target memory address according to the base address and the address unit size, and obtaining the target identification value.

In the IPC message, parameters other than the buffer address are simpler, and the number of occupied bits (bits) is smaller. An absolute buffer address in a 64-bit operating system contains 64 bits (i.e., occupies 2 dwords). A typical structure is as follows, where the buffer address occupies 9 Dwords:

typedef union

{

struct

{

u32 msgType : 8;

u32 flashChanQ : 4;

u32 chan : 5;

u32 outMsgQ : 4;

u32 reservedDW0B31_21 : 11;

u32 tag : 16;

u32 pageType : 3;

u32 read_type : 4;

u32 page_load_flag : 1;

u32 fast_read_flag : 1;

u32 inject_err_type : 3;

u32 reservedDW1B31_28 : 4;

u32 data_frame_offset : 11;

u32 data_frame_length : 11;

u32 buf_alloc_flag : 1;

u32 plane_bitmap : 4;

u32 df_bitmap : 16;

u32 reservedDW4B31_20 : 12;

u32 read_refs;

u32 eccCodeRateIndex : 4;

u32 reservedDW7B7_5 : 4;

u32 maxIter : 8;

u32 lLR0 : 8;

u32 lLR1 : 8;

u32 buffer_addr[9];

};

u32 dw[16];

} flash_read_t 。

the most basic operation of different FUs in communication with NCM (Nand Control Manager, flash control management) processes is reading, writing, erasing, etc., wherein the speed of reading and writing is critical, and the basic performance of the product is determined. However, with the development of NAND technology, one multi-plane read/write message needs to transfer more buffer addresses, and at this time, the IPC message length has to be increased significantly. In the inter-process communication, the IPC message needs to be written in one module and read out from another module, and after the message length is increased, more CPU (Central Processing Unit ) resources are consumed in reading and writing the IPC message. In addition, the IPC message sometimes needs to be forwarded in multiple layers in the transmission process among different FUs, and too long IPC message also causes great burden on a bus during message transmission, thereby affecting transmission performance and transmission efficiency.

In order to solve at least part of the above problems, in this embodiment, the format of the memory address recorded in the target transmission message may be reconstructed, and instead of directly recording the complete memory address, compression and optimization of the Dword number occupied by the memory address in the message structure are implemented by recording the identification value corresponding to the memory address.

In this embodiment, the identification value of the address identifier corresponding to the target memory address may be determined according to the base address and the address unit size, to obtain the target identification value. Here, the base address may be used as a starting address for the memory address. The target identification value may be used to identify a target memory address.

Alternatively, the target identification value may be related to the base address and address unit size according to the size of the target memory address. The base address and address unit size may be fixed values set in advance, that is, the base address and address unit size corresponding to each memory address may be the same.

Alternatively, the setting of the base address and the address unit may be performed once before each message transmission, or may be performed in a preparation stage such as when the memory is initialized, and accordingly, the setting of the base address and the address unit may be performed only once no matter how many times the message transmission is performed.

Step S206, the target identification value is written into the message structure body of the target transmission message, and the target transmission message is transmitted to the receiving end of the target transmission message.

The target transmission message to be transmitted may include a message structure for writing information carried in the message, and after the target identification value is obtained, the target identification value may be written into the message structure of the target transmission message, and the target transmission message may be transmitted to the receiving end of the target transmission message. The manner of transmitting the target transmission message may include a message structure of the transmission target transmission message, and may further include other information of the transmission target transmission message than the message structure. By writing the identification value corresponding to the memory address into the message structure body of the transmission message, compared with a mode of transmitting the direct address, the purpose of reducing the number of bits occupied by the memory address in the transmission message can be achieved, so that the length of the transmission message (namely, the number of occupied bits) can be reduced, and the bandwidth utilization rate is improved.

Here, the message structure of the target transmission message may include a plurality of parameters, and the order and position of the plurality of parameters may be set in advance. Each of the plurality of parameters may correspond to a field in the message structure, each of the plurality of parameters may correspond to one or more bits, i.e., occupy one or more bits, and the number of bits occupied by each of the plurality of parameters may be fixed or may be set for different transmission messages. The target memory address may belong to one of a plurality of parameters, and the target identification value may be written in a writing position corresponding to the target memory address in the message structure.

Through the steps, the target memory address is obtained, wherein the target memory address is a buffer address of a target buffer, which is transmitted by a target transmission message to be transmitted; determining an identification value of an address identification corresponding to a target memory address according to the base address and the size of the address unit to obtain a target identification value; the method comprises the steps of writing the target identification value into a message structure body of the target transmission message, and transmitting the target transmission message to a receiving end of the target transmission message, so that the problem of low message transmission efficiency caused by overlong message to be transmitted in a transmission method of the inter-process communication message in the related technology can be solved, and the technical effect of improving the message transmission performance is achieved.

In an exemplary embodiment, before determining the identification value of the address identification corresponding to the target memory address according to the base address and the address unit size, the method further includes: and acquiring the base address and the address unit size, wherein the base address and the address unit size are set in the process of initializing the memory.

The base address and address unit size may be obtained prior to determining the target identification value. Here, the base address and address unit size may be set during the memory initialization process. Memory initialization refers to the initialization of a memory that manages data for multiple processes.

By the embodiment, the setting of the base address and the address unit is completed in the process of initializing the memory, so that the waste of individual resources for setting the base address and the address unit can be avoided, and the utilization rate of the resources is improved.

In an exemplary embodiment, the above method further comprises: the minimum value of the buffer address is set as the base address, and the minimum unit between the memory addresses is set as the address unit size.

In setting the base address and the address unit size, the minimum value of the buffer address may be set as the base address, and the minimum unit between the storage addresses may be set as the address unit size. For example, when the memory is initialized, baseAddr (base address) and UnitSize (address unit size) are defined, the BaseAddr adopts the minimum value of the buffer address used, and the UnitSize is the minimum unit between storage addresses.

Optionally, the address unit size is the length of the address unit (or the bit number occupied by the address unit), and setting the minimum unit between the storage addresses to the address unit size refers to: setting the size of the minimum unit between the storage addresses as the address unit size, wherein the address unit is the minimum unit between the storage addresses.

By setting the minimum value of the buffer address as the base address and setting the minimum unit between the storage addresses as the address unit size, the applicability of the base address and the address unit size to all memory addresses can be improved.

In one exemplary embodiment, obtaining the base address and address unit size includes: the base address and address cell size are read from a preset register.

In this embodiment, for the base address and the address unit size, the base address and the address unit size may be stored in a preset register after definition is completed under the condition of hardware support, for example, when the memory is initialized, the base address and the address unit size are set, and the set base address and address unit size are stored in the preset register. Correspondingly, the base address and the address unit size can be read from a preset register when the message is transmitted. Here, the preset register may be a register which is preset and may include a flip-flop having a memory function.

The preset registers may be allowed to be set, modified, etc. only at the time of memory initialization, or not allowed to be set, modified, etc. during message transmission. In this case, after the base address and the address unit size are stored in the preset register, the base address and the address unit size can be read from the preset register when different sender wants to transmit the transmission message. Optionally, to avoid information acquisition collision, the preset register allows only one process to read data at the same time, and at the same time, does not allow other processes to read data from the preset register when reading data. Alternatively, the preset register may allow multiple processes to read data at the same time, where data read conflicts may be avoided in one or more ways, e.g., information in the preset register may only be read, modification may not be allowed, etc. This is not limited in this embodiment.

It should be noted that, when transmitting the transmission message, different processes can read the base address and the address unit size from the preset register, and the base address and the address unit size read by different processes may be the same.

By reading the base address and the address unit size from the register, the base address and the address unit size can be conveniently obtained, and therefore convenience in information obtaining is improved.

In an exemplary embodiment, determining an identification value of an address identifier corresponding to a target memory address according to a base address and an address unit size, to obtain a target identification value includes: determining an address offset between a target memory address and a base address to obtain a target offset; and determining a target identification value of the address identification corresponding to the target memory address according to the target offset and the address unit size.

Because the actual address of the memory address can be determined by the base address and the offset address, when determining the target identification value, considering the unique function (positioning arrangement) of the base address, the address offset between the target memory address and the base address can be determined first to obtain the target offset, and then the target identification value of the address identification corresponding to the target memory address is determined according to the target offset and the address unit size. The target offset may be the difference between the sizes of the target memory address and the base address, i.e., the offset address.

According to the embodiment, the identification value corresponding to the memory address is determined according to the relation between the offset of the memory address and the base address and the size of the address unit, so that the association between the identification value and the memory address can be improved, and the memory address of the receiving end transmitting the message can be conveniently acquired.

In one exemplary embodiment, determining a target identification value of an address identification corresponding to a target memory address according to a target offset and an address unit size includes: and determining a quotient obtained by dividing the target offset by the size of the address unit as a target identification value of the address identification corresponding to the target memory address.

In this embodiment, since the address unit size may be the smallest unit between memory addresses, each address stored may be considered to occupy an integer number of address units, i.e., the size of each address is an integer multiple of the address unit size. The quotient of the target offset divided by the address unit size may be determined as a target identification value of the address identification corresponding to the target memory address.

For example, after the sender acquires the BufferAddr, the relative offset of the BufferAddr with respect to the base address is calculated, and the offset value bufferand= (BufferAddr-BaseAddr)/UnitSize, the bufferand obtained after the calculation generally does not exceed 12bits.

According to the embodiment, the identification value corresponding to the memory address is determined according to the quotient of the offset of the memory address and the base address and the size of the address unit, so that the convenience of determining the identification value can be improved.

In an exemplary embodiment, the above method further comprises: and determining a parameter value of a buffer length parameter corresponding to the target memory address according to the buffer size and the address unit size of the target buffer to obtain a target length value. Correspondingly, writing the target identification value to a message structure of the target transmission message comprises: the target identification value and the target length value are written to a message structure of the target transfer message.

In order to facilitate the receiving end of the target transmission message to accurately determine the complete information of the buffer area corresponding to the target memory address, the length value corresponding to the target memory address may also be written into the message structure body of the target transmission message. In this embodiment, the parameter value of the buffer length parameter corresponding to the target memory address may be determined according to the buffer size and the address unit size of the target buffer, to obtain the target length value.

The target length value may be written to the message structure of the target transfer message at the same time as the target identification value is written to the message structure of the target transfer message. For example, the sender may fill the acquired bufferId, bufferLength into the IPC message structure.

Alternatively, the target identification value and the target length value may be contiguous as a memory address parameter in the message structure of the target transfer message. The target identification value may be before, the target length value may be after, or the target length value may be before, and the target identification value may be after, which is not limited in this embodiment. Here, the address identifier may be used to identify a memory address (absolute address) of the buffer, and the buffer length parameter (or buffer length identifier) may be used to identify a buffer size of the buffer, from which the corresponding buffer may be determined.

By the embodiment, the length value corresponding to the memory address and the identification value corresponding to the memory address are written into the message structure body together, so that the positioning boundary of the buffer area can be improved, and the accuracy of information transmission is provided.

In an exemplary embodiment, determining a parameter value of a buffer length parameter corresponding to a target memory address according to a buffer size and an address unit size of a target buffer to obtain a target length value includes: and determining a quotient obtained by dividing the buffer size of the target buffer by the address unit size as a target length value of a buffer length parameter corresponding to the target memory address.

In this embodiment, when determining the length value corresponding to the target memory address, the quotient obtained by dividing the buffer size of the target buffer by the address unit size may be determined as the target length value of the buffer length parameter corresponding to the target memory address. Here, the length value corresponding to the memory address refers to the length value of the buffer length parameter corresponding to the memory address, that is, the size of the buffer corresponding to the memory address can be identified.

For example, the buffer length (a parameter that can be used to identify the buffer size) can be obtained by dividing the buffer size that needs to be transmitted by UnitSize, and the occupied bits are generally smaller.

According to the embodiment, the quotient of the buffer size of the buffer and the address unit size is determined as the length value written in the message structure body, so that the receiving end can conveniently determine complete buffer information according to the preset address unit size, and the accuracy of message transmission is improved.

In one exemplary embodiment, writing a target identification value and a target length value to a message structure of a target transfer message includes: and writing the target identification value and the target length value into a message structure body of the target transmission message according to the bit number occupied by the target identification value and the bit number occupied by the target length value.

For the determined target identification value and target length value, the bit numbers of the target identification value and the target length value in the message structure body of the target transmission message can be respectively determined, and the target identification value and the target length value are written into the message structure body of the target transmission message according to the bit numbers occupied by the target identification value and the target length value.

According to the embodiment, writing in the message structure body is completed according to the bit number occupied by the identification value and the length value, so that the bit number occupied by the memory address in the message structure body can be effectively reduced, and the purpose of reducing the message length is achieved.

In an exemplary embodiment, the above method further comprises: and dynamically adjusting the number of bits occupied by the target identification value and the number of bits occupied by the target length value according to the number of bits occupied by the target memory address.

The number of bits occupied by the target identification value and the target length value in the message structure body of the target transmission message can be dynamically adjusted according to the actual scene. In this embodiment, the number of bits occupied by the target identifier value and the number of bits occupied by the target length value may be dynamically adjusted according to the number of bits occupied by the target memory address.

Optionally, the number of bits occupied by the target identification value and the number of bits occupied by the target length may be determined in advance by the transmitting end and the receiving end according to the current transmission environment and by combining the sizes of the corresponding parameters such as the memory address, etc.

For example, to facilitate obtaining information carried in a transmission message, one Dword may store two sets of bufferld and bufferLength, where more addresses may be stored under the same message length.

According to the embodiment, the number of bits occupied by the identification value and the number of bits occupied by the length value are dynamically adjusted, so that more memory addresses can be transmitted without increasing the message length, and the utilization rate of the message structure body is improved.

In one exemplary embodiment, dynamically adjusting the number of bits occupied by the target identification value and the number of bits occupied by the target length value according to the number of bits occupied by the target memory address includes: and determining the product of the number of bits occupied by the target memory address and the preset proportion as the number of bits occupied by the target identification value, and determining the difference value of the number of bits occupied by the target memory address and the number of bits occupied by the target identification value as the number of bits occupied by the target length value.

For the dynamic adjustment of the number of bits occupied by the identification value and the length value, a proportion, that is, a preset proportion, may be preset, and the number of bits occupied by the identification value and the number of bits occupied by the length value may be determined by calculating according to the preset proportion. In this embodiment, the product of the number of bits occupied by the target memory address and the preset ratio may be determined as the number of bits occupied by the target identification value, and the difference between the number of bits occupied by the target memory address and the number of bits occupied by the target identification value may be determined as the number of bits occupied by the target length value.

For example, when the obtained bufferId, bufferLength is filled into the IPC message structure, the number of bits occupied by each buffer can be dynamically adjusted according to the number of bits occupied by the buffer, for example, the buffer id occupies 12bits and the buffer length occupies 4bits.

According to the embodiment, the dynamic adjustment of the bit number occupied by the identification value and the length value is realized through the preset proportion, so that the adjustment efficiency can be improved, and the message transmission efficiency is improved.

In an exemplary embodiment, determining an identification value of an address identifier corresponding to a target memory address according to a base address and an address unit size, to obtain a target identification value includes: when the target memory address comprises a plurality of memory addresses, determining an identification value of an address identification corresponding to each memory address in the plurality of memory addresses according to the base address and the address unit size, and obtaining an identification value corresponding to each memory address, wherein the target identification value comprises the identification value corresponding to each memory address.

Because the number of address information in the NAND technology and the capacity of the NAND are in positive correlation, the IPC message generally includes a plurality of memory addresses, in this embodiment, when the target memory address includes a plurality of memory addresses, the target identification value may include an identification value corresponding to each memory address, and according to the base address and the address unit size, the identification value of the address identifier corresponding to each memory address in the plurality of memory addresses may be determined respectively, so as to obtain the identification value corresponding to each memory address.

Alternatively, the address offset between the memory address and the base address may be determined in the manner of determining the target identifier value, and the quotient obtained by dividing the address offset by the address unit size may be determined as the identifier value of the address identifier corresponding to the memory address.

Alternatively, while determining the identification value corresponding to each memory address, the length value corresponding to each memory address may be determined according to the method for determining the target length value described above, and written into the message structure of the target transmission message together with the corresponding identification value.

According to the embodiment, under the condition that a plurality of memory addresses exist, the identification value corresponding to each memory address is determined according to the base address and the address unit size, so that the identification rate of the receiving end to the plurality of memory addresses can be improved, and the accuracy of memory address transmission is improved.

In one exemplary embodiment, retrieving a target memory address includes: and obtaining the absolute address of the target buffer area to obtain the target memory address.

In order to avoid the occurrence of address failure of the memory address in the message transmission process due to chain breakage or the like, in this embodiment, the memory address transmitted in the target transmission message may be an absolute address, that is, an absolute location of the file. Fetching the target memory address may refer to fetching an absolute address of the target buffer.

By the embodiment, the absolute address is obtained as the memory address to be transmitted, address failure caused by the change of the connection position can be avoided, and the validity of memory address transmission can be improved.

According to another aspect of the embodiments of the present application, there is also provided a transmission method of a message, which may be a transmission message for receiving and processing a transmission message generated and transmitted by the transmission method of a message provided in the foregoing embodiments. Taking the transmission method of the message in the present embodiment performed by the computer terminal as an example, fig. 3 is a flowchart of another transmission method of the message according to the embodiment of the present application, as shown in fig. 3, the flowchart includes the following steps:

step S302, receiving a target transmission message sent by a sender.

In this embodiment, in the inter-process communication, for a receiving end of a transmission message, for example, a receiving end of a target transmission message, it may receive the target transmission message sent by the sending end. Here, the received target transmission message may be generated by the transmitting end and the target identification value is written in the message structure body thereof.

Step S304, extracting a target identification value from the message structure body of the target transmission message, wherein the target identification value is the identification value of the address identification corresponding to the target memory address.

After the receiving end receives the target transmission message, the target identification value may be extracted from the message structure of the target transmission message. Here, the target identification value may be an identification value of an address identification corresponding to the target memory address, which may be extracted from a designated field or a designated location of a message structure of the target transfer message, and may be fixed in length or variable, which may be extracted from a designated field or a designated location of a message structure of the target transfer message based on the number of bits occupied, the end identification, or other information.

Optionally, the address identifier of the corresponding target memory address may be determined according to the extracted target identifier value, so as to determine the memory address that the sender wants to transmit.

Optionally, if the message structure body is written with the target identifier value and the length value corresponding to the target memory address, that is, the target length value, the target identifier value is extracted, and at the same time, the corresponding target length value may be extracted, so as to determine the buffer (i.e., buffer) corresponding to the target memory address according to the target length value and the target length value.

Step S306, determining the target memory address according to the target identification value, the base address and the address unit size.

Alternatively, the receiving end may acquire the base address and the address unit size in the same or similar manner as the transmitting end acquires the base address and the address unit size, and the specific acquiring manner may refer to the description of the foregoing embodiment, which is not described herein.

After the target identification value is extracted, the target memory address can be determined according to the acquired base address and address unit size and combining the target identification value. The manner of determining the target memory address may correspond to the manner of generating the target memory address in the foregoing embodiment.

Through the steps, the target transmission message sent by the sending end is received; extracting a target identification value from a message structure body of a target transmission message, wherein the target identification value is an identification value of an address identification corresponding to a target memory address; according to the target identification value, the base address and the address unit size, the target memory address is determined, so that the problem of low message transmission efficiency caused by overlong messages to be transmitted in the transmission method of the inter-process communication messages in the related technology can be solved, and the technical effect of improving the message transmission performance is achieved.

In one exemplary embodiment, extracting the target identification value from the message structure of the target transfer message includes: determining the number of bits occupied by a target identification value and the number of bits occupied by a target length value, wherein the target length value is a parameter value of a buffer zone length parameter corresponding to a target memory address, and is used for identifying the buffer zone size of a target buffer zone corresponding to the target memory address; and extracting the target identification value and the target length value from the message structure body of the target transmission message according to the bit number occupied by the target identification value and the bit number occupied by the target length value.

Because each parameter in the target transmission message may be a message structure written in different positions and bit numbers, when the target identification value and the target length value are written in the message structure of the target transmission message, the mode of extracting the target identification value and the target length value may be to determine the bit number occupied by the target identification value and the bit number occupied by the target length value first, and then extract the target identification value and the target length value from the message structure of the target transmission message according to the bit number occupied by the target identification value and the bit number occupied by the target length value. Here, the target length value is a parameter value of a buffer length parameter corresponding to the target memory address, and the target length value is used to identify a buffer size of the target buffer corresponding to the target memory address.

Alternatively, the number of bits occupied by the target identifier value and the number of bits occupied by the target length value may be sent by the sending end to the receiving end while the target transmission message is being sent, and correspondingly, may be implemented by sending the foregoing preset proportion or the like. In addition, the number of bits occupied by the target identification value and the number of bits occupied by the target length value may be determined by both the receiving end and the transmitting end before the message transmission, that is, the receiving end knows the number of bits occupied by the target identification value and the number of bits occupied by the target length value, without the transmitting end informing.

According to the embodiment, the identification value and the target length value are extracted according to the bit number occupied by the identification value and the bit number occupied by the length value, so that the accuracy of acquiring the identification value and the length value can be improved.

In one exemplary embodiment, determining the target memory address based on the target identification value, the base address, and the address unit size includes: and determining the sum of the product of the target identification value and the size of the address unit and the base address as the target memory address.

In this embodiment, the target identifier may be a quotient obtained by dividing an address offset between the target memory address and the base address by the address unit size (i.e., bufferid= (BufferAddr-BaseAddr)/UnitSize), and the receiving end may determine the sum of the product of the target identifier and the address unit size and the base address as the target memory address, i.e., determine the target memory address according to a calculation formula bufferaddr=bufferid ×unitsize+baseaddr.

According to the embodiment, the memory address is determined according to the product of the identification value and the size of the address unit and the sum of the identification value and the base address, so that the accuracy of the transmission of the target memory address can be improved while the number of bits in the target transmission message of the target memory address is reduced.

In an exemplary embodiment, after determining the target memory address according to the target identification value, the base address and the address unit size, the method further includes: performing validity check on the target memory address to obtain a validity check result; under the condition that the validity check result indicates that the target memory address is legal, the target memory address is saved, and the target transmission message is released; and under the condition that the validity check result indicates that the target memory address is illegal, sending message abnormality indication information to the sending end and releasing the target transmission message, wherein the message abnormality indication information is used for indicating that the memory address transmitted in the target transmission message is abnormal.

In order to improve the security of message transmission and avoid the influence on the receiving end caused by the condition that the transmitted memory address is illegal, in this embodiment, after the target memory address is determined, the target memory address can be subjected to validity check, and a validity check result is obtained.

And under the condition that the validity check result indicates that the target memory address is legal, the target memory address can be saved, and the target transmission message is released. And under the condition that the validity check result indicates that the target memory address is illegal, the message abnormality indication information can be sent to the sending end, and the target transmission message is released. Here, the message abnormality indication information may be used to indicate that the memory address transmitted in the target transmission message is abnormal.

For example, taking the target transmission message as an IPC message as an example, after obtaining the BufferAddr, the receiving end may perform parameter checking on the BufferAddr, directly use the BufferAddr and release the IPC message if the BufferAddr is legal, and continue to process the next step, and return an exception and release the IPC message if the BufferAddr is illegal.

By means of the method and the device, validity check is conducted on the determined memory address, the situations that the transmitted message is invalid or the receiving end is affected due to the fact that the illegal memory address is invalid can be avoided, and effectiveness of message transmission can be improved.

In one exemplary embodiment, the validity check is performed on the target memory address to obtain a validity check result, including: under the condition that the target memory address is in a preset address range, determining that the target memory address is legal; and under the condition that the target memory address is out of the preset address range, determining that the target memory address is illegal.

The validity check of the target memory address may be to check whether the size of the target memory address is within an expected range. In this embodiment, an address range may be preset, that is, a preset address range is used to determine whether the determined memory address is legal.

And under the condition that the target memory address is in the preset address range, determining that the target memory address is legal. And under the condition that the target memory address is out of the preset address range, the target memory address can be determined to be illegal.

According to the embodiment, the validity checking efficiency can be improved by presetting the address range of the memory address and checking whether the memory address is in the address range to determine whether the determined memory address is valid, so that the message transmission efficiency is improved.

The following explains the transmission method of the message in the embodiment of the present application with reference to an alternative example. In this alternative example, the target transfer message is an IPC message, the target memory address is a buffer address (i.e., buffer address), the target transfer message is an IPC message, the base address is BaseAddr, and the address unit size is UnitSize.

Since IPC messages sometimes need to be forwarded in multiple layers during transmission between different FUs, too long a message length can occupy a large bandwidth and increase command transmission time. In this optional example, a method for improving the transmission efficiency of an IPC message is provided, an absolute 64bit address is not filled in the message, and the transmission of the message is performed in the form of bufferId and bufferLength. During transmission, the sending end calculates a buffer address and a buffer address according to the defined BaseAddr and the UnitSize and the buffer address to be transferred, and fills the buffer Id and the buffer address into the message body, and the receiving end calculates the buffer address according to the defined BaseAddr and the UnitSize and the received buffer Id and the received buffer address, namely, the transmission of the address is completed. Through the simple calculation, the occupied space of the BufferAddr in the message can be greatly compressed, the original 2 Dwords can only transmit one 64-bit absolute address, and 4 or more absolute addresses can be transmitted after optimization. The message length is reduced by adding simple calculation, the data interaction between processes is optimized, the message transmission efficiency is improved, unnecessary transmission bandwidth waste is reduced, the bus bandwidth is utilized more effectively, and the product performance is improved.

The flow of the message transmission method in this alternative example may include the following steps:

step 1, define BaseAddr, unitSize when initializing the memory.

Step 2, after the sender obtains the BufferAddr, calculating the relative offset of the BufferAddr relative to the base address, determining the bufferand according to the formula bufferaddr= (BufferAddr-BaseAddr)/UnitSize, and dividing the size of the BufferAddr to be transmitted by UnitSize to obtain the bufferLength.

And 3, filling the obtained bufferId, bufferLength into an IPC message structure body, and dynamically adjusting the number of the occupied bits according to the number of the occupied bits.

And 4, the receiving end receives the IPC message, extracts bufferId, bufferLength, and determines the buffer address according to the parameters defined in the step 1 and the formula buffer=buffer Id.

And 5, after the BufferAddr is obtained, parameter checking can be carried out on the BufferAddr to judge whether the BufferAddr is in a legal range, if the BufferAddr is legal, the BufferAddr is directly used and IPC information is released, and if the BufferAddr is not legal, the BufferAddr returns to be abnormal and the IPC information is released.

By the alternative example, the reconstruction of the bufferAddr can be realized by adding simple calculation when the bufferAddr is processed, the bits occupied by each bufferAddr after the reconstruction are reduced, the IPC message length is further reduced, unnecessary transmission is reduced compared with a direct address transmission mode, the bandwidth utilization rate is effectively improved, and the transmission bus is more efficiently and fully utilized.

It should be noted that, for simplicity of description, the foregoing method embodiments are all expressed as a series of action combinations, but it should be understood by those skilled in the art that the present application is not limited by the order of actions described, as some steps may be performed in other order or simultaneously in accordance with the present application. Further, those skilled in the art will also appreciate that the embodiments described in the specification are all preferred embodiments, and that the acts and modules referred to are not necessarily required in the present application.

From the description of the above embodiments, it will be clear to a person skilled in the art that the method according to the above embodiments may be implemented by means of software plus the necessary general hardware platform, but of course also by means of hardware, but in many cases the former is a preferred embodiment. Based on such understanding, the technical solutions of the embodiments of the present application may be essentially or portions contributing to the prior art may be embodied in the form of a software product stored in a storage medium (such as ROM/RAM, magnetic disk, optical disk) including several instructions for causing a terminal device (which may be a mobile phone, a computer, a server, or a network device, etc.) to perform the methods of the embodiments of the present application.

According to still another aspect of the embodiments of the present application, a message transmission device is further provided, and the device is configured to implement the message transmission method provided in the foregoing embodiments, which is not described in detail. As used below, the term "module" may be a combination of software and/or hardware that implements a predetermined function. While the means described in the following embodiments are preferably implemented in software, implementation in hardware, or a combination of software and hardware, is also possible and contemplated.

Fig. 4 is a block diagram of a message transmission apparatus according to an embodiment of the present application, as shown in fig. 4, including:

a first obtaining unit 402, configured to obtain a target memory address, where the target memory address is a buffer address of a target buffer transmitted by a target transmission message to be transmitted;

a first determining unit 404, configured to determine, according to the base address and the address unit size, an identification value of an address identifier corresponding to the target memory address, to obtain a target identification value;

the first execution unit 406 is configured to write the target identifier value into a message structure of the target transmission message, and transmit the target transmission message to a receiving end of the target transmission message.

According to the embodiment of the application, the target memory address is obtained, wherein the target memory address is a buffer area address of a target buffer area transmitted by a target transmission message to be transmitted; determining an identification value of an address identification corresponding to a target memory address according to the base address and the size of the address unit to obtain a target identification value; the method comprises the steps of writing the target identification value into a message structure body of the target transmission message, and transmitting the target transmission message to a receiving end of the target transmission message, so that the problem of low message transmission efficiency caused by overlong message to be transmitted in a transmission method of the inter-process communication message in the related technology can be solved, and the message transmission efficiency is improved.

Optionally, the apparatus further includes:

and the second acquisition unit is used for acquiring the base address and the address unit size before determining the identification value of the address identification corresponding to the target memory address according to the base address and the address unit size, wherein the base address and the address unit size are set in the process of initializing the memory.

Optionally, the apparatus further includes:

and the second execution unit is used for setting the minimum value of the buffer address as a base address and setting the minimum unit among the storage addresses as the address unit size.

Optionally, the second acquisition unit includes:

and the reading unit is used for reading the base address and the address unit size from the preset register.

Optionally, the first determining unit includes:

the first determining module is used for determining the address offset between the target memory address and the base address to obtain the target offset;

and the second determining module is used for determining a target identification value of the address identification corresponding to the target memory address according to the target offset and the size of the address unit.

Optionally, the second determining module includes:

and the determining submodule is used for determining a quotient obtained by dividing the target offset by the size of the address unit as a target identification value of the address identification corresponding to the target memory address.

Optionally, the apparatus further comprises a second determining unit, the first executing unit comprises a writing module, wherein,

the second determining unit is used for determining a parameter value of a buffer length parameter corresponding to the target memory address according to the buffer size and the address unit size of the target buffer to obtain a target length value;

and the writing module is used for writing the target identification value and the target length value into a message structure body of the target transmission message.

Optionally, the second determining unit includes:

And the third determining module is used for determining a quotient obtained by dividing the buffer size of the target buffer by the size of the address unit as a target length value of a buffer length parameter corresponding to the target memory address.

Optionally, the writing module includes:

and the writing sub-module is used for writing the target identification value and the target length value into a message structure body of the target transmission message according to the bit number occupied by the target identification value and the bit number occupied by the target length value.

Optionally, the apparatus further includes:

and the adjusting unit is used for dynamically adjusting the bit number occupied by the target identification value and the bit number occupied by the target length value according to the bit number occupied by the target memory address.

Optionally, the adjusting unit includes:

and the fourth determining module is used for determining the product of the number of bits occupied by the target memory address and the preset proportion as the number of bits occupied by the target identification value, and determining the difference value between the number of bits occupied by the target memory address and the number of bits occupied by the target identification value as the number of bits occupied by the target length value.

Optionally, the first determining unit includes:

and a fifth determining module, configured to determine, according to the base address and the address unit size, an identification value of an address identifier corresponding to each of the plurality of memory addresses, where the target memory address includes an identification value corresponding to each memory address, where the target memory address includes a plurality of memory addresses.

Optionally, the first acquisition unit includes:

and the acquisition module is used for acquiring the absolute address of the target buffer area to obtain the target memory address.

According to still another aspect of the embodiments of the present application, a message transmission device is further provided, and the device is configured to implement the message transmission method provided in the foregoing embodiments, which is not described in detail. Fig. 5 is a block diagram of another message transmission apparatus according to an embodiment of the present application, as shown in fig. 5, including:

a receiving unit 502, configured to receive a target transmission message sent by a sending end;

an extracting unit 504, configured to extract a target identification value from a message structure body of the target transfer message, where the target identification value is an identification value of an address identifier corresponding to the target memory address;

the third determining unit 506 is configured to determine the target memory address according to the target identification value, the base address, and the address unit size.

According to the embodiment of the application, the target transmission message sent by the sending end is received; extracting a target identification value from a message structure body of the target transmission message, wherein the target identification value is an identification value of an address identification corresponding to a target memory address; according to the target identification value, the base address and the address unit size, the target memory address is determined, so that the problem of low message transmission efficiency caused by overlong messages to be transmitted in a transmission method of inter-process communication messages in the related technology can be solved, and the message transmission efficiency is improved.

Optionally, the extraction unit includes:

a sixth determining module, configured to determine a number of bits occupied by the target identifier value and a number of bits occupied by the target length value, where the target length value is a parameter value of a buffer length parameter corresponding to the target memory address, and the target length value is used to identify a buffer size of a target buffer corresponding to the target memory address;

and the extraction module is used for extracting the target identification value and the target length value from the message structure body of the target transmission message according to the bit number occupied by the target identification value and the bit number occupied by the target length value.

Optionally, the third determining unit includes:

and a seventh determining module, configured to determine the sum of the product of the target identification value and the address unit size and the base address as the target memory address.

Optionally, the apparatus further includes:

the checking unit is used for checking the validity of the target memory address after determining the target memory address according to the target identification value, the base address and the address unit size to obtain a validity checking result;

the third execution unit is used for storing the target memory address and releasing the target transmission message under the condition that the validity check result indicates that the target memory address is legal;

And the fourth execution unit is used for sending message abnormality indication information to the sending end and releasing the target transmission message under the condition that the validity check result indicates that the target memory address is illegal, wherein the message abnormality indication information is used for indicating that the memory address transmitted in the target transmission message is abnormal.

Optionally, the inspection unit includes:

an eighth determining module, configured to determine that the target memory address is legal if the target memory address is located in a preset address range;

and the ninth determining module is used for determining that the target memory address is illegal when the target memory address is out of the preset address range.

It should be noted that each of the above modules may be implemented by software or hardware, and for the latter, it may be implemented by, but not limited to: the modules are all located in the same processor; alternatively, the above modules may be located in different processors in any combination.

According to a further aspect of the embodiments of the present application, there is also provided a computer readable storage medium having stored therein a computer program, wherein the computer program is arranged to perform the steps of any of the method embodiments described above when run.

In one exemplary embodiment, the computer readable storage medium may include, but is not limited to: a usb disk, a Read-Only Memory (ROM), a random access Memory (Random Access Memory, RAM), a removable hard disk, a magnetic disk, or an optical disk, or other various media capable of storing a computer program.

According to a further aspect of embodiments of the present application, there is also provided an electronic device comprising a memory, in which a computer program is stored, and a processor arranged to run the computer program to perform the steps of any of the method embodiments described above.

In an exemplary embodiment, the electronic device may further include a transmission device connected to the processor, and an input/output device connected to the processor.

Specific examples in this embodiment may refer to the examples described in the foregoing embodiments and the exemplary implementation, and this embodiment is not described herein.

It will be appreciated by those skilled in the art that the modules or steps of the embodiments of the application described above may be implemented in a general purpose computing device, they may be concentrated on a single computing device, or distributed across a network of computing devices, they may be implemented in program code executable by computing devices, so that they may be stored in a storage device for execution by computing devices, and in some cases, the steps shown or described may be performed in a different order than what is shown or described, or they may be separately fabricated into individual integrated circuit modules, or multiple modules or steps of them may be fabricated into a single integrated circuit module. Thus, embodiments of the present application are not limited to any specific combination of hardware and software.

The foregoing description is only a preferred embodiment of the present application and is not intended to limit the embodiment of the present application, but various modifications and changes may be made to the embodiment of the present application by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the principles of the embodiments of the present application should be included in the protection scope of the embodiments of the present application.

Claims

1. A method for transmitting a message, comprising:

acquiring a target memory address, wherein the target memory address is a buffer area address of a target buffer area transmitted by a target transmission message to be transmitted;

determining an identification value of an address identification corresponding to the target memory address according to the base address and the size of an address unit, and obtaining a target identification value, wherein the size of the address unit is the length of the minimum unit between storage addresses;

writing the target identification value into a message structure body of the target transmission message, and transmitting the target transmission message to a receiving end of the target transmission message;

the determining the identification value of the address identification corresponding to the target memory address according to the base address and the address unit size to obtain the target identification value comprises the following steps: determining an address offset between the target memory address and the base address to obtain a target offset; determining the target identification value of the address identification corresponding to the target memory address according to the target offset and the address unit size;

Wherein the determining, according to the target offset and the address unit size, the target identification value of the address identification corresponding to the target memory address includes: and dividing the target offset by the address unit size to obtain a quotient, and determining the quotient as the target identification value of the address identification corresponding to the target memory address.

2. The method of claim 1, wherein prior to said determining an identification value for an address identification corresponding to said target memory address based on a base address and an address unit size, said method further comprises:

and acquiring the base address and the address unit size, wherein the base address and the address unit size are set in the process of initializing the memory.

3. The method according to claim 2, wherein the method further comprises:

setting a minimum value of the buffer addresses as the base address, and setting a length of a minimum unit between the storage addresses as the address unit size.

4. The method of claim 2, wherein the obtaining the base address and the address unit size comprises:

And reading the base address and the address unit size from a preset register.

5. The method of claim 1, wherein the step of determining the position of the substrate comprises,

the method further comprises the steps of: determining a parameter value of a buffer length parameter corresponding to the target memory address according to the buffer size of the target buffer and the address unit size to obtain a target length value;

the writing the target identification value to the message structure of the target transmission message comprises the following steps: writing the target identification value and the target length value to a message structure of the target transmission message.

6. The method of claim 5, wherein determining the parameter value of the buffer length parameter corresponding to the target memory address according to the buffer size of the target buffer and the address unit size, to obtain the target length value, comprises:

and determining the quotient obtained by dividing the buffer size of the target buffer by the address unit size as the target length value of the buffer length parameter corresponding to the target memory address.

7. The method of claim 6, wherein the writing the target identification value and the target length value to the message structure of the target transfer message comprises:

And writing the target identification value and the target length value into a message structure body of the target transmission message according to the bit number occupied by the target identification value and the bit number occupied by the target length value.

8. The method of claim 7, wherein the method further comprises:

and dynamically adjusting the bit number occupied by the target identification value and the bit number occupied by the target length value according to the bit number occupied by the target memory address.

9. The method of claim 8, wherein dynamically adjusting the number of bits occupied by the target identification value and the number of bits occupied by the target length value according to the number of bits occupied by the target memory address comprises:

and determining the product of the bit number occupied by the target memory address and the preset proportion as the bit number occupied by the target identification value, and determining the difference value of the bit number occupied by the target memory address and the bit number occupied by the target identification value as the bit number occupied by the target length value.

10. The method according to claim 1, wherein determining the identification value of the address identifier corresponding to the target memory address according to the base address and the address unit size, to obtain the target identification value, includes:

And under the condition that the target memory address comprises a plurality of memory addresses, respectively determining an identification value of an address identification corresponding to each memory address in the plurality of memory addresses according to the base address and the address unit size to obtain an identification value corresponding to each memory address, wherein the target identification value comprises the identification value corresponding to each memory address.

11. The method according to any one of claims 1 to 10, wherein the fetching a target memory address comprises:

and acquiring the absolute address of the target buffer area to obtain the target memory address.

12. A method for transmitting a message, comprising:

receiving a target transmission message sent by a sending end;

extracting a target identification value from a message structure body of the target transmission message, wherein the target identification value is an identification value of an address identification corresponding to a target memory address;

determining the target memory address according to the target identification value, the base address and the address unit size, wherein the address unit size is the length of the minimum unit between storage addresses;

wherein the extracting the target identification value from the message structure body of the target transmission message includes: determining the bit number occupied by the target identification value and the bit number occupied by a target length value, wherein the target length value is a parameter value of a buffer zone length parameter corresponding to the target memory address, and the target length value is used for identifying the buffer zone size of a target buffer zone corresponding to the target memory address; extracting the target identification value and the target length value from a message structure body of the target transmission message according to the bit number occupied by the target identification value and the bit number occupied by the target length value;

Wherein, the determining the target memory address according to the target identification value, the base address and the address unit size includes: and determining the product of the target identification value and the size of the address unit and the sum of the target identification value and the base address as the target memory address.

13. The method of claim 12, wherein after the determining the target memory address based on the target identification value, the base address, and the address unit size, the method further comprises:

performing validity check on the target memory address to obtain a validity check result;

storing the target memory address and releasing the target transmission message under the condition that the validity check result indicates that the target memory address is legal;

and under the condition that the validity check result indicates that the target memory address is illegal, sending message abnormality indication information to the sending end and releasing the target transmission message, wherein the message abnormality indication information is used for indicating that the memory address transmitted in the target transmission message is abnormal.

14. The method of claim 13, wherein the performing the validity check on the target memory address to obtain a validity check result includes:

Determining that the target memory address is legal under the condition that the target memory address is in a preset address range;

and under the condition that the target memory address is out of a preset address range, determining that the target memory address is illegal.

15. A message transmission apparatus, comprising:

the first acquisition unit is used for acquiring a target memory address, wherein the target memory address is a buffer area address of a target buffer area transmitted by a target transmission message to be transmitted;

the first determining unit is used for determining an identification value of an address identification corresponding to the target memory address according to the base address and the size of an address unit to obtain a target identification value, wherein the size of the address unit is the length of the minimum unit between the storage addresses;

the first execution unit is used for writing the target identification value into a message structure body of the target transmission message and transmitting the target transmission message to a receiving end of the target transmission message;

wherein the first determining unit includes: the first determining module is used for determining the address offset between the target memory address and the base address to obtain a target offset; a second determining module, configured to determine, according to the target offset and the address unit size, the target identifier value of an address identifier corresponding to the target memory address,

Wherein the second determining module includes: and the determining submodule is used for determining the quotient obtained by dividing the target offset by the size of the address unit as the target identification value of the address identification corresponding to the target memory address.

16. A message transmission apparatus, comprising:

the receiving unit is used for receiving the target transmission message sent by the sending end;

an extracting unit, configured to extract a target identification value from a message structure body of the target transmission message, where the target identification value is an identification value of an address identifier corresponding to a target memory address;

the third determining unit is used for determining the target memory address according to the target identification value, the base address and the address unit size, wherein the address unit size is the length of the minimum unit between the storage addresses;

wherein the extraction unit includes: a sixth determining module, configured to determine a number of bits occupied by the target identifier value and a number of bits occupied by a target length value, where the target length value is a parameter value of a buffer length parameter corresponding to the target memory address, and the target length value is used to identify a buffer size of a target buffer corresponding to the target memory address; an extracting module, configured to extract the target identification value and the target length value from a message structure body of the target transmission message according to the number of bits occupied by the target identification value and the number of bits occupied by the target length value;

Wherein the third determination unit includes: and a seventh determining module, configured to determine, as the target memory address, a sum of the product of the target identification value and the address unit size and the base address.

17. A computer readable storage medium, characterized in that a computer program is stored in the computer readable storage medium, wherein the computer program, when being executed by a processor, implements the steps of the method according to any of the claims 1 to 14.

18. An electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, characterized in that the processor implements the steps of the method of any one of claims 1 to 14 when the computer program is executed.