CN115878351A

CN115878351A - Message transmission method and device, storage medium and electronic device

Info

Publication number: CN115878351A
Application number: CN202310199164.0A
Authority: CN
Inventors: 张海仑; 赵龙; 钟戟
Original assignee: Suzhou Inspur Intelligent Technology Co Ltd
Current assignee: Suzhou Inspur Intelligent Technology Co Ltd
Priority date: 2023-03-03
Filing date: 2023-03-03
Publication date: 2023-03-31
Anticipated expiration: 2043-03-03
Also published as: CN115878351B

Abstract

The embodiment of the application provides a message transmission method and device, a storage medium and an electronic device, wherein the message transmission method comprises the following steps: acquiring a target memory address, wherein the target memory address is a buffer area address of a target buffer area transmitted by a target transmission message to be transmitted; determining an identification value of an address identification corresponding to the target memory address according to the base address and the size of the address unit to obtain a target identification value; and writing the target identification value into a message structure body of the target transmission message, and transmitting the target transmission message to a receiving end of the target transmission message. By the method and the device, the problem of low message transmission efficiency caused by the fact that the message needing to be transmitted is too long in the transmission method of the interprocess communication message in the related technology is solved.

Description

Message transmission method and device, storage medium and electronic device

Technical Field

The embodiment of the application relates to the field of computers, in particular to a message transmission method and device, a storage medium and an electronic device.

Background

Currently, for Communication between different FU (Function units), an Inter-Process Communication mode is generally adopted, and an IPC (Inter-Process Communication) message is used as a basic Unit. Each IPC message contains several parameters, where the number of bits occupied by the memory address is large.

However, with the development of NAND (Not AND, that is, a computer flash memory device) technology, the number of memory addresses that a multiplane (that is, a memory matrix) read-write message needs to transfer is increasing, AND the length of the IPC message is also correspondingly increased, so that the resource consumed in reading AND writing the IPC message is increased, thereby affecting the transmission efficiency of the message.

Therefore, the method for transmitting the interprocess communication message in the related art has the problem of low message transmission efficiency caused by the overlong message needing to be transmitted.

Disclosure of Invention

The embodiment of the application provides a message transmission method and device, a storage medium and an electronic device, so as to at least solve the problem that the message transmission efficiency is low due to the fact that a message needing to be transmitted is too long in the inter-process communication message transmission method in the related art.

According to an embodiment of the present application, there is provided a message transmission method, including: acquiring a target memory address, wherein the target memory address is a buffer area address of a target buffer area transmitted by a target transmission message to be transmitted; determining an identification value of an address identification corresponding to the target memory address according to the base address and the size of the address unit to obtain a target identification value; and writing the target identification value into a message structure body of the target transmission message, and transmitting the target transmission message to a receiving end of the target transmission message.

According to another aspect of the embodiments of the present application, there is also provided a method for transmitting a message, including: receiving a target transmission message sent by a sending end; extracting a target identification value from a message structure body of the target transmission message, wherein the target identification value is an identification value of an address identification corresponding to a target memory address; and determining the target memory address according to the target identification value, the base address and the size of the address unit.

According to another embodiment of the present application, there is provided a message transmission apparatus including: the device comprises a first obtaining unit, a second obtaining unit and a processing unit, wherein the first obtaining unit is used for obtaining a target memory address, and the target memory address is a buffer area address of a target buffer area transmitted by a target transmission message to be transmitted; the first determining unit is used for determining an identification value of an address identification corresponding to the target memory address according to the base address and the size of the address unit to obtain a target identification value; and the first execution unit is used for writing the target identification value into a message structure body of the target transmission message and transmitting the target transmission message to a receiving end of the target transmission message.

According to another embodiment of the present application, there is also provided a message transmission apparatus, including: the receiving unit is used for receiving a target transmission message sent by the sending end; the extracting unit is used for extracting a target identification value from a message structure body of the target transmission message, wherein the target identification value is an identification value of an address identification corresponding to a target memory address; and the third determining unit is used for determining the target memory address according to the target identification value, the base address and the size of the address unit.

According to a further embodiment of the present application, there is also provided a computer-readable storage medium having a computer program stored thereon, wherein the computer program is arranged to, when executed, perform the steps of any of the method embodiments described above.

According to yet another embodiment of the present application, there is also provided an electronic device, comprising a memory having a computer program stored therein and a processor configured to run the computer program to perform the steps of any of the method embodiments described above.

According to the method and the device, the storage format of the memory address stored in the message is reconstructed, and the target memory address is obtained, wherein the target memory address is the buffer area address of the target buffer area transmitted by the target transmission message to be transmitted; determining an identification value of an address identification corresponding to a target memory address according to the base address and the size of the address unit to obtain a target identification value; the target identification value is written into a message structure of the target transmission message, and the target transmission message is transmitted to a receiving end of the target transmission message, because the message is not stored with an original memory address, but with the identification value corresponding to the memory address determined according to the predefined base address and address unit size (which can be used for restoring the original memory address according to the base address and the address unit size), the occupied space of the memory address in the message can be effectively compressed, the purpose of shortening the length of the message to be transmitted can be realized, the technical effect of improving the message transmission efficiency is achieved, and the problem of low message transmission efficiency caused by the overlong message to be transmitted in the transmission method of the interprocess communication message in the related technology is solved.

Drawings

Fig. 1 is a hardware environment diagram of a message transmission method according to an embodiment of the present application;

fig. 2 is a flow chart of a message transmission method according to an embodiment of the present application;

fig. 3 is a flow chart of another message transmission method according to an embodiment of the present application;

fig. 4 is a block diagram of a message transmission apparatus according to an embodiment of the present application;

fig. 5 is a block diagram of another message transmission apparatus according to an embodiment of the present application.

Detailed Description

Embodiments of the present application will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.

It should be noted that the terms "first," "second," and the like in the description and claims of the embodiments of the present application and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order.

The method embodiments provided in the embodiments of the present application may be executed in a mobile terminal, a computer terminal, or a similar computing device. Taking an example of the method running on a computer terminal, fig. 1 is a schematic diagram of a hardware environment of a message transmission method according to an embodiment of the present application. As shown in fig. 1, the computer terminal may include one or more processors 102 (only one is shown in fig. 1) (the processor 102 may include, but is not limited to, a processing device such as a microprocessor MCU or a programmable logic device FPGA, etc.) and a memory 104 for storing data, wherein the computer terminal may further include a transmission device 106 for communication functions and an input-output device 108. It will be understood by those skilled in the art that the structure shown in fig. 1 is only an illustration and is not intended to limit the structure of the computer terminal. For example, the computer terminal may also include more or fewer components than shown in FIG. 1, or have a different configuration than shown in FIG. 1.

The memory 104 may be used to store computer programs, for example, software programs and modules of application software, such as a computer program corresponding to the message transmission method in the embodiment of the present application, and the processor 102 executes various functional applications and data processing by running the computer programs stored in the memory 104, so as to implement the above method. The memory 104 may include high speed random access memory, and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some examples, the memory 104 may further include memory located remotely from the processor 102, which may be connected to the mobile terminal over a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.

The transmission device 106 is used to receive or transmit data via a network. Specific examples of the network described above may include a wireless network provided by a communication provider of the computer terminal. In one example, the transmission device 106 includes a Network adapter (NIC) that can be connected to other Network devices through a base station to communicate with the internet. In one example, the transmission device 106 may be a Radio Frequency (RF) module, which is used to communicate with the internet in a wireless manner.

According to an aspect of the embodiments of the present application, there is provided a method for transmitting a message, for example, a computer terminal executes the method for transmitting a message in the embodiments of the present application, and fig. 2 is a flowchart of a method for transmitting a message according to the embodiments of the present application, as shown in fig. 2, the flowchart includes the following steps:

step S202, a target memory address is obtained, where the target memory address is a buffer address of a target buffer transmitted by a target transmission message to be transmitted.

The message transmission method in this embodiment can be applied to a scenario in which communication is performed between different functional units FU in the same device. For Firmware FW (Firmware), communication between different FUs mainly adopts an inter-process communication mode, and different pipeline FIFOs (First Input First Output) are defined by FUs. The IPC message is a basic unit of interprocess communication, and the length of the IPC message is generally in units of Dword (Double Word, each Word is 2 bytes long, 32 bits). Each IPC message may include a plurality of Dwords (e.g., 16 Dwords), which include parameters such as a message source, a message destination, a message unique identifier, a message type, a message address, and a plurality of buffer (memory addresses for storing data when reading and writing data) addresses to be transferred.

In this embodiment, before message transmission between different functional units, the target memory address may be obtained first. Here, the target memory address may be a buffer address of a target buffer transmitted by the target transmission message to be transmitted, that is, the aforementioned buffer address. The targeted transfer message may be the aforementioned IPC message.

Step S204, according to the base address and the size of the address unit, determining the identification value of the address identification corresponding to the target memory address, and obtaining the target identification value.

In the IPC message, other parameters except the buffer address are simpler, and the number of occupied bits (bits) is less. An absolute buffer address in a 64-bit operating system contains 64 bits (i.e., occupies 2 dwords). A typical structure is as follows, where the buffer address occupies 9 Dwords:

typedef union

{

struct

{

u32 msgType : 8;

u32 flashChanQ : 4;

u32 chan : 5;

u32 outMsgQ : 4;

u32 reservedDW0B31_21 : 11;

u32 tag : 16;

u32 pageType : 3;

u32 read_type : 4;

u32 page_load_flag : 1;

u32 fast_read_flag : 1;

u32 inject_err_type : 3;

u32 reservedDW1B31_28 : 4;

u32 data_frame_offset : 11;

u32 data_frame_length : 11;

u32 buf_alloc_flag : 1;

u32 plane_bitmap : 4;

u32 df_bitmap : 16;

u32 reservedDW4B31_20 : 12;

u32 read_refs;

u32 eccCodeRateIndex : 4;

u32 reservedDW7B7_5 : 4;

u32 maxIter : 8;

u32 lLR0 : 8;

u32 lLR1 : 8;

u32 buffer_addr[9];

};

u32 dw[16];

} flash_read_t 。

the most basic operations of the communication between different FUs and NCM (Nand Control Manager) processes include reading, writing, erasing and the like, wherein the speed of reading and writing is important, and the basic performance of the product is determined. However, with the development of NAND technology, one multi-plane read-write message needs to deliver more buffer addresses, and at this time, the IPC message length has to be increased greatly. When the processes communicate with each other, the IPC message needs to be written in one module and read out from another module, and after the length of the message is increased, more CPU (Central Processing Unit) resources are consumed when the IPC message is read and written. In addition, the IPC message needs to be forwarded in multiple layers in the transmission process between different FUs, and too long IPC message also causes a great burden to the bus in the message transmission process, thereby affecting the transmission performance and the transmission efficiency.

In order to solve at least some of the above problems, in this embodiment, the format of the memory address recorded in the target transmission message may be reconstructed, and the compression and optimization of the Dword number occupied by the memory address in the message structure are implemented by recording the identifier value corresponding to the memory address instead of directly recording the complete memory address.

In this embodiment, the identification value of the address identifier corresponding to the target memory address may be determined according to the base address and the size of the address unit, so as to obtain the target identification value. Here, the base address may be a start address of the memory address. The target identification value may be used to identify a target memory address.

Alternatively, the target identification value may be based on a size of the target memory address relative to the base address and the address location size. The base address and the address unit size may be fixed values set in advance, that is, the base address and the address unit size corresponding to each memory address may be the same.

Alternatively, the setting of the base address and the address unit may be performed once before each message transmission, or may be completed in a preparation stage such as memory initialization, and accordingly, the setting of the base address and the address unit may only need to be performed once no matter how many message transmissions are performed.

Step S206, writing the target identification value into the message structure of the target transmission message, and transmitting the target transmission message to the receiving end of the target transmission message.

The target transmission message to be transmitted may include a message structure, where the message structure is a structure used to write information carried in the message, and after the target identification value is obtained, the target identification value may be written into the message structure of the target transmission message, and the target transmission message may be transmitted to a receiving end of the target transmission message. The mode of transmitting the target transmission message may include transmitting a message structure of the target transmission message, and may also include transmitting other information of the target transmission message except the message structure. By writing the identification value corresponding to the memory address into the message structure of the transmission message, compared with a mode of transmitting a direct address, the purpose of reducing the bit number occupied by the memory address in the transmission message can be realized, so that the length (namely, the occupied bit number) of the transmission message can be reduced, and the bandwidth utilization rate is improved.

Here, the message structure of the target transfer message may include a plurality of parameters, and the order and position of the plurality of parameters may be preset. Each parameter of the plurality of parameters may correspond to one field in the message structure, each parameter corresponds to one or more bits, that is, occupies one or more bits, and the number of bits occupied by each parameter may be fixed or may be set correspondingly for different transmission messages. The target memory address may belong to one of a plurality of parameters, and the target identification value may be written in a write location in the message structure corresponding to the target memory address.

Through the steps, a target memory address is obtained, wherein the target memory address is a buffer area address of a target buffer area transmitted by a target transmission message to be transmitted; determining an identification value of an address identification corresponding to a target memory address according to the base address and the size of the address unit to obtain a target identification value; the target identification value is written into the message structure of the target transmission message, and the target transmission message is transmitted to the receiving end of the target transmission message, so that the problem of low message transmission efficiency caused by overlong messages needing to be transmitted in the transmission method of the interprocess communication message in the related technology can be solved, and the technical effect of improving the message transmission performance is achieved.

In an exemplary embodiment, before determining an identification value of an address identifier corresponding to the target memory address according to the base address and the address unit size, the method further includes: and acquiring a base address and an address unit size, wherein the base address and the address unit size are set in the process of initializing the memory.

The base address and address unit size may be obtained prior to determining the target identification value. Here, the base address and the address unit size may be set during the initialization of the memory. The memory initialization refers to initialization of a memory that manages data of a plurality of processes.

Through the embodiment, the setting of the base address and the address unit is completed in the process of memory initialization, so that the condition that independent resources are wasted for setting the base address and the address unit can be avoided, and the utilization rate of the resources is improved.

In one exemplary embodiment, the above method further comprises: the minimum value of the buffer addresses is set as the base address, and the minimum unit between the memory addresses is set as the address unit size.

In setting the base address and the address unit size, the minimum value of the buffer address may be set as the base address, and the minimum unit between the memory addresses may be set as the address unit size. For example, during memory initialization, baseAddr (base address) and UnitSize (address unit size) are defined, where the BaseAddr uses the minimum value of the used buffer address, and the UnitSize is the minimum unit between storage addresses.

Optionally, the address unit size is the length of the address unit (or the number of bits occupied by the address unit), and setting the minimum unit between the storage addresses as the address unit size means: and setting the size of the minimum unit between the storage addresses as the size of an address unit, wherein the address unit is the minimum unit between the storage addresses.

By the embodiment, the minimum value of the buffer address is set as the base address, and the minimum unit between the storage addresses is set as the size of the address unit, so that the applicability of the base address and the size of the address unit to all memory addresses can be improved.

In one exemplary embodiment, obtaining the base address and the address unit size comprises: the base address and address location size are read from a preset register.

In this embodiment, for the base address and the address unit size, under the condition supported by hardware, the base address and the address unit size may be stored in a preset register after the definition is completed, for example, when the memory is initialized, the base address and the address unit size are set, and the set base address and the set address unit size are stored in the preset register. Correspondingly, when the message is transmitted, the base address and the address unit size can be read from the preset register. Here, the preset register may be a register which is set in advance and may include a flip-flop having a memory function.

The preset register may be allowed to be set, modified, or the like only at the time of memory initialization, or may not be allowed to be set, modified, or the like during the transmission of a message. In this case, after the base address and the address unit size are stored in the preset register, when a different sender wants to perform a transfer message transmission, the base address and the address unit size can be read from the preset register. Optionally, to avoid the information acquisition conflict, the preset register only allows one process to read data at the same time, and at the same time, does not allow other processes to read data from the preset register when reading data. Alternatively, the preset register may also allow multiple processes to read data at the same time, and at this time, data reading conflicts may be avoided in one or more ways, for example, the information in the preset register only allows reading, does not allow modification, and the like. This is not limited in this embodiment.

It should be noted that, when different processes transmit transmission messages, the base address and the address unit size can be read from the preset register, and the base address and the address unit size read by different processes may be the same.

Through the embodiment, the base address and the size of the address unit can be conveniently acquired by reading the base address and the size of the address unit from the register, so that the convenience of information acquisition is improved.

In an exemplary embodiment, determining an identifier value of an address identifier corresponding to a target memory address according to a base address and an address unit size, and obtaining the target identifier value includes: determining the address offset between the target memory address and the base address to obtain the target offset; and determining a target identification value of the address identification corresponding to the target memory address according to the target offset and the size of the address unit.

Because the actual address of the memory address can be determined by the base address and the offset address, when determining the target identification value, the unique function (positioning arrangement) of the base address is considered, the address offset between the target memory address and the base address can be determined firstly to obtain the target offset, and then the target identification value of the address identification corresponding to the target memory address is determined according to the target offset and the size of the address unit. The target offset may be a difference between the size of the target memory address and the base address, i.e., the offset address.

By the embodiment, the identification value corresponding to the memory address is determined according to the relationship between the offset of the memory address and the base address and the size of the address unit, so that the relevance between the identification value and the memory address can be improved, and the acquisition of the memory address of the receiving end for transmitting the message is facilitated.

In an exemplary embodiment, determining a target tag value of an address tag corresponding to a target memory address according to a target offset and an address unit size includes: and determining the target identification value of the address identification corresponding to the target memory address by dividing the target offset by the size of the address unit.

In the present embodiment, since the address unit size may be the smallest unit between the storage addresses, it may be considered that each address stored occupies an integer number of address units, i.e., the size of each address is an integer multiple of the address unit size. The target offset may be divided by the address unit size to determine a target identification value of the address identification corresponding to the target memory address.

For example, after the sender acquires the BufferAddr, the relative offset of the BufferAddr with respect to the base address is calculated, and the offset value bufferId = (BufferAddr-BaseAddr)/UnitSize, where the bufferId obtained after the calculation generally does not exceed 12bits.

By the embodiment, the identification value corresponding to the memory address is determined according to the quotient of the offset of the memory address and the base address and the size of the address unit, so that convenience in determining the identification value can be improved.

In one exemplary embodiment, the above method further comprises: and determining the parameter value of the buffer length parameter corresponding to the target memory address according to the size of the buffer area and the size of the address unit of the target buffer area to obtain a target length value. Correspondingly, writing the target identification value into a message structure of the target transmission message includes: and writing the target identification value and the target length value into a message structure body of the target transmission message.

In order to facilitate a receiving end of the target transmission message to accurately determine complete information of the buffer corresponding to the target memory address, a length value corresponding to the target memory address can be written into a message structure of the target transmission message. In this embodiment, a parameter value of a buffer length parameter corresponding to a target memory address may be determined according to the size of a buffer of a target buffer and the size of an address unit, so as to obtain a target length value.

While the target identification value is written to the message structure of the target transfer message, the target length value may also be written to the message structure of the target transfer message. For example, the sending end may fill the obtained bufferld and bufferLength into the IPC message structure.

Optionally, the target identifier value and the target length value may be adjacent to each other in the message structure of the target transmission message as a memory address parameter. The target length may be a length of the target, and the target identifier value is a length of the target. Here, the address identifier may be used to identify a memory address (absolute address) of the buffer, and the buffer length parameter (or referred to as a buffer length identifier) may be used to identify a buffer size of the buffer, and the corresponding buffer may be determined by the two parameters.

Through the embodiment, the length value corresponding to the memory address and the identification value corresponding to the memory address are written into the message structure body together, so that the boundary of the buffer area positioning can be improved, and the accuracy of information transmission is improved.

In an exemplary embodiment, determining a parameter value of a buffer length parameter corresponding to a target memory address according to a buffer size and an address unit size of a target buffer to obtain a target length value includes: and determining the quotient obtained by dividing the size of the buffer area of the target buffer area by the size of the address unit as the target length value of the buffer area length parameter corresponding to the target memory address.

In this embodiment, when determining the length value corresponding to the target memory address, a quotient obtained by dividing the size of the buffer area of the target buffer area by the size of the address unit may be determined as the target length value of the buffer area length parameter corresponding to the target memory address. Here, the length value corresponding to the memory address refers to a length value of a buffer length parameter corresponding to the memory address, that is, the length value may be used to identify a size of a buffer corresponding to the memory address.

For example, the buffer length (a parameter that can be used to identify the size of the buffer) can be obtained by dividing the size of the buffer to be transmitted by the UnitSize, and the occupied bits is generally small.

Through the embodiment, the quotient of the size of the buffer area and the size of the address unit of the buffer area is determined as the length value written in the message structure body, so that the receiving end can conveniently determine complete buffer area information according to the size of the preset address unit, and the accuracy of message transmission is improved.

In one exemplary embodiment, writing a target identification value and a target length value to a message structure of a target transfer message includes: and writing the target identification value and the target length value into a message structure body of the target transmission message according to the bit number occupied by the target identification value and the bit number occupied by the target length value.

For the determined target identification value and the target length value, the bit numbers of the target identification value and the target length value in the message structure body of the target transmission message can be respectively determined, and the target identification value and the target length value are written into the message structure body of the target transmission message according to the bit number occupied by the target identification value and the bit number occupied by the target length value.

According to the embodiment, the writing in the message structure body is completed according to the bit number occupied by the identification value and the length value, so that the bit number occupied by the memory address in the message structure body can be effectively reduced, and the purpose of reducing the message length is achieved.

In one exemplary embodiment, the above method further comprises: and dynamically adjusting the bit number occupied by the target identification value and the bit number occupied by the target length value according to the bit number occupied by the target memory address.

The bit number occupied by the target identification value and the target length value in the message structure body of the target transmission message can be dynamically adjusted according to the actual scene. In this embodiment, the number of bits occupied by the target identifier value and the number of bits occupied by the target length value may be dynamically adjusted according to the number of bits occupied by the target memory address.

Optionally, the number of bits occupied by the target identifier and the number of bits occupied by the target length may be predetermined by the transmitting end and the receiving end according to the current transmission environment and in combination with the size of parameters such as the corresponding memory address.

For example, to conveniently obtain the information carried in the transmission message, one Dword may store two sets of bufferld and bufferLength, and at this time, more addresses may be stored under the same message length.

Through the embodiment, more memory addresses can be transmitted under the condition of not increasing the message length by dynamically adjusting the bit number occupied by the identification value and the bit number occupied by the length value, so that the utilization rate of a message structure body is improved.

In an exemplary embodiment, dynamically adjusting the number of bits occupied by the target identifier value and the number of bits occupied by the target length value according to the number of bits occupied by the target memory address includes: and determining the bit number occupied by the target length value as the difference value of the bit number occupied by the target memory address and the bit number occupied by the target identification value.

For the dynamic adjustment of the bit number occupied by the identification value and the length value, a ratio, that is, a preset ratio, may be preset, and the bit number occupied by the identification value and the bit number occupied by the length value may be determined according to the preset ratio. In this embodiment, the product of the bit number occupied by the target memory address and the preset ratio may be determined as the bit number occupied by the target identifier value, and the difference between the bit number occupied by the target memory address and the bit number occupied by the target identifier value may be determined as the bit number occupied by the target length value.

For example, when the obtained bufferld and bufferLength are filled in the IPC message structure, the bit numbers occupied by the bufferld and the bufferLength can be dynamically adjusted according to the bit number occupied by the buffer, for example, the bufferld occupies 12bits and the bufferLength occupies 4bits.

Through the embodiment, the dynamic adjustment of the bit number occupied by the identification value and the length value is realized through the preset proportion, the adjustment efficiency can be improved, and the message transmission efficiency is improved.

In an exemplary embodiment, determining an identifier value of an address identifier corresponding to a target memory address according to a base address and an address unit size, and obtaining the target identifier value includes: under the condition that the target memory address comprises a plurality of memory addresses, respectively determining an identification value of an address identification corresponding to each memory address in the plurality of memory addresses according to the base address and the size of the address unit, and obtaining an identification value corresponding to each memory address, wherein the target identification value comprises the identification value corresponding to each memory address.

In this embodiment, when the target memory address includes a plurality of memory addresses, the target identification value may include an identification value corresponding to each memory address, and the identification value of the address identification corresponding to each memory address in the plurality of memory addresses may be determined according to the base address and the size of the address unit, so as to obtain the identification value corresponding to each memory address.

Optionally, an address offset between the memory address and the base address may be determined in the foregoing manner of determining the target identification value, and a quotient obtained by dividing the address offset by the size of the address unit is determined as the identification value of the address identification corresponding to the memory address.

Optionally, while determining the identifier value corresponding to each memory address, the length value corresponding to each memory address may be determined according to the method for determining the target length value, and the length value and the corresponding identifier value are written into the message structure of the target transmission message.

Through the embodiment, under the condition that a plurality of memory addresses exist, the identification value corresponding to each memory address is determined according to the base address and the size of the address unit, so that the recognition rate of the receiving end on the plurality of memory addresses can be improved, and the accuracy of memory address transmission is improved.

In one exemplary embodiment, obtaining the target memory address includes: and acquiring an absolute address of the target buffer area to obtain a target memory address.

In order to avoid address failure of the memory address in the message transmission process due to chain scission and the like, in this embodiment, the memory address transmitted in the target transmission message may be an absolute address, that is, an absolute position of a file. Obtaining the target memory address may refer to obtaining an absolute address of the target buffer.

By the embodiment, the absolute address is obtained to be used as the memory address to be transmitted, so that address failure caused by change of the connection position can be avoided, and the effectiveness of memory address transmission can be improved.

According to another aspect of the embodiments of the present application, there is also provided a transmission method of a message, which may be a transmission message for receiving and processing the transmission message generated and transmitted by the transmission method of a message provided in the foregoing embodiments. Taking the example of the method for transmitting a message in this embodiment executed by a computer terminal as an example, fig. 3 is a flowchart of another method for transmitting a message according to the embodiment of the present application, and as shown in fig. 3, the flowchart includes the following steps:

step S302, receiving the target transmission message sent by the sending end.

In this embodiment, in inter-process communication, for a receiver of a transfer message, for example, a receiver of a target transfer message, it may receive the target transfer message sent by a sender. Here, the received target transfer message may be generated by the transmitting end, and the target identification value may be written in the message structure thereof.

Step S304, a target identification value is extracted from the message structure of the target transmission message, where the target identification value is an identification value of an address identification corresponding to the target memory address.

After the receiving end receives the target transmission message, the target identification value may be extracted from a message structure of the target transmission message. Here, the target identification value may be an identification value of an address identifier corresponding to the target memory address, which may be extracted from a specified field or a specified position of a message structure of the target transfer message, and the length of the target identification value may be fixed or variable, and may be extracted from the specified field or the specified position of the message structure of the target transfer message based on the number of bits occupied, the end identifier, or other information.

Optionally, the address identifier of the corresponding target memory address may be determined according to the extracted target identifier value, so as to determine the memory address that the sending end wants to transmit.

Optionally, if a target identification value and a length value corresponding to the target memory address, that is, a target length value, are written in the message structure at the same time, the corresponding target length value may be extracted while the target identification value is extracted, so as to determine a buffer (that is, a buffer) corresponding to the target memory address according to the target length value and the target length value.

Step S306, determining a target memory address according to the target identification value, the base address and the size of the address unit.

Optionally, the receiving end may obtain the base address and the address unit size in a manner the same as or similar to the manner in which the sending end obtains the base address and the address unit size, and the specific obtaining manner may refer to the description of the foregoing embodiment, which is not described herein again.

After the target identification value is extracted, the target memory address can be determined by combining the target identification value according to the obtained base address and the size of the address unit. The manner in which the target memory address is determined may correspond to the manner in which the target memory address is generated in the foregoing embodiments.

Through the steps, the target transmission message sent by the sending end is received; extracting a target identification value from a message structure body of a target transmission message, wherein the target identification value is an identification value of an address identification corresponding to a target memory address; the target memory address is determined according to the target identification value, the base address and the size of the address unit, so that the problem of low message transmission efficiency caused by overlong messages needing to be transmitted in the inter-process communication message transmission method in the related technology can be solved, and the technical effect of improving the message transmission performance is achieved.

In one exemplary embodiment, extracting the target identification value from the message structure of the target transfer message includes: determining the bit number occupied by a target identification value and the bit number occupied by a target length value, wherein the target length value is a parameter value of a buffer length parameter corresponding to a target memory address, and the target length value is used for identifying the buffer size of a target buffer corresponding to the target memory address; and extracting the target identification value and the target length value from the message structure body of the target transmission message according to the bit number occupied by the target identification value and the bit number occupied by the target length value.

Because each parameter in the target transmission message can be a message structure written in different positions and bit numbers, under the condition that the target identification value and the target length value are written in the message structure of the target transmission message, the mode of extracting the target identification value and the target length value can be that the bit number occupied by the target identification value and the bit number occupied by the target length value are determined firstly, and then the target identification value and the target length value are extracted from the message structure of the target transmission message according to the bit number occupied by the target identification value and the bit number occupied by the target length value. Here, the target length value is a parameter value of a buffer length parameter corresponding to the target memory address, and the target length value is used to identify a buffer size of the target buffer corresponding to the target memory address.

Optionally, the number of bits occupied by the target identifier value and the number of bits occupied by the target length value may be sent to the receiving end by the sending end while sending the target transmission message, and correspondingly, the number of bits occupied by the target identifier value and the number of bits occupied by the target length value may be implemented by sending the preset ratio and the like. In addition, the number of bits occupied by the target identification value and the number of bits occupied by the target length value may also be determined by both the receiving end and the transmitting end before message transmission, that is, the receiving end knows the number of bits occupied by the target identification value and the number of bits occupied by the target length value, and does not need to inform by the transmitting end.

By the embodiment, the identification value and the target length value are extracted according to the bit number occupied by the identification value and the bit number occupied by the length value, so that the accuracy of obtaining the identification value and the length value can be improved.

In one exemplary embodiment, determining the target memory address according to the target identification value, the base address, and the address unit size includes: and determining the sum of the product of the target identification value and the size of the address unit and the base address as the target memory address.

In this embodiment, the target identification value may be a quotient obtained by dividing an address offset between the target memory address and the base address by an address unit size (i.e., bufferAddr-BaseAddr)/UnitSize), and the receiving end may determine the sum of the base address and a product of the target identification value and the address unit size as the target memory address, that is, determine the target memory address according to a calculation formula BufferAddr = bufferald × UnitSize + basedre.

By the embodiment, the memory address is determined according to the product of the identification value and the size of the address unit and the sum of the base address, so that the bit number of the target memory address in the target transmission message can be reduced, and the accuracy of target memory address transmission can be improved.

In an exemplary embodiment, after determining the target memory address according to the target identification value, the base address, and the address unit size, the method further includes: carrying out validity check on the target memory address to obtain a validity check result; under the condition that the validity check result indicates that the target memory address is valid, storing the target memory address and releasing the target transmission message; and under the condition that the legality checking result indicates that the target memory address is illegal, sending message abnormity indication information to the sending end, and releasing the target transmission message, wherein the message abnormity indication information is used for indicating that the memory address transmitted in the target transmission message is abnormal.

In order to improve the security of message transmission and avoid the influence on the receiving end due to the conditions that the transmitted memory address is illegal, in this embodiment, after the target memory address is determined, the target memory address may be subjected to validity check, and a validity check result is obtained.

And under the condition that the validity check result indicates that the target memory address is valid, the target memory address can be stored, and the target transmission message is released. And under the condition that the target memory address is indicated to be illegal by the validity check result, sending message abnormity indication information to the sending end and releasing the target transmission message. Here, the message exception indication information may be used to indicate that the memory address transferred in the target transfer message is an exception.

For example, taking the target transmission message as the IPC message as an example, after the BufferAddr is obtained, the receiving end may perform parameter check on the BufferAddr, and if the BufferAddr is legal, the receiving end directly uses the BufferAddr and releases the IPC message, and continues to process the next step, and returns an exception and releases the IPC message if the rule is not legal.

By the embodiment, the validity check is performed on the determined memory address, so that the situations that the transmitted message is invalid or the receiving end is affected due to the illegal memory address can be avoided, and the validity of message transmission can be improved.

In an exemplary embodiment, performing a validity check on a target memory address to obtain a validity check result includes: determining that the target memory address is legal under the condition that the target memory address is within a preset address range; and determining that the target memory address is illegal under the condition that the target memory address is out of the preset address range.

The validity check of the target memory address may be to check whether the size of the target memory address is within an expected range. In this embodiment, an address range, that is, a preset address range, may be preset to determine whether the determined memory address is legal.

And determining that the target memory address is legal under the condition that the target memory address is within the preset address range. And under the condition that the target memory address is outside the preset address range, the target memory address can be determined to be illegal.

According to the embodiment, whether the determined memory address is legal or not is determined by presetting the address range of the memory address and checking whether the memory address is located in the address range or not, so that the legal checking efficiency can be improved, and the message transmission efficiency is improved.

The following explains a transmission method of a message in the embodiment of the present application with an alternative example. In this optional example, the target transfer message is an IPC message, the target memory address is a BufferAddr (i.e., a buffer address), the target transfer message is an IPC message, the base address is a BaseAddr, and the address unit size is UnitSize.

Because IPC messages need to be forwarded in multiple layers in the process of transmission among different FUs, the long message length can occupy larger bandwidth and increase the time consumption of command transmission. In this optional example, a method for improving the transmission efficiency of an IPC message is provided, where an absolute 64-bit address is not filled in the message, and a bufferld and bufferLength format is used to transmit the message. During transmission, the sending end calculates the buffer Id and the buffer Length according to the defined BaseAddr and UnitSize and the buffer address to be transmitted, and fills the buffer Id and the buffer Length into the message body, and the receiving end calculates the buffer address according to the defined BaseAddr and UnitSize and the received buffer Id and buffer Length, namely the transmission of the address is completed. Through the simple calculation, the occupied space of the BufferAddr in the message can be greatly compressed, only one 64-bit absolute address can be transmitted by the original 2 Dwords, and 4 or more absolute addresses can be transmitted after the optimization. The method has the advantages that the reduction of the message length is realized by adding simple calculation, the data interaction between processes is optimized, the message transmission efficiency is improved, unnecessary transmission bandwidth waste is reduced, the bus bandwidth is more effectively utilized, and the product performance is favorably improved.

The flow of the message transmission method in this optional example may include the following steps:

step 1, defining BaseAddr and UnitSize during memory initialization.

And step 2, after the transmitting end acquires the BufferAddr, calculating the relative offset of the BufferAddr relative to the base address, determining the bufferId according to a formula bufferadR = (BufferAddr-BaseAddr)/UnitSize, and dividing the size of the buffer to be transmitted by the UnitSize to acquire the buffer Length.

And 3, filling the acquired bufferld and bufferLength into an IPC message structure body, and dynamically adjusting the bit number occupied by each according to the bit number occupied.

And 4, the receiving end receives the IPC message, extracts the bufferId and the bufferLength, and determines the buffer address according to the formula BufferAddr = bufferId UnitSize + BaseAddr and the parameters defined in the step 1.

And 5, after the BufferAddr is obtained, performing parameter check on the BufferAddr to judge whether the BufferAddr is in a legal range, directly using the BufferAddr and releasing the IPC message if the BufferAddr is legal, and returning an exception and releasing the IPC message if the BufferAddr is illegal.

Through the optional example, by adding simple calculation when processing the bufferAddr, the reconstruction of the bufferAddr can be realized, bits occupied by each bufferAddr after reconstruction is reduced, and further the IPC message length is reduced.

It should be noted that, for simplicity of description, the above-mentioned method embodiments are described as a series of acts or combination of acts, but those skilled in the art will recognize that the present application is not limited by the order of acts described, as some steps may occur in other orders or concurrently depending on the application. Further, those skilled in the art should also appreciate that the embodiments described in the specification are preferred embodiments and that the acts and modules referred to are not necessarily required in this application.

Through the description of the foregoing embodiments, it is clear to those skilled in the art that the method according to the foregoing embodiments may be implemented by software plus a necessary general hardware platform, and certainly may also be implemented by hardware, but the former is a better implementation mode in many cases. Based on such understanding, the technical solutions of the embodiments of the present application may be essentially or partially implemented in the form of a software product, where the computer software product is stored in a storage medium (e.g., ROM/RAM, magnetic disk, optical disk), and includes several instructions for enabling a terminal device (e.g., a mobile phone, a computer, a server, or a network device) to execute the methods of the embodiments of the present application.

According to another aspect of the embodiment of the present application, there is further provided a device for transmitting a message, where the device is configured to implement the method for transmitting a message provided in the foregoing embodiment, and details of the description are omitted. As used below, the term "module" may be a combination of software and/or hardware that implements a predetermined function. Although the means described in the embodiments below are preferably implemented in software, an implementation in hardware, or a combination of software and hardware is also possible and contemplated.

Fig. 4 is a block diagram of a transmission apparatus of a message according to an embodiment of the present application, and as shown in fig. 4, the apparatus includes:

a first obtaining unit 402, configured to obtain a target memory address, where the target memory address is a buffer address of a target buffer transmitted by a target transmission message to be transmitted;

a first determining unit 404, configured to determine, according to the base address and the size of the address unit, an identifier value of an address identifier corresponding to the target memory address to obtain a target identifier value;

the first executing unit 406 is configured to write the target identifier value into the message structure of the target transmission message, and transmit the target transmission message to the receiving end of the target transmission message.

According to the method and the device, a target memory address is obtained, wherein the target memory address is a buffer area address of a target buffer area, which is transmitted by a target transmission message to be transmitted; determining an identification value of an address identification corresponding to a target memory address according to the base address and the size of the address unit to obtain a target identification value; the target identification value is written into the message structure of the target transmission message, and the target transmission message is transmitted to the receiving end of the target transmission message, so that the problem of low message transmission efficiency caused by the overlong message to be transmitted in the transmission method of the interprocess communication message in the related technology can be solved, and the message transmission efficiency is improved.

Optionally, the apparatus further comprises:

and a second obtaining unit, configured to obtain the base address and the size of the address unit before determining, according to the base address and the size of the address unit, an identification value of an address identifier corresponding to the target memory address, where the base address and the size of the address unit are set in a process of performing memory initialization.

Optionally, the apparatus further comprises:

and a second execution unit for setting a minimum value of the buffer addresses as a base address and a minimum unit between the storage addresses as an address unit size.

Optionally, the second obtaining unit includes:

and the reading unit is used for reading the base address and the size of the address unit from the preset register.

Optionally, the first determination unit includes:

the first determining module is used for determining the address offset between the target memory address and the base address to obtain the target offset;

and the second determining module is used for determining a target identification value of the address identification corresponding to the target memory address according to the target offset and the size of the address unit.

Optionally, the second determining module includes:

and the determining submodule is used for determining a quotient obtained by dividing the target offset by the size of the address unit as a target identification value of the address identification corresponding to the target memory address.

Optionally, the apparatus further comprises a second determining unit, the first executing unit comprises a writing module, wherein,

a second determining unit, configured to determine a parameter value of a buffer length parameter corresponding to the target memory address according to the size of the buffer of the target buffer and the size of the address unit, to obtain a target length value;

and the writing module is used for writing the target identification value and the target length value into a message structure body of the target transmission message.

Optionally, the second determination unit includes:

and a third determining module, configured to determine a quotient obtained by dividing the size of the buffer area of the target buffer area by the size of the address unit, as a target length value of the buffer area length parameter corresponding to the target memory address.

Optionally, the writing module comprises:

and the writing submodule is used for writing the target identification value and the target length value into a message structure body of the target transmission message according to the bit number occupied by the target identification value and the bit number occupied by the target length value.

Optionally, the apparatus further comprises:

and the adjusting unit is used for dynamically adjusting the bit number occupied by the target identification value and the bit number occupied by the target length value according to the bit number occupied by the target memory address.

Optionally, the adjusting unit comprises:

a fourth determining module, configured to determine the product of the bit number occupied by the target memory address and the preset ratio as the bit number occupied by the target identifier value, and determine the difference between the bit number occupied by the target memory address and the bit number occupied by the target identifier value as the bit number occupied by the target length value.

Optionally, the first determination unit includes:

a fifth determining module, configured to determine, according to the base address and the size of the address unit, an identifier value of an address identifier corresponding to each memory address in the multiple memory addresses respectively when the target memory address includes multiple memory addresses, to obtain an identifier value corresponding to each memory address, where the target identifier value includes the identifier value corresponding to each memory address.

Optionally, the first obtaining unit includes:

and the acquisition module is used for acquiring the absolute address of the target buffer area to obtain the target memory address.

According to another aspect of the embodiment of the present application, there is further provided a device for transmitting a message, where the device is configured to implement the method for transmitting a message provided in the foregoing embodiment, and details of the description are omitted. Fig. 5 is a block diagram of another message transmission apparatus according to an embodiment of the present application, and as shown in fig. 5, the apparatus includes:

a receiving unit 502, configured to receive a target transmission message sent by a sending end;

an extracting unit 504, configured to extract a target identifier value from a message structure of a target transmission message, where the target identifier value is an identifier value of an address identifier corresponding to a target memory address;

a third determining unit 506, configured to determine the target memory address according to the target identifier value, the base address, and the size of the address unit.

According to the embodiment of the application, the target transmission message sent by the sending end is received; extracting a target identification value from a message structure body of the target transmission message, wherein the target identification value is an identification value of an address identification corresponding to a target memory address; and determining the target memory address according to the target identification value, the base address and the size of the address unit, so that the problem of low message transmission efficiency caused by overlong messages needing to be transmitted in the transmission method of the interprocess communication messages in the related technology can be solved, and the message transmission efficiency is improved.

Optionally, the extraction unit comprises:

a sixth determining module, configured to determine a bit number occupied by the target identifier value and a bit number occupied by the target length value, where the target length value is a parameter value of a buffer length parameter corresponding to the target memory address, and the target length value is used to identify a buffer size of a target buffer corresponding to the target memory address;

and the extraction module is used for extracting the target identification value and the target length value from the message structure body of the target transmission message according to the bit number occupied by the target identification value and the bit number occupied by the target length value.

Optionally, the third determining unit includes:

and a seventh determining module, configured to determine a sum of a product of the target identifier value and the address unit size and the base address as the target memory address.

Optionally, the apparatus further comprises:

the checking unit is used for carrying out validity check on the target memory address after the target memory address is determined according to the target identification value, the base address and the size of the address unit to obtain a validity check result;

the third execution unit is used for saving the target memory address and releasing the target transmission message under the condition that the validity check result indicates that the target memory address is valid;

and the fourth execution unit is used for sending message exception indication information to the sending end and releasing the target transmission message under the condition that the validity check result indicates that the target memory address is illegal, wherein the message exception indication information is used for indicating that the memory address transmitted in the target transmission message is abnormal.

Optionally, the inspection unit comprises:

the eighth determining module is used for determining that the target memory address is legal under the condition that the target memory address is within the preset address range;

and the ninth determining module is used for determining that the target memory address is illegal under the condition that the target memory address is out of the preset address range.

It should be noted that, the above modules may be implemented by software or hardware, and for the latter, the following may be implemented, but not limited to: the modules are all positioned in the same processor; alternatively, the modules are respectively located in different processors in any combination.

According to a further aspect of an embodiment of the present application, there is also provided a computer-readable storage medium having a computer program stored therein, wherein the computer program is configured to perform the steps in any of the above method embodiments when executed.

In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to: various media capable of storing computer programs, such as a usb disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a removable hard disk, a magnetic disk, or an optical disk.

According to a further aspect of an embodiment of the present application, there is also provided an electronic device, including a memory in which a computer program is stored and a processor configured to execute the computer program to perform the steps in any of the above method embodiments.

In an exemplary embodiment, the electronic device may further include a transmission device and an input/output device, wherein the transmission device is connected to the processor, and the input/output device is connected to the processor.

For specific examples in this embodiment, reference may be made to the examples described in the above embodiments and exemplary embodiments, and details of this embodiment are not repeated herein.

It will be apparent to those skilled in the art that the modules or steps of the embodiments of the present application described above may be implemented by a general purpose computing device, they may be centralized on a single computing device or distributed across a network of multiple computing devices, they may be implemented by program code executable by a computing device, and thus, may be stored in a storage device and executed by a computing device, and in some cases, the steps shown or described may be performed in an order different from that described herein, or they may be separately fabricated into individual integrated circuit modules, or multiple ones of them may be fabricated into a single integrated circuit module. Thus, embodiments of the present application are not limited to any specific combination of hardware and software.

The above description is only a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and changes may be made to the embodiment by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the principle of the embodiments of the present application shall be included in the protection scope of the embodiments of the present application.

Claims

1. A method for transmitting a message, comprising:

acquiring a target memory address, wherein the target memory address is a buffer area address of a target buffer area transmitted by a target transmission message to be transmitted;

determining an identification value of an address identification corresponding to the target memory address according to the base address and the size of the address unit to obtain a target identification value;

and writing the target identification value into a message structure body of the target transmission message, and transmitting the target transmission message to a receiving end of the target transmission message.

2. The method of claim 1, wherein prior to determining the identification value of the address identifier corresponding to the target memory address based on the base address and the address unit size, the method further comprises:

and acquiring the base address and the size of the address unit, wherein the base address and the size of the address unit are set in the process of initializing the memory.

3. The method of claim 2, further comprising:

setting a minimum value of a buffer address as the base address, and setting a minimum unit of a storage address unit as the address unit size.

4. The method of claim 2, wherein the obtaining the base address and the address unit size comprises:

and reading the base address and the size of the address unit from a preset register.

5. The method of claim 1, wherein determining an identification value of an address identifier corresponding to the target memory address according to the base address and the address unit size to obtain a target identification value comprises:

determining the address offset between the target memory address and the base address to obtain a target offset;

and determining the target identification value of the address identification corresponding to the target memory address according to the target offset and the size of the address unit.

6. The method of claim 5, wherein determining the target tag value of the address tag corresponding to the target memory address according to the target offset and the address unit size comprises:

and dividing the target offset by the size of the address unit to obtain a quotient, and determining the quotient as the target identification value of the address identification corresponding to the target memory address.

7. The method of claim 1,

the method further comprises the following steps: determining a parameter value of a buffer length parameter corresponding to the target memory address according to the size of the buffer of the target buffer and the size of the address unit to obtain a target length value;

the writing of the target identification value to the message structure of the target transfer message includes: and writing the target identification value and the target length value into a message structure body of the target transmission message.

8. The method according to claim 7, wherein the determining a parameter value of a buffer length parameter corresponding to the target memory address according to the buffer size of the target buffer and the address unit size to obtain a target length value comprises:

and determining the quotient obtained by dividing the size of the buffer area of the target buffer area by the size of the address unit as the target length value of the buffer area length parameter corresponding to the target memory address.

9. The method of claim 7, wherein writing the target identification value and the target length value to a message structure of the target transfer message comprises:

and writing the target identification value and the target length value into a message structure of the target transmission message according to the bit number occupied by the target identification value and the bit number occupied by the target length value.

10. The method of claim 9, further comprising:

and dynamically adjusting the bit number occupied by the target identification value and the bit number occupied by the target length value according to the bit number occupied by the target memory address.

11. The method according to claim 10, wherein the dynamically adjusting the number of bits occupied by the target identifier and the number of bits occupied by the target length value according to the number of bits occupied by the target memory address comprises:

and determining the product of the bit number occupied by the target memory address and a preset proportion as the bit number occupied by the target identification value, and determining the difference value of the bit number occupied by the target memory address and the bit number occupied by the target identification value as the bit number occupied by the target length value.

12. The method of claim 1, wherein determining an identification value of an address identifier corresponding to the target memory address according to the base address and the address unit size to obtain a target identification value comprises:

and under the condition that the target memory address comprises a plurality of memory addresses, respectively determining an identification value of an address identification corresponding to each memory address in the plurality of memory addresses according to the base address and the size of the address unit, and obtaining an identification value corresponding to each memory address, wherein the target identification value comprises the identification value corresponding to each memory address.

13. The method of any one of claims 1 to 12, wherein the obtaining the target memory address comprises:

and acquiring the absolute address of the target buffer area to obtain the target memory address.

14. A method for transmitting a message, comprising:

receiving a target transmission message sent by a sending end;

extracting a target identification value from a message structure body of the target transmission message, wherein the target identification value is an identification value of an address identification corresponding to a target memory address;

and determining the target memory address according to the target identification value, the base address and the size of the address unit.

15. The method of claim 14, wherein extracting the target identification value from the message structure of the target transfer message comprises:

determining the number of bits occupied by the target identification value and the number of bits occupied by a target length value, wherein the target length value is a parameter value of a buffer length parameter corresponding to the target memory address, and the target length value is used for identifying the size of a buffer of a target buffer corresponding to the target memory address;

and extracting the target identification value and the target length value from a message structure body of the target transmission message according to the bit number occupied by the target identification value and the bit number occupied by the target length value.

16. The method of claim 14, wherein determining the target memory address based on the target identification value, the base address, and the address unit size comprises:

and determining the sum of the product of the target identification value and the size of the address unit and the base address as the target memory address.

17. The method of claim 14, wherein after said determining the target memory address based on the target identification value, the base address, and the address location size, the method further comprises:

carrying out validity check on the target memory address to obtain a validity check result;

under the condition that the validity check result indicates that the target memory address is valid, storing the target memory address and releasing the target transmission message;

and under the condition that the target memory address is indicated to be illegal by the validity check result, sending message abnormity indication information to the sending end, and releasing the target transmission message, wherein the message abnormity indication information is used for indicating that the memory address transmitted in the target transmission message is abnormal.

18. The method of claim 17, wherein the checking the target memory address for validity to obtain a validity check result comprises:

determining that the target memory address is legal under the condition that the target memory address is within a preset address range;

and determining that the target memory address is illegal under the condition that the target memory address is out of a preset address range.

19. An apparatus for transmitting a message, comprising:

the device comprises a first obtaining unit, a second obtaining unit and a processing unit, wherein the first obtaining unit is used for obtaining a target memory address, and the target memory address is a buffer area address of a target buffer area transmitted by a target transmission message to be transmitted;

the first determining unit is used for determining an identification value of an address identification corresponding to the target memory address according to the base address and the size of the address unit to obtain a target identification value;

and the first execution unit is used for writing the target identification value into a message structure body of the target transmission message and transmitting the target transmission message to a receiving end of the target transmission message.

20. An apparatus for transmitting a message, comprising:

the receiving unit is used for receiving a target transmission message sent by a sending end;

the extracting unit is used for extracting a target identification value from a message structure body of the target transmission message, wherein the target identification value is an identification value of an address identification corresponding to a target memory address;

and the third determining unit is used for determining the target memory address according to the target identification value, the base address and the size of the address unit.

21. A computer-readable storage medium, in which a computer program is stored which, when being executed by a processor, carries out the steps of the method according to any one of claims 1 to 18.

22. An electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, characterized in that the steps of the method as claimed in any of claims 1 to 18 are implemented when the computer program is executed by the processor.