CN202093503U

CN202093503U - Apparatus for on-line upgrading FPGA logic

Info

Publication number: CN202093503U
Application number: CN2010206711042U
Authority: CN
Inventors: 白宗元; 张磊; 李静; 刘朝辉; 李锋伟
Original assignee: Dawning Information Industry Co Ltd
Current assignee: Dawning Information Industry Co Ltd
Priority date: 2010-12-17
Filing date: 2010-12-17
Publication date: 2011-12-28
Anticipated expiration: 2020-12-17

Abstract

The utility model provides an apparatus for on-line upgrading FPGA (field programmable gate array) logic. The apparatus comprises a remote terminal, a controlling terminal, an FPGA programmable logic gate circuit and a PROM (programmable read-only memory ); the FPGA programmable logic gate circuit is connected with the remote terminal by a PCIE (peripheral component Interconnect - express) bus, and is connected with the PROM by an IO (input-output) interface. If logic programming needs to be performed in a complex environment that is not suitable for a worker to work in-site, the method of the utility model can solve the problem of upgrading conveniently; the apparatus doesn't need power off or restarting, can accomplish the upgrading only by hot resetting the system after automatic loading; can realize remote operation; saves manpower and material resource, and is operated simply and conveniently.

Description

A kind of device of online upgrading fpga logic

Technical field

The utility model relates to integrated circuit board logical update field, is specifically related to a kind of device of online upgrading fpga logic.

Background technology

Require to be not suitable for the staff and to go the programming logic to the scene in some environment more complicated, confidentiality, adopt traditional private cable programming load mode obviously can not meet the demands than under the condition with higher; In the present circumstance, the mode that the staff adopts private cable at the scene logic to be upgraded more makes that the enforceability of work is relatively more difficult.

CN200610156169.1 discloses the method for automatic download of a kind of FPGA of realization and online upgrading, wherein, realizes that the method that FPGA downloads automatically comprises the steps: the download bus interface of FPGA is connected with the general programmable input/output interface of CPU; The downloading mode of FPGA is set; CPU will download from nonvolatile semiconductor memory member by the Flash bus and read; Downloading that CPU will read writes among the FPGA by general programmable input/output interface signal bus, finishes until download.

This method the upgrading process in, need CPU from nonvolatile semiconductor memory member, to read to download to be written to then among the FPGA, and being power down, FPGA promptly loses logic, each upgrading also needs the participation of CPU, make efficient not high, and after repeatedly upgrading, can not well write down the information of upgrade logic.

Summary of the invention

The device that the utility model purpose is to propose a kind of online upgrading fpga logic solves some and is not suitable for staff's local logical update of working.

A kind of device of online upgrading fpga logic comprises remote terminal, control end, FPGA FPGA (Field Programmable Gate Array) gate circuit and PROM.

First kind of optimal technical scheme of the present utility model is: described control end logs on remote terminal by the windows remote desktop.

Second kind of optimal technical scheme of the present utility model is: described FPGA FPGA (Field Programmable Gate Array) gate circuit is connected with remote terminal by the PCIE bus, is connected with PROM by the IO interface.

The third optimal technical scheme of the present utility model is: earlier upgrade file is downloaded to remote terminal during upgrading, control end control remote terminal writes PROM by FPGA FPGA (Field Programmable Gate Array) gate circuit with file then.

The utility model in some environment more complicated, be not suitable for the staff and go under the situation of programming logic to on-the-spot, adopt this method can solve upgrade problem very easily, and do not need power-off restarting, automatically loading the back only need can finish system's hot reset, but operated from a distance, use manpower and material resources sparingly, simple to operation.

Description of drawings

Fig. 1 is the utility model apparatus structure synoptic diagram

Specific embodiments

The utility model is implemented in systems programming PROM chip, and do not realize by downloading line, therefore we adopt the logic in the PROM chip to be written are write scheme among the PROM by upper layer software (applications) by the PCIE interface, Fig. 1 is the utility model apparatus structure synoptic diagram, comprise remote terminal, control end, FPGA FPGA (Field Programmable Gate Array) gate circuit and PROM.

1, the download bus interface with FPGA realizes being connected by the PCIE bus interface with remote terminal;

2, control end writes logical file and the logical message that will upgrade by windows remote desktop control remote terminal by the PCIE bus in nonvolatile semiconductor memory member, comprises version number, update time information;

3, the upgrade logic that writes among the FPGA that finishes will carry out verification to the content of write non-volatile memory spare, with the correctness that guarantees to write;

4, write end after, carry out automatic load instructions, finish loading procedure, do not need the integrated circuit board power-off restarting, only need the hot reset can the completion logic escalation process, only need power on after the power down and restart also the process that can completion logic loads.

Claims

1. the device of an online upgrading fpga logic, it is characterized in that: comprise remote terminal, control end, FPGA FPGA (Field Programmable Gate Array) gate circuit and PROM, described FPGA FPGA (Field Programmable Gate Array) gate circuit is connected with remote terminal by the PCIE bus, is connected with PROM by the IO interface.