CN111813432A

CN111813432A - FPGA configuration upgrading method and FPGA platform

Info

Publication number: CN111813432A
Application number: CN202010485275.4A
Authority: CN
Inventors: 王闯; 熊伟; 龚宗跃; 杨敬
Original assignee: Datang Microelectronics Technology Co Ltd
Current assignee: Datang Microelectronics Technology Co Ltd
Priority date: 2020-06-01
Filing date: 2020-06-01
Publication date: 2020-10-23

Abstract

The invention discloses a field programmable gate array FPGA configuration upgrading method, which comprises the following steps: the FPGA loads automatic loading logic data contained in a first storage area of a non-volatile memory FLASH; executing the automatic loading logic data, and acquiring new application configuration data after data erasing is carried out on the second storage area of the FLASH; and writing the new application configuration data into a second storage area of the FLASH. The invention also discloses a field programmable gate array FPGA platform.

Description

FPGA configuration upgrading method and FPGA platform

Technical Field

The invention relates to the technical field of computers, in particular to a Field Programmable Gate Array (FPGA) configuration upgrading method and an FPGA platform.

Background

The FPGA has the characteristics of strong data processing capacity, dynamic reconfiguration of functions and the like, and is widely applied to various fields of communication, aviation and the like. The product function is often tested and debugged in the product design and development, the FPGA configuration file needs to be configured continuously in the process, and even if the product stage is started, the FPGA configuration file also needs to be updated and iterated along with the product evolution. Configuration upgrading of FPGA data files is an important part in the FPGA development and application process. They are not professional FPGA development designers for the customer and do not know the professional FPGA download configuration tools, thus increasing the technical threshold used by the customer. For a development tool VIVADOH or ISE of a XILINX FPGA, 20Gb disk space is probably needed after installation, and for some old equipment, the occupied space is large, and the use cost is increased. Even if the IMPACT programming tool is installed singly, the FPGA can be smoothly configured and upgraded by professional operation. In order to solve the problem, the invention provides a method for programming a configuration storage unit FLASH by using FPGA internal logic resources on the premise of basically not changing the hardware state of a product, thereby realizing the updating and upgrading of FPGA platform configuration data. The common configuration method for the FPGA product is complex in operation, an additional control chip and a corresponding configuration circuit are required to be added, and the circuit structure is complex.

The prior art mainly has two schemes: one is to configure and upgrade the FPGA through professional FPGA configuration software of XILINX corporation such as IMPACT, and the like, and this scheme needs to select the model of the FPGA chip, the model of the configuration memory chip, the configuration mode, and the like, and is complex to operate, and causes difficulty for non-professional developers such as testing and clients. The second is to directly configure the FPGA or program a storage chip for configuring the FPGA by a third-party control chip, a DSP, a CPLD, an MCU and the like, so as to realize the function of configuration and upgrade of the FPGA. The method needs to add an additional control chip and a corresponding circuit in the original circuit design of the product, thereby increasing the cost of a hardware circuit and increasing the power consumption of the product. Meanwhile, unnecessary interference is added to the signal lines of the product under the condition that board-level space and routing are required. Secondly, after the software and hardware operation of the MCU is increased, the failure probability is increased, because the MCU not only needs to perform read-write operation on the memory chip, but also needs to simulate the power-on loading process of the FPGA, if the loading is unsuccessful, not only the upgrading function of the product fails, but also the basic function of the product fails.

How to provide an FPGA configuration upgrading scheme with simple and convenient operation through smaller hardware modification is necessary.

Disclosure of Invention

In order to solve the above technical problems, embodiments of the present invention provide an FPGA configuration upgrading method and an FPGA platform, which do not need to add an additional control chip and a corresponding supporting circuit, and implement an FPGA configuration upgrading function on the premise of slightly changing the function state of an original hardware circuit.

The embodiment of the invention provides a field programmable gate array FPGA configuration upgrading method, which comprises the following steps:

the FPGA loads automatic loading logic data contained in a first storage area of a non-volatile memory FLASH;

executing the automatic loading logic data, and acquiring new application configuration data after data erasing is carried out on the second storage area of the FLASH; and writing the new application configuration data into a second storage area of the FLASH.

The embodiment of the present invention further provides a field programmable gate array FPGA platform, which is characterized by comprising: the FPGA and a nonvolatile memory FLASH for configuring the FPGA;

the FPGA is set to load the automatic loading logic data contained in the first storage area of the FLASH;

the FPGA is also set to execute the automatic loading logic data, and obtain new application configuration data after the second storage area of the FLASH is subjected to data erasure; and writing the new application configuration data into a second storage area of the FLASH.

It can be seen that all operations on the configuration chip (FLASH) provided by the scheme provided by the embodiment of the invention are realized by the internal logic of the FPGA, and the circuit has the advantages of simple and stable structure and low cost.

Drawings

Fig. 1 is a flowchart of an FPGA configuration upgrading method according to an embodiment of the present invention;

FIG. 2 is a schematic structural diagram of an FPGA platform and related devices in the second, third and eighth embodiments of the present invention;

fig. 3 is a flowchart of an FPGA configuration upgrading method according to the second embodiment;

FIG. 4 is a diagram illustrating a structure of an FPGA platform according to a second embodiment;

FIG. 5 is a schematic structural diagram of an FPGA platform according to a third embodiment;

fig. 6 is an interaction flowchart of an FPGA configuration upgrading method according to the third embodiment;

fig. 7 is another flowchart of an FPGA configuration upgrading method according to the third embodiment;

FIG. 8 is a diagram illustrating a structure of an FPGA platform according to a fourth embodiment;

fig. 9 is a schematic structural diagram of an FPGA platform in the sixth embodiment.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in further detail with reference to the accompanying drawings and specific embodiments. It should be noted that the embodiments and features of the embodiments in the present application may be arbitrarily combined with each other without conflict.

Example one

The embodiment of the invention provides a field programmable gate array FPGA configuration upgrading method, as shown in FIG. 1, comprising the following steps:

step 101, loading automatic loading logic data contained in a first storage area of a non-volatile memory FLASH by an FPGA;

102, executing the automatic loading logic data, and after performing data erasure on the second storage area of the FLASH, acquiring new application configuration data; and writing the new application configuration data into a second storage area of the FLASH.

Optionally, wherein the FLASH includes the first storage area and the second storage area;

the first storage area is a storage area with the highest address of 0 in the FLASH, and the second storage area is a storage area with the highest address of 1 in the FLASH;

alternatively, the first and second electrodes may be,

the first storage area is a storage area with the highest address of 1 in the FLASH, and the second storage area is a storage area with the highest address of 0 in the FLASH.

Optionally, the loading, by the FPGA, the automatic loading logic data included in the first storage area of the non-volatile memory FLASH includes:

when the first storage area is a storage area with the highest address of the FLASH being 0, and the highest address of the FLASH is in a low level, loading automatic loading logic data contained in the first storage area of the FLASH;

alternatively, the first and second electrodes may be,

and when the first storage area is a storage area with the highest address of the FLASH being 1, loading the automatic loading logic data contained in the first storage area of the FLASH when the highest address of the FLASH is at a high level.

Optionally, the loading, by the FPGA, of the automatic loading logic data included in the first storage area of the nonvolatile memory FLASH in step 101 includes:

when the first storage area is a storage area with the highest address of the FLASH being 0, and the highest address of the FLASH is in a low level, loading automatic loading logic data contained in the first storage area of the FLASH, and setting the FLASH to be not allowed to be erased;

alternatively, the first and second electrodes may be,

and when the first storage area is a storage area with the highest address of 1, loading the automatic loading logic data contained in the first storage area of the FLASH when the highest address of the FLASH is at a high level, and setting the FLASH to be not allowed to be erased.

Optionally, the erasing data from the second storage area of the FLASH in step 102 includes:

when the first storage area is a storage area with the highest address of the FLASH being 0, the highest address of the FLASH is at a high level, and the FLASH is allowed to be erased, and data erasing is carried out on a second storage area of the FLASH;

or when the first storage area is the storage area with the highest address of 1 of the FLASH, the highest address of the FLASH is at a low level and the FLASH is allowed to be erased, and data erasing is carried out on the second storage area of the FLASH.

Optionally, when the general purpose input/output GPIO port of the FPGA platform is at a low level, the FLASH is not allowed to be erased; when the GPIO port of the FPGA platform is at a high level, the FLASH is allowed to be erased and written;

alternatively, the first and second electrodes may be,

when the general purpose input/output GPIO port of the FPGA platform is at a high level, the FLASH is not allowed to be erased and written; when the GPIO port of the FPGA platform is in a low level, the FLASH is allowed to be erased and written.

Optionally, the acquiring new application configuration data in step 102 includes:

receiving the new application configuration data from an upper computer;

or, reading the new application configuration data from a preset external storage device.

Optionally, after writing the new application configuration data into the second storage area of the FLASH, the method further includes:

and 103, reloading the FPGA according to the new application configuration data in the second storage area of the FLASH so as to update the application of the FPGA.

and acquiring the encrypted new application configuration data, and executing a decryption instruction in the automatic loading logic data to obtain the decrypted new application configuration data.

Optionally, when receiving the new application configuration data from the upper computer, the receiving the new application configuration data includes:

receiving the new application configuration data by communicating with the upper computer through any one of the following interfaces: the device comprises a serial port, a USB interface, an SPI interface and an IIC interface;

alternatively, the first and second electrodes may be,

utilizing a general purpose input/output GPIO port of an FPGA platform, realizing any one of the following interfaces through the communication logic in the automatic loading logic data, and then communicating with the upper computer to receive the new application configuration data: UART interface, IIC interface, SPI interface.

Example two

The embodiment of the invention provides a method for upgrading FPGA configuration, wherein the equipment environment executed by the method is shown in figure 2 and comprises an upper computer and a PFGA platform, and the upper computer is connected with the FPGA platform through a serial port communication interface. The block diagram marked by the FPGA is a logic function realized by the FPGA chip, namely the FPGA indicated in the application. The main control FPGA chip of the FPGA platform for debugging is a Kintex-7 series XC7K160T chip of XILINX company, the model of the FLASH configuration chip is PC28F00AP30TF, and the storage capacity is 1 Gbit. The computer is connected with the equipment through RS-232, asynchronous serial communication is adopted, the baud rate is 11520, 8-bit data bits, no odd check exists, and 1-bit stop bit exists.

The upper computer mainly sends the FPGA configuration file to the FPGA through a serial port, and meanwhile, the read-back and verification functions of data can be completed. The FPGA driving logic part mainly comprises serial port driving logic, FLASH control programming logic and interface logic parts of the serial port driving logic and the FLASH control programming logic. The serial port module performs data interaction with the computer, receives configuration data sent by the upper computer and feeds corresponding state information back to the upper computer. The FLASH read-write control module realizes relevant operations such as FLASH erasing, programming and readback.

In this embodiment, the configuration storage unit FLASH is programmed (written) by using the internal logic resource of the FPGA, so as to update and upgrade the configuration data of the FPGA platform. As shown in FIG. 3, the FLASH memory space is physically partitioned by performing high-low switching control on the highest address A [26] of FLASH. The FLASH address space may be divided into a 0000000-1FFFFFF lower half area and a 2000000-3FFFFFF upper half area. The lower half area is used as a storage space for loading logic function data of the FPGA (called data storage space for automatic load function for short); the upper half area is used as a product application configuration data storage space. The lower half here is the first storage area and the upper half is the second storage area.

In the normal product application process, the dial switch K1 connected with A26 is kept in off state, A26 is kept in high state, and after the FPGA platform is electrified, the upper half area data (product application data) of the FLASH is loaded to be used as product application.

When the application data of the FPGA product needs to be configured and updated (upgraded), the flow is shown in fig. 3, and the FPGA platform system is shown in fig. 4, and includes:

step 301, a dial switch K1 connected to a FLASH address a [26] is closed, a [26] is kept low all the time, the FPGA platform is powered off, and after the FPGA platform is powered on again, the platform is loaded with the data (auto load function logic data, namely, auto load logic data) in the lower half area, and then the platform enters the auto load function state.

Step 302, after the loading is finished, the dial switch K1 is switched off, and the autoload logic function is executed to erase the data in the upper half area of the FLASH; namely, the FPGA operates the storage space of the upper half area of the FLASH, namely the application configuration data area.

And step 303, sending new application configuration data by the upper computer through the serial port, receiving the product application data by the serial port logic part in the FPGA, and writing the new application configuration data into the upper half area of the FLASH through FLASH operation logic.

After step 303, the application configuration upgrade is completed.

And powering off the FPGA platform again and then powering on, wherein the running data is the updated application configuration data.

EXAMPLE III

The FPGA platform adopted in this embodiment is added with a FLASH write protection function on the basis of the second embodiment, where the write protection is turned on to indicate that FLASH erasing is allowed, and the write protection is turned off to indicate that FLASH erasing is not allowed, for example, in fig. 5, the P1 connection circuit realizes a function of preventing a misoperation (write protection function), protects the application data of the product from being updated to the upper half area of FLASH, and does not rewrite the lower half area of FLASH, that is, the autoload logic configuration data area. The realization principle is that K1 and K2 are kept synchronous during operation, and the erasing operation of FLASH can not be carried out when P1 is low. It is defined that the state is 11 when both of K1 and K2 are open, and the state is 00 when both of K1 and K2 are closed. That is, K1K2 can overwrite the upper half of FLASH data only if it is switched to the 11 state. When the user forgets to turn off the K1, the operation address space corresponding to the FPGA is the FLASH lower half memory space, but is not rewritten. The P1 is write protection of FLASH, the low P1 indicates that the write protection is closed and the FLASH can not be erased, and the high P1 indicates that the write protection is opened and the FLASH can be erased. Optionally, the P1 is connected to a general purpose input output GPIO port of the FPGA.

Before the FPGA configuration upgrading method is carried out, developers firstly write the logic data of the autoload function (completing the functions of uart transceiving logic, FLASH programming control logic and the like), namely the logic data which is automatically loaded, into the lower half area of the FLASH in advance. Writing can be completed through professional tools such as an impact tool, and the FPGA configuration automatic upgrading function can be completed without other tools.

The embodiment provides a method for upgrading an FPGA configuration, as shown in fig. 6, the steps are as follows:

step 601, dialing the FPGA platform dial switch K2K1 shown in FIG. 5 to a closed state, that is, A [26] and P1 are both low;

step 602, powering on an FPGA platform; at this time, the FPGA loads the data of the lower half area of the FLASH, namely, the autoload functional logic data is loaded, at this time, the platform is in an autoload functional state, but the K2K1 is in a 00 state, and the FLASH cannot be erased;

step 603, dialing FPGA platform dial switch K2K1 to off state, namely A [26] and P1 are both high; at the moment, the K2K1 is in the 11 state, the autoload function is executed, the erasing operation is started to be carried out on the upper half area of the FLASH, after the erasing operation is finished, the data are fed back to the upper computer through the serial port, and the FPGA is in the state of waiting for receiving the data of the upper computer;

step 604, the upper computer sends new application configuration data to the FPGA platform;

after receiving the erasure completion information fed back by the FPGA platform, the upper computer loads and sends application configuration data to be updated through a serial assistant or other upper computer software, and waits for the completion of data sending;

optionally, the new application configuration data is product application configuration file data generated in a XILINX vivadd tool; or new application configuration data generated by other tools, not limited to the specific tools exemplified in this embodiment; optionally, if encryption is required, encryption may be performed by using a selected encryption algorithm, and corresponding decryption logic may be added to the corresponding autoload function logic.

605, after the upper computer software prompts that the data is sent, waiting for the completion of the feedback programming of the autoload logic function; correspondingly, the FPGA platform executes the autoload logic function to write the received new application configuration data into the upper half area of the FLASH;

606, powering off the FPGA platform after the upper computer receives the FPGA platform feedback write-in completion operation;

and step 607, electrifying the FPGA platform and finishing the operation. At this time, the FPGA loads the data in the upper half area of the FLASH, that is, the updated application configuration data, and at this time, the FPGA platform is in the updated application function state.

The method for upgrading the FPGA configuration described in this embodiment may also refer to the process shown in fig. 7.

Example four

The embodiment of the invention provides a method for upgrading FPGA configuration, wherein the equipment environment executed by the method is shown in figure 8 and comprises an upper computer and a PFGA platform, and the upper computer is connected with the FPGA platform through a serial port communication interface. Fig. 8 is that an encryption/decryption logic portion is added on the basis of fig. 2, encryption/decryption processing needs to be performed on an FPGA application configuration file (data), and an encryption/decryption logic portion is added in an internal logic function of the FPGA, that is, the encryption/decryption logic is also correspondingly included in the automatic loading logic data of the second or third embodiment.

And when the received new application configuration data is encrypted data, the FPGA executes decryption logic firstly and then writes the decryption logic into the upper half area of the FLASH. Referring to the flow of the second or third embodiment, one skilled in the art may determine to modify step 303 or step 605 accordingly.

EXAMPLE five

Compared with the second, third and fourth embodiments, when communicating with the upper computer, the embodiment of the present invention optionally may use any communication protocol and tool, such as USB (Universal Serial Bus), SPI (Serial Peripheral Interface), IIC (Integrated Circuit Bus), etc., to communicate with the upper computer, thereby completing the function of upgrading the FPGA configuration. The method is realized by only changing the serial port transceiving logic in the autoload into the control logic of the corresponding communication protocol. If the FPGA platform used does not have a communication port, GPIO can be used for realizing communication functions of UART (Universal asynchronous receiver Transmitter/Transmitter), IIC, SPI and the like by utilizing a communication logic part in the autoload.

EXAMPLE six

Compared with the second, third and fourth embodiments, the embodiment of the invention provides a method for upgrading FPGA configuration, wherein the upper computer completes interaction with an FPGA platform, and is only used for realizing the function of issuing application configuration data. The invention can also utilize any storage media such as SD card, U disk and the like to match with the automatic load logic function to complete the configuration upgrade of FPGA, taking the SD card as an example, as shown in FIG. 9, only SD Controller logic codes are added in the automatic load control logic to read the configuration data from the SD card and program and write the configuration data into FLASH, and the operation becomes more concise because no observation and operation of an upper computer is needed. When other storage media are used, only corresponding read-write control drive logic needs to be added into the autoload control logic code.

EXAMPLE seven

Compared with the second, third and fourth embodiments, the first storage area and the second storage area are set oppositely, and the upper half area of the FLASH is used as the first storage area, and the lower half area of the FLASH is used as the second storage area. Accordingly, the switch or closing of the corresponding dial switch K1 may be adjusted.

Optionally, the FLASH is divided into two or more regions, for example, into 3 regions or 4 regions, including the first storage region and the second storage region, without limiting the use of other regions. Correspondingly, according to the determined difference of the highest addresses of the first storage area and the second storage area, setting dial switches correspondingly, for example, if the highest 2-bit address is the corresponding first storage area of 11, and the highest 2-bit address is the corresponding second storage area of 10, then loading the auto-loading logic data when the corresponding address dial switch X1X2 is equal to 11; for another example, if the address of the highest 2 bits is 00 for the first storage area and the address of the highest 2 bits is 01 for the second storage area, the corresponding address dial switch X1X2 is loaded with the auto-load logic data when it is 00. Others, and so on, will be apparent to those skilled in the art.

Example eight

The present embodiment provides a field programmable gate array FPGA platform 10, as shown in fig. 2, including: FPGA101 and FLASH 102;

the FPGA101 is configured to load the automatic loading logic data contained in the first storage area of the FLASH 102;

the FPGA101 is further configured to execute the automatic loading of the logic data, and obtain new application configuration data after performing data erasure on the second storage area of the FLASH 102; and writing the new application configuration data into a second storage area of the FLASH 102.

Optionally, wherein the FLASH102 comprises the first storage area and the second storage area;

the first storage area is a storage area with the highest address of 0 in the FLASH102, and the second storage area is a storage area with the highest address of 1 in the FLASH 102;

alternatively, the first and second electrodes may be,

the first storage area is a storage area with the highest address of 1 in the FLASH102, and the second storage area is a storage area with the highest address of 0 in the FLASH 102.

Optionally, the loading, by the FPGA101, of the automatic loading logic data contained in the first storage area of the non-volatile memory FLASH102 includes:

when the first storage area is a storage area with the highest address of the FLASH102 being 0, and the highest address of the FLASH102 is in a low level, loading automatic loading logic data contained in the first storage area of the FLASH 102;

alternatively, the first and second electrodes may be,

and when the highest address of the FLASH102 is in a high level when the first storage area is the storage area with the highest address of the FLASH102 being 1, loading the automatic loading logic data contained in the first storage area of the FLASH 102.

Optionally, the loading, by the FPGA101, the auto-loading logic data contained in the first storage area of the non-volatile memory FLASH102 includes:

when the highest address of the FLASH102 is in a low level when the first storage area is a storage area with the highest address of the FLASH102 being 0, loading automatic loading logic data contained in the first storage area of the FLASH102, and setting the FLASH102 to be not allowed to be erased;

alternatively, the first and second electrodes may be,

when the first storage area is a storage area with the highest address of the FLASH102 being 1, and the highest address of the FLASH102 is at a high level, loading the automatic loading logic data contained in the first storage area of the FLASH102, and setting the FLASH102 to be not allowed to be erased.

Optionally, the erasing data from the second storage area of the FLASH102 includes:

when the first storage area is a storage area with the highest bit address of the FLASH102 being 0, the highest bit address of the FLASH102 is at a high level and the FLASH102 is allowed to be erased, and data erasing is carried out on a second storage area of the FLASH;

or, when the first storage area is a storage area with the highest address of the FLASH102 being 1, the highest address of the FLASH102 is at a low level and the FLASH102 is allowed to be erased, and data erasing is performed on the second storage area of the FLASH 102.

Optionally, when the GPIO port of the FPGA platform 10 is at a low level, the FLASH102 is not allowed to be erased; when the GPIO port of the FPGA platform 10 is at a high level, the FLASH102 is allowed to be erased and written;

alternatively, the first and second electrodes may be,

when the general purpose input/output GPIO port of the FPGA platform 10 is at a high level, the FLASH102 is not allowed to be erased; when the GPIO port of the FPGA platform 10 is low, the FLASH102 is erasable.

Optionally, the acquiring, by the FPGA101, new application configuration data includes:

receiving the new application configuration data from an upper computer;

Optionally, the FPGA101 is further configured to, after writing the new application configuration data into the second storage area of the FLASH102, reload the new application configuration data according to the second storage area of the FLASH102, so as to update the application of the FPGA.

alternatively, the first and second electrodes may be,

Compared with the prior art, the circuit is extremely simple, under the condition that a FLASH erasing protection function is not used (no P1 is arranged, as shown in figure 3), other port resources of the FPGA are not additionally occupied, only one dial switch circuit is externally connected, if the original platform circuit does not exist, the circuit can be completed through pin flying, the hardware state of a product function circuit is basically not changed, and the performance of a product application circuit is not influenced. Meanwhile, the characteristic that the logic of the FPGA can be dynamically reconfigured is utilized, control chips and control circuits such as an MCU (microprogrammed control Unit), a DSP (digital signal processor) and the like are replaced, and the cost is low. All operations of the configuration chip (FLASH) are realized by internal logic of the FPGA (automatic loading logic in the first storage area), so that the circuit structure is simple and stable.

The upper computer uses the serial assistant as an operation interface, avoids the complexity of the operation of IMPACT professional tools, reduces the use threshold, is friendly to clients and convenient for the clients to use, and the scheme can utilize any original communication interface of the platform, and if no communication port exists, GPIO can be used to realize communication functions of UART, IIC, SPI and the like by utilizing a communication logic part in autoload, thereby having good portability and expansibility.

It will be understood by those of ordinary skill in the art that all or some of the steps of the methods, systems, functional modules/units in the devices disclosed above may be implemented as software, firmware, hardware, and suitable combinations thereof. In a hardware implementation, the division between functional modules/units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component may have multiple functions, or one function or step may be performed by several physical components in cooperation. Some or all of the components may be implemented as software executed by a processor, such as a digital signal processor or microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit. Such software may be distributed on computer readable media, which may include computer storage media (or non-transitory media) and communication media (or transitory media). The term computer storage media includes volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data, as is well known to those of ordinary skill in the art. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, Digital Versatile Disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can accessed by a computer. In addition, communication media typically embodies computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and includes any information delivery media as known to those skilled in the art.

Claims

1. A field programmable gate array FPGA configuration upgrading method comprises the following steps:

2. The method of claim 1, wherein,

the FLASH comprises the first storage area and the second storage area;

alternatively, the first and second electrodes may be,

3. The method of claim 2, wherein,

the automatic loading logic data contained in the first storage area of the FPGA loading nonvolatile memory FLASH comprises the following steps:

alternatively, the first and second electrodes may be,

4. The method of claim 2, wherein,

alternatively, the first and second electrodes may be,

5. The method of claim 2, wherein,

the erasing data of the second storage area of the FLASH comprises the following steps:

6. The method according to any one of claims 4 or 5,

when the general purpose input/output GPIO port of the FPGA platform is in low level, the FLASH is not allowed to be erased and written; when the GPIO port of the FPGA platform is at a high level, the FLASH is allowed to be erased and written;

alternatively, the first and second electrodes may be,

7. The method of any one of claims 1-5,

the acquiring new application configuration data includes:

receiving the new application configuration data from an upper computer;

or, reading the new application configuration data from a preset external storage device;

or acquiring the encrypted new application configuration data, and executing a decryption instruction in the automatic loading logic data to obtain the decrypted new application configuration data.

8. The method of any one of claims 1-5,

after writing the new application configuration data into the second storage area of the FLASH, the method further includes:

and the FPGA reloads according to the new application configuration data in the second storage area of the FLASH, so that the application of the FPGA is updated.

9. The method of claim 7, wherein,

when receiving the new application configuration data from the upper computer, the receiving the new application configuration data includes:

receiving the new application configuration data by communicating with the upper computer through any one of the following interfaces: the system comprises a serial port, a Universal Serial Bus (USB) interface, a serial peripheral equipment (SPI) interface and an integrated circuit bus (IIC) interface;

alternatively, the first and second electrodes may be,

utilizing a general purpose input/output GPIO port of an FPGA platform, realizing any one of the following interfaces through the communication logic in the automatic loading logic data, and then communicating with the upper computer to receive the new application configuration data: the universal asynchronous receiving and transmitting transmitter UART interface, the integrated circuit bus IIC interface and the serial peripheral equipment SPI interface.

10. A Field Programmable Gate Array (FPGA) platform, comprising: the FPGA and a nonvolatile memory FLASH for configuring the FPGA;