CN113590153A - Firmware upgrading method, system, equipment and medium for CPLD - Google Patents
Firmware upgrading method, system, equipment and medium for CPLD Download PDFInfo
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- G06F8/00—Arrangements for software engineering
- G06F8/60—Software deployment
- G06F8/65—Updates
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0646—Horizontal data movement in storage systems, i.e. moving data in between storage devices or systems
- G06F3/0652—Erasing, e.g. deleting, data cleaning, moving of data to a wastebasket
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Abstract
The invention discloses a firmware upgrading method of a CPLD, which comprises the following steps: the processor sends an upgrading instruction to the CPLD so that the CPLD erases the corresponding firmware storage area according to the upgrading instruction; updating the value of the first register to a first preset value in response to the completion of erasing the firmware storage area by the CPLD; in response to the processor detecting that the value of the first register is updated to a first preset value, writing firmware upgrading data into the second register, and updating the value of the third register to a second preset value after the firmware upgrading data is completely written into the second register; and reading the firmware upgrading data in the second register and writing the firmware upgrading data into the firmware storage area in response to the CPLD detecting that the value of the third register is updated to the second preset value. The invention also discloses a system, a computer device and a readable storage medium. The scheme provided by the invention reduces the dependence on hardware design and upper-layer MCU design, reduces IO application, and increases design flexibility and universality.
Description
Technical Field
The invention relates to the field of firmware upgrading, in particular to a firmware upgrading method, system, equipment and storage medium of a CPLD.
Background
The CPLD is a semi-customized special integrated circuit, has the series advantages of flexible programming, quick response, high integration level and the like, and is more and more widely applied to the field of development, verification and control application in the prior art. In the switch system, the CPLD chip is used for controlling the power-on and power-off sequence control, communication control, key detection, fan rotating speed control, SFP lighting control, serial port switching and the like of the whole switch, and the MCU is used for indicating the state, state detection, firmware upgrading, remote control, voltage control, log collection and the like of the switch.
The CPLD firmware upgrading is the important content of CPLD design, and means that the image is upgraded into an internal Flash or SRAM, wherein the Flash is used as a storage area and has the characteristic of not losing in power failure; the SRAM is used as a working area, is a logic design actual working area and has the characteristic of power failure loss. The CPLD upgrading step is to upgrade the mirror image to Flash, the normal work of the CPLD cannot be influenced in the process, and then whether the refreshing action of the CPLD is executed or not is determined according to actual requirements, namely the mirror image is loaded to SRAM from Flash, and CPLD IO is out of control at the moment, so that the normal work is influenced. The firmware upgrading mode is usually based on an IIC hard core or JTAG (joint test action group) provided by a chip, the IIC hard core is upgraded by IIC communication, the communication between an MCU (microprogrammed control unit) and an IIC special for a CPLD (complex programmable logic device) needs to be realized on hardware, and meanwhile, the MCU needs to realize the IIC upgrading time sequence required by the CPLD; on one hand, the upgrading of the CPLD realized through the JTAG realizes the communication between the MCU IO and the special JTAG of the CPLD, and simultaneously requires the MCU to realize the JTAG time sequence simulation. The two designs are based on hardware design and depend on the upper-layer MCU timing design.
Disclosure of Invention
In view of the above, in order to overcome at least one aspect of the above problems, an embodiment of the present invention provides a firmware upgrade method for a CPLD, including the following steps:
the processor sends an upgrading instruction to the CPLD so that the CPLD erases the corresponding firmware storage area according to the upgrading instruction;
updating the value of a first register to a first preset value in response to the CPLD finishing erasing the firmware storage area;
in response to the processor detecting that the value of the first register is updated to a first preset value, writing firmware upgrading data into the second register, and after the current firmware upgrading data is written, updating the value of the third register to a second preset value;
and reading firmware upgrading data in the second register and writing the firmware upgrading data into the firmware storage area in response to the CPLD detecting that the value of the third register is updated to a second preset value.
In some embodiments, further comprising:
the processor updates the value of the first register from a first preset value to a third preset value;
responding to the CPLD to write all the firmware upgrading data in the second register into the firmware storage area, and judging whether the value of a fourth register is a fourth preset value;
and responding to the value of the fourth register as a fourth preset value, and verifying the data in the firmware storage area.
In some embodiments, further comprising:
updating the value of the first register from a third preset value to a fifth preset value;
in response to successful verification, updating the value of the first register from a fifth preset value to a sixth preset value;
and in response to the verification failure, updating the value of the first register from a fifth preset value to a seventh preset value.
In some embodiments, further comprising:
and feeding back the success of firmware upgrade of the CPLD to the upper layer in response to the processor detecting that the value of the first register is updated to a sixth preset value.
In some embodiments, further comprising:
and feeding back a check failure to an upper layer in response to the processor detecting that the value of the first register is updated to a seventh preset value.
In some embodiments, further comprising:
and in response to the fact that the value of the fourth register is not the fourth preset value, the CPLD updates the value of the first register from the third preset value to the first preset value, so that when the processor detects that the value of the first register is the first preset value again, data are continuously written into the second register.
In some embodiments, reading the firmware upgrade data in the second register and writing to the firmware storage area further comprises:
and writing the firmware upgrading data into the firmware storage area by using a wishbone bus.
Based on the same inventive concept, according to another aspect of the present invention, an embodiment of the present invention further provides a firmware upgrade system for a CPLD, including:
the processor module is configured to enable the processor to send an upgrading instruction to the CPLD so that the CPLD can erase the corresponding firmware storage area according to the upgrading instruction;
the updating module is configured to respond to the completion of erasing the firmware storage area by the CPLD and update the value of the first register to a first preset value;
the writing module is configured to respond to the processor detecting that the value of the first register is updated to a first preset value, write firmware upgrading data into the second register, and update the value of the third register to a second preset value after the current firmware upgrading data is written;
and the reading module is configured to respond to the CPLD detecting that the value of the third register is updated to a second preset value, read the firmware upgrading data in the second register and write the firmware upgrading data into the firmware storage area.
Based on the same inventive concept, according to another aspect of the present invention, an embodiment of the present invention further provides a computer apparatus, including:
at least one processor; and
a memory storing a computer program operable on the processor, wherein the processor executes the program to perform the steps of any of the methods of firmware upgrade of CPLDs described above.
Based on the same inventive concept, according to another aspect of the present invention, an embodiment of the present invention further provides a computer-readable storage medium storing a computer program which, when executed by a processor, performs the steps of the firmware upgrade method of any one of the CPLDs described above.
The invention has one of the following beneficial technical effects: according to the scheme provided by the invention, the firmware upgrading data is written into the register through the access of the processor to the custom register in the CPLD, then the CPLD realizes the driving logic, and the data in the register is written into the Flash, so that the MCU indirectly accesses the Flash, and further the MCU realizes the burning upgrading of the CPLD. Therefore, the dependence on hardware design and upper-layer MCU design is reduced, IO application is reduced, and design flexibility and universality are improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other embodiments can be obtained by using the drawings without creative efforts.
Fig. 1 is a schematic flowchart of a firmware upgrading method for a CPLD according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a firmware upgrade system of a CPLD according to an embodiment of the present invention;
FIG. 3 is a schematic structural diagram of a computer device provided in an embodiment of the present invention;
fig. 4 is a schematic structural diagram of a computer-readable storage medium according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the following embodiments of the present invention are described in further detail with reference to the accompanying drawings.
It should be noted that all expressions using "first" and "second" in the embodiments of the present invention are used for distinguishing two entities with the same name but different names or different parameters, and it should be noted that "first" and "second" are merely for convenience of description and should not be construed as limitations of the embodiments of the present invention, and they are not described in any more detail in the following embodiments.
According to an aspect of the present invention, an embodiment of the present invention provides a firmware upgrade method for a CPLD, as shown in fig. 1, which may include the steps of:
s1, the processor sends an upgrade instruction to the CPLD to enable the CPLD to erase the corresponding firmware storage area according to the upgrade instruction;
s2, responding to the completion of erasing the firmware storage area by the CPLD, and updating the value of the first register to a first preset value;
s3, responding to the processor detecting that the value of the first register is updated to a first preset value, writing firmware upgrading data into the second register, and updating the value of the third register to a second preset value after the current firmware upgrading data is written;
s4, responding to the CPLD detecting that the value of the third register is updated to a second preset value, reading the firmware upgrade data in the second register and writing the firmware upgrade data into the firmware storage area.
According to the scheme provided by the invention, the firmware upgrading data is written into the register through the access of the processor to the custom register in the CPLD, then the CPLD realizes the driving logic, and the data in the register is written into the Flash, so that the MCU indirectly accesses the Flash, and further the MCU realizes the burning upgrading of the CPLD. Therefore, the dependence on hardware design and upper-layer MCU design is reduced, IO application is reduced, and design flexibility and universality are improved.
In some embodiments, in step S1, the processor sends an upgrade instruction to the CPLD to enable the CPLD to erase the corresponding firmware storage area according to the upgrade instruction, and in particular, the specific erasing area may be different due to different executed commands issued by the processor, resulting in different erasing areas.
In some embodiments, a Flash command module may be provided in the CPLD, and the module may implement operations including: the method comprises the following steps of Wishbone bus enabling, Flash operation area erasing, Flash operation area burning, burning data verification and firmware refreshing, wherein the firmware refreshing can be related to user logic, namely whether a refreshing instruction is executed or not according to user requirements. The specific erasing area is different due to different executed commands, namely different operations are executed on Flash due to different commands executed on Flash.
In some embodiments, in step S2, in response to the CPLD completing erasing the firmware storage area, the value of the first register is updated to a first preset value, and specifically, the first register may be an upgrade status indication register, which may be used to indicate that the CPLD is ready to receive data, that is, the processor (MCU) may write the firmware upgrade data into the CPLD only when the value of the first register is the first preset value.
In some embodiments, in step S3, in response to the processor detecting that the value of the first register is updated to the first preset value, the processor writes the firmware upgrade data into the second register, and updates the value of the third register to the second preset value after the current firmware upgrade data is completely written, specifically, when the processor detects that the value of the first register is the first preset value, the processor writes the data into the second register in the CPLD, and when the MCU writes the data into the second register, a single-byte writing mode may be used. And because the capacity of the register is limited, the processor may need to write data into the second register in multiple rounds, but each round needs to update the value of the first register to the first preset value by the CPLD, that is, after the CPLD is ready to receive data, data writing in the next round is performed. The third register may be an upgrade data enable control register, which is used to indicate whether the current firmware upgrade data is completely written, and if the current firmware upgrade data is completely written, the value is updated to the second preset value, so as to tell the CPLD that the data can be fetched from the second register.
In some embodiments, in step S4, in response to the CPLD detecting that the value of the third register is updated to the second preset value, the firmware upgrade data in the second register is read and written into the firmware storage area, specifically, after the CPLD detecting that the value of the third register is updated to the second preset value, it indicates that the data in the second register needs to be written into the firmware storage area (i.e., Flash), and at this time, the CPLD updates the value of the third register from the second preset value to the default value.
In some embodiments, reading the firmware upgrade data in the second register and writing to the firmware storage area further comprises:
and writing the firmware upgrading data into the firmware storage area by using a wishbone bus.
Specifically, in the CPLD, the LocalBus interface module may implement access of the CPLD to the image configuration area (i.e., Flash) through the LocalBus interface module, and the LocalBus interface module may be a Wishbone interface module, that is, the CPLD implements sending of a related instruction to the Flash command module through the Wishbone interface module, and further implements corresponding operation of the Flash command module, thereby implementing access to the Flash area of the CPLD itself. The Wishbone design conforms to the Wishbone design specification, and the user logic interfaces include wb _ clk, wb _ rst, wb _ cyc, wb _ stb, wb _ cyc, wb _ ack, wb _ addr, wb _ datain and wb _ dataout, each meaning Wishbone clock signal, reset signal, transfer indication, core selection, response, address, input data and output data.
In some embodiments, further comprising:
the processor updates the value of the first register from a first preset value to a third preset value;
responding to the CPLD to write all the firmware upgrading data in the second register into the firmware storage area, and judging whether the value of a fourth register is a fourth preset value;
and responding to the value of the fourth register as a fourth preset value, and verifying the data in the firmware storage area.
Specifically, when the processor detects that the value of the first register is updated to the first preset value, the processor starts to write the firmware upgrade data into the second register, and at this time, the processor may update the value of the first register from the first preset value to the third preset value. And the fourth register may be an upgrade enable controller, which may be configured to indicate whether the firmware upgrade data is completely written, and when the processor has completely written the firmware upgrade data, the processing agent may update a value of the fourth register and a fourth preset value, at which time the CPLD may perform a verification process on the data in the firmware storage area.
In some embodiments, further comprising:
updating the value of the first register from a third preset value to a fifth preset value;
in response to successful verification, updating the value of the first register from a fifth preset value to a sixth preset value;
and in response to the verification failure, updating the value of the first register from a fifth preset value to a seventh preset value.
In some embodiments, further comprising:
and feeding back the success of firmware upgrade of the CPLD to the upper layer in response to the processor detecting that the value of the first register is updated to a sixth preset value.
In some embodiments, further comprising:
and feeding back a check failure to an upper layer in response to the processor detecting that the value of the first register is updated to a seventh preset value.
Specifically, in the verification process, the CPLD may modify the value of the first register from the third preset value to a fifth preset value, which indicates that the verification process is in progress at this time, and if the verification is successful, the value of the first register is updated from the fifth preset value to a sixth preset value, and the corresponding processor detects that the value of the first register is updated to the sixth preset value, and feeds back the firmware of the CPLD to the upper layer to be updated successfully; if the verification fails, updating the value of the first register from a fifth preset value to a seventh preset value, and correspondingly, feeding back the verification failure to an upper layer when the processor detects that the value of the first register is the seventh preset value.
In some embodiments, further comprising:
and in response to the fact that the value of the fourth register is not the fourth preset value, the CPLD updates the value of the first register from the third preset value to the first preset value, so that when the processor detects that the value of the first register is the first preset value again, data are continuously written into the second register.
Specifically, if the value of the fourth register is not the fourth preset value, it indicates that the MCU has not completely written the firmware upgrade data of the CPLD, at this time, if the CPLD has already written the data in the second register into the flash, the value of the first register may be updated from the third preset value to the first preset value again, which indicates that the CPLD is ready to receive data, then the MCU writes the data into the second register again, and after the data is completely written in this round (for example, the second register is fully written), the third register is updated from the default value to the second preset value again, so as to tell the CPLD that the CPLD can read the data, the reading process is the same as the process described in the above embodiment, and details are not repeated here.
The scheme provided by the invention realizes the online upgrading function of the CPLD mirror image configuration area through the read-write operation of the MCU to the general register, the access of the MCU to the CPLD general register is the basic function of each CPLD, the common access interfaces comprise IIC, LPC and the like, and the PCIe access can be realized for high-speed PLD equipment. The CPLD LocalBus interface and the Flash command interface module are realized through the CPLD, the MCU only needs to read and write access to the CPLD general register when operating the CPLD mirror image configuration area, and the communication between the general register and the CPLD LocalBus interface is realized through the CPLD user logic adhesion.
According to the scheme provided by the invention, the firmware upgrading data is written into the register through the access of the processor to the custom register in the CPLD, then the CPLD realizes the driving logic, and the data in the register is written into the Flash, so that the MCU indirectly accesses the Flash, and further the MCU realizes the burning upgrading of the CPLD. Therefore, the dependence on hardware design and upper-layer MCU design is reduced, IO application is reduced, and design flexibility and universality are improved.
Based on the same inventive concept, according to another aspect of the present invention, an embodiment of the present invention further provides a firmware upgrade system 400 of a CPLD, as shown in fig. 2, including:
the processor module 401 is configured to enable the processor to send an upgrade instruction to the CPLD so that the CPLD erases the corresponding firmware storage area according to the upgrade instruction;
an updating module 402 configured to update the value of the first register to a first preset value in response to the CPLD completing erasing the firmware storage area;
a writing module 403, configured to, in response to the processor detecting that the value of the first register is updated to the first preset value, write firmware upgrade data into the second register, and update the value of the third register to the second preset value after the current firmware upgrade data is completely written;
a reading module 404, configured to, in response to the CPLD detecting that the value of the third register is updated to the second preset value, read the firmware upgrade data in the second register and write the firmware upgrade data into the firmware storage area.
In some embodiments, further comprising:
the processor updates the value of the first register from a first preset value to a third preset value;
responding to the CPLD to write all the firmware upgrading data in the second register into the firmware storage area, and judging whether the value of a fourth register is a fourth preset value;
and responding to the value of the fourth register as a fourth preset value, and verifying the data in the firmware storage area.
In some embodiments, further comprising:
updating the value of the first register from a third preset value to a fifth preset value;
in response to successful verification, updating the value of the first register from a fifth preset value to a sixth preset value;
and in response to the verification failure, updating the value of the first register from a fifth preset value to a seventh preset value.
In some embodiments, further comprising:
and feeding back the success of firmware upgrade of the CPLD to the upper layer in response to the processor detecting that the value of the first register is updated to a sixth preset value.
In some embodiments, further comprising:
and feeding back a check failure to an upper layer in response to the processor detecting that the value of the first register is updated to a seventh preset value.
In some embodiments, further comprising:
and in response to the fact that the value of the fourth register is not the fourth preset value, the CPLD updates the value of the first register from the third preset value to the first preset value, so that when the processor detects that the value of the first register is the first preset value again, data are continuously written into the second register.
In some embodiments, reading the firmware upgrade data in the second register and writing to the firmware storage area further comprises:
and writing the firmware upgrading data into the firmware storage area by using a wishbone bus.
According to the scheme provided by the invention, the firmware upgrading data is written into the register through the access of the processor to the custom register in the CPLD, then the CPLD realizes the driving logic, and the data in the register is written into the Flash, so that the MCU indirectly accesses the Flash, and further the MCU realizes the burning upgrading of the CPLD. Therefore, the dependence on hardware design and upper-layer MCU design is reduced, IO application is reduced, and design flexibility and universality are improved.
Based on the same inventive concept, according to another aspect of the present invention, as shown in fig. 3, an embodiment of the present invention further provides a computer apparatus 501, comprising:
at least one processor 520; and
a memory 510, the memory 510 storing a computer program 511 executable on the processor, the processor 520 executing the program to perform the steps of:
s1, the processor sends an upgrade instruction to the CPLD to enable the CPLD to erase the corresponding firmware storage area according to the upgrade instruction;
s2, responding to the completion of erasing the firmware storage area by the CPLD, and updating the value of the first register to a first preset value;
s3, responding to the processor detecting that the value of the first register is updated to a first preset value, writing firmware upgrading data into the second register, and updating the value of the third register to a second preset value after the current firmware upgrading data is written;
s4, responding to the CPLD detecting that the value of the third register is updated to a second preset value, reading the firmware upgrade data in the second register and writing the firmware upgrade data into the firmware storage area.
In some embodiments, further comprising:
the processor updates the value of the first register from a first preset value to a third preset value;
responding to the CPLD to write all the firmware upgrading data in the second register into the firmware storage area, and judging whether the value of a fourth register is a fourth preset value;
and responding to the value of the fourth register as a fourth preset value, and verifying the data in the firmware storage area.
In some embodiments, further comprising:
updating the value of the first register from a third preset value to a fifth preset value;
in response to successful verification, updating the value of the first register from a fifth preset value to a sixth preset value;
and in response to the verification failure, updating the value of the first register from a fifth preset value to a seventh preset value.
In some embodiments, further comprising:
and feeding back the success of firmware upgrade of the CPLD to the upper layer in response to the processor detecting that the value of the first register is updated to a sixth preset value.
In some embodiments, further comprising:
and feeding back a check failure to an upper layer in response to the processor detecting that the value of the first register is updated to a seventh preset value.
In some embodiments, further comprising:
and in response to the fact that the value of the fourth register is not the fourth preset value, the CPLD updates the value of the first register from the third preset value to the first preset value, so that when the processor detects that the value of the first register is the first preset value again, data are continuously written into the second register.
In some embodiments, reading the firmware upgrade data in the second register and writing to the firmware storage area further comprises:
and writing the firmware upgrading data into the firmware storage area by using a wishbone bus.
According to the scheme provided by the invention, the firmware upgrading data is written into the register through the access of the processor to the custom register in the CPLD, then the CPLD realizes the driving logic, and the data in the register is written into the Flash, so that the MCU indirectly accesses the Flash, and further the MCU realizes the burning upgrading of the CPLD. Therefore, the dependence on hardware design and upper-layer MCU design is reduced, IO application is reduced, and design flexibility and universality are improved.
Based on the same inventive concept, according to another aspect of the present invention, as shown in fig. 4, an embodiment of the present invention further provides a computer-readable storage medium 601, where the computer-readable storage medium 601 stores computer program instructions 610, and the computer program instructions 610, when executed by a processor, perform the following steps:
s1, the processor sends an upgrade instruction to the CPLD to enable the CPLD to erase the corresponding firmware storage area according to the upgrade instruction;
s2, responding to the completion of erasing the firmware storage area by the CPLD, and updating the value of the first register to a first preset value;
s3, responding to the processor detecting that the value of the first register is updated to a first preset value, writing firmware upgrading data into the second register, and updating the value of the third register to a second preset value after the current firmware upgrading data is written;
s4, responding to the CPLD detecting that the value of the third register is updated to a second preset value, reading the firmware upgrade data in the second register and writing the firmware upgrade data into the firmware storage area.
In some embodiments, further comprising:
the processor updates the value of the first register from a first preset value to a third preset value;
responding to the CPLD to write all the firmware upgrading data in the second register into the firmware storage area, and judging whether the value of a fourth register is a fourth preset value;
and responding to the value of the fourth register as a fourth preset value, and verifying the data in the firmware storage area.
In some embodiments, further comprising:
updating the value of the first register from a third preset value to a fifth preset value;
in response to successful verification, updating the value of the first register from a fifth preset value to a sixth preset value;
and in response to the verification failure, updating the value of the first register from a fifth preset value to a seventh preset value.
In some embodiments, further comprising:
and feeding back the success of firmware upgrade of the CPLD to the upper layer in response to the processor detecting that the value of the first register is updated to a sixth preset value.
In some embodiments, further comprising:
and feeding back a check failure to an upper layer in response to the processor detecting that the value of the first register is updated to a seventh preset value.
In some embodiments, further comprising:
and in response to the fact that the value of the fourth register is not the fourth preset value, the CPLD updates the value of the first register from the third preset value to the first preset value, so that when the processor detects that the value of the first register is the first preset value again, data are continuously written into the second register.
In some embodiments, reading the firmware upgrade data in the second register and writing to the firmware storage area further comprises:
and writing the firmware upgrading data into the firmware storage area by using a wishbone bus.
According to the scheme provided by the invention, the firmware upgrading data is written into the register through the access of the processor to the custom register in the CPLD, then the CPLD realizes the driving logic, and the data in the register is written into the Flash, so that the MCU indirectly accesses the Flash, and further the MCU realizes the burning upgrading of the CPLD. Therefore, the dependence on hardware design and upper-layer MCU design is reduced, IO application is reduced, and design flexibility and universality are improved.
Finally, it should be noted that, as will be understood by those skilled in the art, all or part of the processes of the methods of the above embodiments may be implemented by a computer program, which may be stored in a computer-readable storage medium, and when executed, may include the processes of the embodiments of the methods described above.
Further, it should be appreciated that the computer-readable storage media (e.g., memory) herein can be either volatile memory or nonvolatile memory, or can include both volatile and nonvolatile memory.
Those of skill would further appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the disclosure herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as software or hardware depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the disclosed embodiments of the present invention.
The foregoing is an exemplary embodiment of the present disclosure, but it should be noted that various changes and modifications could be made herein without departing from the scope of the present disclosure as defined by the appended claims. The functions, steps and/or actions of the method claims in accordance with the disclosed embodiments described herein need not be performed in any particular order. Furthermore, although elements of the disclosed embodiments of the invention may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated.
It should be understood that, as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly supports the exception. It should also be understood that "and/or" as used herein is meant to include any and all possible combinations of one or more of the associated listed items.
The numbers of the embodiments disclosed in the embodiments of the present invention are merely for description, and do not represent the merits of the embodiments.
It will be understood by those skilled in the art that all or part of the steps of implementing the above embodiments may be implemented by hardware, or may be implemented by a program instructing relevant hardware, and the program may be stored in a computer-readable storage medium, and the above-mentioned storage medium may be a read-only memory, a magnetic disk or an optical disk, etc.
Those of ordinary skill in the art will understand that: the discussion of any embodiment above is meant to be exemplary only, and is not intended to intimate that the scope of the disclosure, including the claims, of embodiments of the invention is limited to these examples; within the idea of an embodiment of the invention, also technical features in the above embodiment or in different embodiments may be combined and there are many other variations of the different aspects of the embodiments of the invention as described above, which are not provided in detail for the sake of brevity. Therefore, any omissions, modifications, substitutions, improvements, and the like that may be made without departing from the spirit and principles of the embodiments of the present invention are intended to be included within the scope of the embodiments of the present invention.
Claims (10)
1. A firmware upgrading method for a CPLD is characterized by comprising the following steps:
the processor sends an upgrading instruction to the CPLD so that the CPLD erases the corresponding firmware storage area according to the upgrading instruction;
updating the value of a first register to a first preset value in response to the CPLD finishing erasing the firmware storage area;
in response to the processor detecting that the value of the first register is updated to a first preset value, writing firmware upgrading data into the second register, and after the current firmware upgrading data is written, updating the value of the third register to a second preset value;
and reading firmware upgrading data in the second register and writing the firmware upgrading data into the firmware storage area in response to the CPLD detecting that the value of the third register is updated to a second preset value.
2. The method of claim 1, further comprising:
the processor updates the value of the first register from a first preset value to a third preset value;
responding to the CPLD to write all the firmware upgrading data in the second register into the firmware storage area, and judging whether the value of a fourth register is a fourth preset value;
and responding to the value of the fourth register as a fourth preset value, and verifying the data in the firmware storage area.
3. The method of claim 2, further comprising:
updating the value of the first register from a third preset value to a fifth preset value;
in response to successful verification, updating the value of the first register from a fifth preset value to a sixth preset value;
and in response to the verification failure, updating the value of the first register from a fifth preset value to a seventh preset value.
4. The method of claim 3, further comprising:
and feeding back the success of firmware upgrade of the CPLD to the upper layer in response to the processor detecting that the value of the first register is updated to a sixth preset value.
5. The method of claim 3, further comprising:
and feeding back a check failure to an upper layer in response to the processor detecting that the value of the first register is updated to a seventh preset value.
6. The method of claim 2, further comprising:
and in response to the fact that the value of the fourth register is not the fourth preset value, the CPLD updates the value of the first register from the third preset value to the first preset value, so that when the processor detects that the value of the first register is the first preset value again, data are continuously written into the second register.
7. The method of claim 1, wherein reading the firmware upgrade data in the second register and writing to the firmware storage area, further comprises:
and writing the firmware upgrading data into the firmware storage area by using a wishbone bus.
8. A firmware upgrade system for a CPLD, comprising:
the processor module is configured to enable the processor to send an upgrading instruction to the CPLD so that the CPLD can erase the corresponding firmware storage area according to the upgrading instruction;
the updating module is configured to respond to the completion of erasing the firmware storage area by the CPLD and update the value of the first register to a first preset value;
the writing module is configured to respond to the processor detecting that the value of the first register is updated to a first preset value, write firmware upgrading data into the second register, and update the value of the third register to a second preset value after the current firmware upgrading data is written;
and the reading module is configured to respond to the CPLD detecting that the value of the third register is updated to a second preset value, read the firmware upgrading data in the second register and write the firmware upgrading data into the firmware storage area.
9. A computer device, comprising:
at least one processor; and
memory storing a computer program operable on the processor, wherein the processor executes the program to perform the steps of the method according to any of claims 1-7.
10. A computer-readable storage medium, in which a computer program is stored which, when being executed by a processor, is adapted to carry out the steps of the method according to any one of claims 1 to 7.
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| US20150339118A1 (en) * | 2014-05-20 | 2015-11-26 | Huawei Technologies Co., Ltd. | Upgrade Processing Method, Apparatus and System for CPLD |
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| CN111142896A (en) * | 2019-12-09 | 2020-05-12 | 苏州浪潮智能科技有限公司 | Method and device for upgrading firmware of storage device and readable medium |
| CN112199231A (en) * | 2020-10-21 | 2021-01-08 | 苏州浪潮智能科技有限公司 | CPLD fault detection and repair method and device |
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| US20150339118A1 (en) * | 2014-05-20 | 2015-11-26 | Huawei Technologies Co., Ltd. | Upgrade Processing Method, Apparatus and System for CPLD |
| CN111090545A (en) * | 2019-11-28 | 2020-05-01 | 苏州浪潮智能科技有限公司 | Method, device and medium for recovering failed CPLD |
| CN111142896A (en) * | 2019-12-09 | 2020-05-12 | 苏州浪潮智能科技有限公司 | Method and device for upgrading firmware of storage device and readable medium |
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