CN112947971A - FPGA remote updating device and method - Google Patents
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Abstract
The invention discloses a device and a method for remotely updating an FPGA (field programmable gate array), wherein the device comprises an FPGA module, and a communication controller, a remote system updating controller, a dual-configuration controller and an NVM (non-volatile memory) controller are arranged in the FPGA module; the remote system updating controller is respectively in communication connection with the communication controller, the dual-configuration controller and the NVM controller; the dual-configuration controller and the NVM controller are connected with a user NVM, a first configuration NVM and a second configuration NVM, the user NVM is used for storing user data, and the first configuration NVM and the second configuration NVM are respectively used for storing first firmware image data and second firmware image data; the FPGA module is in communication connection with the communication controller, the communication controller is in communication connection with the interface circuit, and the communication controller is in communication connection with the upper computer through the interface circuit. The invention adopts a double-configuration remote updating mode, is safer and more reliable, and can still ensure the normal starting of the system even if an accident occurs in the field updating process.
Description
Technical Field
The invention relates to the technical field of data processing, in particular to a device and a method for remotely updating an FPGA (field programmable gate array).
Background
In recent years, with the increasing popularity of technologies such as big data, artificial intelligence, 5G, internet of things and the like, FPGAs are applied more and more widely. Reprogrammability is an essential characteristic of FPGAs. Generally, an SRAM unit is used by an FPGA to store configuration data, and the configuration data disappears after power failure, so that the configuration data needs to be stored in an external nonvolatile memory and loaded into the SRAM unit after each power-on. The commonly used configuration schemes are: an active configuration scheme, a passive configuration scheme, a JTAG configuration scheme, and the like. The JTAG configuration scheme is local and is suitable for development and factory loading. The "field programmable" feature of the configuration scheme is exploited to its fullest extent when it supports remote system updates.
CN201710034806.6 discloses an FPGA remote updating apparatus supporting updating a single image, as shown in fig. 1, an FPGA module includes an embedded processor remote updating system, and the remote updating system includes a communication module and a remote updating module. The communication module receives commands and program data of the upper computer and sends the commands and the program data to the remote updating module, the remote updating system of the embedded processor analyzes the received commands, converts the program data into data streams and clock streams suitable for configuring FLASH, and reads, writes and erases the configured FLASH data.
CN201811245075.0 discloses a program remote updating system and method based on DSP + FPGA architecture, as shown in fig. 2, including: DSP, application FPGA, management FPGA and external FLASH. The management FPGA is used for configuring an application FPGA on line and programming an external FLASH of the application FPGA; and the DSP receives the update data of the application FPGA and updates the application FPGA by managing the FPGA.
CN201310530155.1 discloses a method and an apparatus for implementing FPGA remote update by using a CPU to control a multi-channel analog switch, as shown in fig. 3, the CPU controls the multi-channel analog switch to control the connection of the main control object of the memory, so as to implement the function of updating the memory data by the CPU.
The three existing methods all use a single configuration mode, only one configuration data storage area is provided, and if an accident occurs in the configuration process, the original configuration data is damaged, and the system cannot be started normally.
Besides, in the prior art, the CN201811245075.0 needs to use a DSP, an application FPGA and a management FPGA, and the CN201310530155.1 needs to use a CPU and a multi-way analog switch for control, so that the structure is complex and the cost is high.
Disclosure of Invention
Aiming at the defects of the prior art, the invention aims to provide a device and a method for remotely updating an FPGA.
In order to achieve the purpose, the invention adopts the following technical scheme:
an FPGA remote updating device comprises an FPGA module, wherein a communication controller, a remote system updating controller, a dual-configuration controller and an NVM controller are arranged in the FPGA module; the remote system updating controller is respectively in communication connection with the communication controller, the dual-configuration controller and the NVM controller; the dual-configuration controller and the NVM controller are connected with a user NVM, a first configuration NVM and a second configuration NVM, the user NVM is used for storing user data, and the first configuration NVM and the second configuration NVM are respectively used for storing first firmware image data and second firmware image data; the FPGA module is in communication connection with the communication controller, the communication controller is in communication connection with the interface circuit, and the communication controller is in communication connection with the upper computer through the interface circuit;
the remote system updating controller is used for realizing power-on loading flow control and remote updating flow control in remote updating and is provided with a keyword Image _ load; the dual-configuration controller is used for completing a power-on loading process in remote updating under the control of the remote system updating controller; the NVM controller is used for completing a remote updating process in remote updating under the control of the remote system updating controller and is responsible for controlling, reading and writing access to the user NVM, the first configuration NVM and the second configuration NVM; the user NVM is provided with a keyword Image _ set.
Further, the interface circuit is any one of an ethernet interface, a serial interface, a USB interface, and a PCIe interface.
The invention also provides a method for remotely updating the device by utilizing the FPGA, which comprises the following specific processes:
s1, power-on loading:
s101, after being electrified, the FPGA module samples CONFIG _ SEL pin level or reads a configuration initial address to determine firmware mapping data;
s102, loading corresponding firmware mapping data by the FPGA module: the remote system updating controller determines the value of Image _ load by inquiring the dual-configuration controller;
s103, reading the Image _ set in the user NVM by the remote system updating controller through the NVM controller;
s104, the remote system updating controller compares whether the Image _ load is equal to the Image _ set or not; if the Image _ load is equal to the Image _ set, ending the electrifying and loading process; if the Image _ load is not equal to the Image _ set, the remote system updating controller sets a CONFIG _ SEL register bit value or a configuration starting address as the value of the Image _ set saved by the user NVM through the dual-configuration controller, triggers reconfiguration and shifts to S102;
s2, remote updating:
s201, the upper computer sends a remote updating request to the FPGA module;
s202, after the remote system updating controller receives the remote updating request through the communication controller, determining whether the first configuration NVM or the second configuration NVM needs to be erased according to the current Image _ load, and completing erasing through the NVM controller;
s203, the remote system updating controller requests a frame of firmware mapping data, and then the first configuration NVM or the second configuration NVM which finishes erasing is written into the data word by word through the NVM controller;
s204, after the frame of firmware image data is written, the remote system updating controller sends a code back to the upper computer;
s205, if the firmware mapping data is not written completely, returning to the step S203 to request the firmware mapping data of the next frame and writing the firmware mapping data through the NVM controller, and jumping to the step S206 after all the firmware mapping data are written completely;
s206, the upper computer sends a read-back command to the remote system updating controller, after receiving the command, the remote system updating controller controls the NVM controller to read back a frame of firmware mapping data, and the reading back is carried out in frames until all the frames are read back;
s207, the upper computer compares whether all written data and read data are equal or not; if not, returning to the step S201 to restart, otherwise, jumping to the step S208;
s208, the upper computer sends a successful updating notification to the remote system updating controller, and the remote system updating controller modifies the Image _ set through the NVM controller and writes the modified Image _ set into the user NVM;
and S209, triggering reconfiguration by the remote system updating controller through the setting register of the double configuration controller.
The invention has the beneficial effects that:
1. the invention adopts a double-configuration remote updating mode, is safer and more reliable, and can still ensure the normal starting of the system even if an accident occurs in the field updating process.
2. The version rollback function can be realized by modifying the value of the keyword Image _ set to switch between the new firmware version and the old firmware version.
3. According to the invention, after field updating is finished, human intervention is not needed, pin setting is not needed, and firmware can be automatically loaded to the latest version.
4. When the invention is used for remote updating, the upper computer software does not need to know the details of bottom hardware, and the firmware can automatically select the sector needing to be updated.
5. The invention is realized by pure hardware logic, does not need a hard core or a soft core processor, has small resource consumption, is easy to be divided from the application function and is easy to be transplanted.
Drawings
FIG. 1 is a schematic diagram of a first prior art system architecture;
FIG. 2 is a schematic diagram of a second prior art system configuration;
FIG. 3 is a schematic diagram of a third prior art system configuration;
FIG. 4 is a schematic structural view of an apparatus according to embodiment 1 of the present invention;
fig. 5 is a schematic diagram of a power-on loading flow in embodiment 2 of the present invention;
FIG. 6 is a schematic diagram of a remote update process according to embodiment 2 of the present invention;
FIG. 7 is a schematic structural view of an apparatus according to embodiment 3 of the present invention;
fig. 8 is a schematic structural diagram of an apparatus according to embodiment 4 of the present invention.
Detailed Description
The present invention will be further described with reference to the accompanying drawings, and it should be noted that the present embodiment is based on the technical solution, and the detailed implementation and the specific operation process are provided, but the protection scope of the present invention is not limited to the present embodiment.
Example 1
The present embodiment provides an FPGA remote updating apparatus, as shown in fig. 4, including an FPGA module 1, where the FPGA module 1 is internally provided with a communication controller 101, a remote system updating controller 102, a dual configuration controller 103, and an NVM controller 104; the remote system update controller 102 is respectively connected to the communication controller 101, the dual configuration controller 103 and the NVM controller 104 in a communication manner; the dual-configuration controller 103 and the NVM controller 104 are connected to a user NVM401, a first configuration NVM402 and a second configuration NVM 403.
The FPGA module 1 is in communication connection with the upper computer 3 through the communication controller 101. The FPGA module 1 realizes command and data communication with the upper computer 3 through the communication controller 101.
More specifically, the communication controller 101 is communicatively connected to the interface circuit 2, and the communication controller 101 is communicatively connected to the upper computer 3 through the interface circuit 2. The interface circuit 2 may be any one of ethernet, serial, USB, PCIe, and other interfaces.
It should be noted that the remote system update controller 102 is configured to implement power-on loading flow control and remote update flow control in remote update, and is provided with a keyword Image _ load. The dual configuration controller 103 is used to assist the remote system update controller 102 in completing the power-on loading process in the remote update. The NVM controller 104 is used to assist the remote system update controller 102 in completing a remote update procedure in a remote update, and is responsible for controlling, reading, and writing access to the user NVM401, the first configuration NVM402, and the second configuration NVM 403.
The user NVM401 is used for storing user data, and may be disposed inside or outside the FPGA module 1. The user NVM401 is provided with a keyword Image _ set. The first configuration NVM402 and the second configuration NVM403 are used for storing first firmware image data and second firmware image data, respectively, and may be disposed inside or outside the FPGA module 1.
Example 2
The embodiment provides a method for remotely updating a device by using an FPGA described in embodiment 1, as shown in fig. 5, the specific process is as follows:
s1, power-on loading:
s101, after the power is on, the FPGA module 1 samples a CONFIG _ SEL pin level or reads a configuration initial address to determine firmware mapping data;
s102, loading corresponding firmware mapping data by the FPGA module 1: the remote system update controller 102 determines the value of Image _ load by querying the dual configuration controller 103;
s103, the remote system updating controller 102 reads Image _ set in the user NVM401 through the NVM controller 104;
s104, the remote system updating controller 102 compares whether the Image _ load is equal to the Image _ set or not; if the Image _ load is equal to the Image _ set, ending the electrifying and loading process; if Image _ load is not equal to Image _ set, the remote system update controller 102 sets a CONFIG _ SEL register bit value or configures the start address as the value of Image _ set saved by the user NVM401 through the dual-configuration controller 103, triggers reconfiguration, and goes to S102.
The power-on loading process ends.
S2, as shown in fig. 6, remote update:
s201, the upper computer 3 sends a remote updating request to the FPGA module 1;
s202, after receiving the remote updating request through the communication controller 101, the remote system updating controller 102 determines whether the first configured NVM402 or the second configured NVM403 is to be erased according to the current Image _ load, and completes the erasing through the NVM controller 104;
s203, the remote system updating controller 102 requests a frame of firmware image data, and then writes the first configuration NVM402 or the second configuration NVM403 which finishes erasing word by word through the NVM controller 104;
s204, after the frame of firmware image data is written, the remote system updating controller 102 sends a code back to the upper computer 3;
s205, if the firmware mapping data is not written completely, returning to the step S203 to request the firmware mapping data of the next frame and writing the firmware mapping data through the NVM controller 104, and jumping to the step S206 after all the firmware mapping data are written completely;
s206, the upper computer 3 sends a read-back command to the remote system update controller 102, after receiving the command, the remote system update controller 102 controls the NVM controller 104 to read back a frame of firmware image data, and the read-back is carried out in frames until all the frames are read back;
s207, the upper computer 3 compares whether all the written data and the read data are equal; if not, returning to the step S201 to restart, otherwise, jumping to the step S208;
s208, the upper computer 3 sends a successful updating notification to the remote system updating controller 102, and the remote system updating controller 102 modifies the Image _ set through the NVM controller 104 and writes the modified Image _ set into the user NVM;
s209, the remote system update controller 102 sets a register through the dual configuration controller 103 to trigger reconfiguration.
The remote update procedure ends.
Example 3
This example is an application example to examples 1 and 2.
In the FPGA remote updating apparatus of this embodiment, as shown in fig. 7, the FPGA module 1 is an Intel MAX10 series chip 10M16DAF256, the interface circuit 2 is an ethernet 10/100/1000PHY, the upper computer 3 is a desktop or notebook with an RJ45 port, the communication controller 101 adopts a UDP/IP protocol and application of a three-speed ethernet IP core and pure hardware logic, the remote system updating controller 102 is hardware logic, the dual-configuration controller 103 and the NVM controller 104 are hardware logic, and the user NVM401, the first configuration NVM402, and the second configuration NVM403 both adopt 10M16DAF256 built-in flash memories.
The specific process of the method for remotely updating the device by using the FPGA of the embodiment is as follows:
s1, power-on loading:
s101, when the system is powered on, the FPGA module 110M 16DAF256 samples a CONFIG _ SEL pin level to determine firmware mapping data;
s102, loading corresponding firmware mapping data by the FPGA module 1: the remote system update controller 102 determines the value of Image load by querying the dual configuration controller 103.
S103, after the firmware Image data is loaded successfully, the remote system update controller 102 firstly reads a loaded Image setting value Image _ set stored in the user NVM401 through the NVM controller 104;
s104, the remote system updating controller 102 compares whether the Image _ load is equal to the Image _ set or not; if the Image _ load is equal to the Image _ set, ending the electrifying and loading process; if Image _ load is not equal to Image _ set, the remote system update controller 102 sets a CONFIG _ SEL register bit value or configures the start address as the value of Image _ set saved by the user NVM401 through the dual-configuration controller 103, triggers reconfiguration, and goes to S102.
S2, remote updating:
s201, when the upper computer 3 needs to be updated remotely, a remote updating request is sent to the FPGA module 1 through the RJ45 network port;
s202, after the communication controller 101 receives the remote update request, the remote system update controller 102 determines to erase the first configuration NVM402 or the second configuration NVM403 according to the current Image _ load, and completes the erasing through the NVM controller 104, where the rule is that the oldest data is replaced, e.g. Image _ load is 0, and the rule is to erase the second configuration NVM403, e.g. Image _ load is 1, and erase the first configuration NVM 402. Here the firmware update data size per frame is 1 KB.
S203, the remote system updating controller 102 requests a frame of firmware image data, and then writes the first configuration NVM402 or the second configuration NVM403 which finishes erasing word by word through the NVM controller 104;
and S204, after the firmware image data of the frame is completely written, the remote system updating controller 102 sends a code back to the upper computer 3 to feed back whether the writing operation is successful or failed, and the upper computer 3 determines whether to retransmit the frame or send new frame data according to the feedback of the remote system updating controller 102.
S205, if the firmware image data is not written completely, returning to the step S203 to request the next frame data and writing the next frame data through the NVM controller 104 until all the firmware data are written completely, and jumping to the step 206;
s206, the upper computer 3 sends a read-back command to the remote system update controller 102, after receiving the command, the remote system update controller 102 controls the NVM controller 104 to read back a frame of firmware image data, and the read-back is carried out in frames until all the frames are read back; in this embodiment 256B is read back every frame.
S207, the upper computer 3 compares all written data with all read data, and if the written data and the read data are not all equal, the step S201 is returned to start again; if the written data and the read-back data are all equal, the verification is successful and the process jumps to step S208.
S208, the upper computer 3 sends a successful updating notification to the remote system updating controller 102, and the remote system updating controller 102 modifies the Image _ set through the NVM controller 104 and writes the modified Image _ set into the user NVM;
s209, the remote system update controller 102 sets a register through the dual configuration controller 103 to trigger reconfiguration.
The remote update procedure ends.
Example 4
This embodiment is another application example to embodiment 1 and embodiment 2.
As shown in fig. 8, the FPGA remote updating apparatus of this embodiment includes an FPGA module 1 that is an Intel Cyclone IV series chip EP4CGX15, an interface circuit 2 that is a level shifter MAX3232, an upper computer 3 that is a desktop or a notebook computer with a serial port, and a communication controller 101 that is a serial port controller and adopts hardware logic. The remote system update controller 102 is hardware logic, the dual configuration controller 103 and the NVM controller 104 are hardware logic, the user NVM401 is 24LC00, and the first configuration NVM402 and the second configuration NVM403 are two connected sectors of EPCQ 64.
The specific process of utilizing the FPGA remote updating apparatus of this embodiment is as follows:
s1, power-on loading:
s101, when the system is powered on, the FPGA module 1EP4CGX15 reads a configuration start address and determines firmware mapping data;
s102, loading corresponding firmware mapping data by the FPGA module 1: the remote system update controller 102 determines Image _ load by querying the dual configuration controller 103;
s103, after the firmware Image data is loaded successfully, the remote system update controller 102 firstly reads a loaded Image setting value Image _ set stored in the user NVM401 through the NVM controller 104;
s104, the remote system updating controller 102 compares whether the Image _ load is equal to the Image _ set or not; if the Image _ load is equal to the Image _ set, ending the electrifying and loading process; if Image _ load is not equal to Image _ set, the remote system update controller 102 sets a CONFIG _ SEL register bit value or configures the start address as the value of Image _ set saved by the user NVM401 through the dual-configuration controller 103, triggers reconfiguration, and goes to S102.
S2, remote updating:
s201, when the upper computer 3 is updated remotely, a remote updating request is sent to the FPGA module 1 through a serial port;
s202, after the serial port controller 101 receives the remote update request, the remote system update controller 102 determines whether the first configured NVM402 or the second configured NVM403 is to be erased according to the current Image _ load, and completes the erasing through the NVM controller 104, where the rule is that the oldest data is replaced, if Image _ load is equal to 0, the second configured NVM403 is erased, if Image _ load is equal to 1, the first configured NVM402 is erased. Here the firmware update data size per frame is 1 KB.
S203, the remote system updating controller 102 requests a frame of firmware image data, and then writes the first configuration NVM402 or the second configuration NVM403 which finishes erasing word by word through the NVM controller 104;
and S204, after the firmware image data of the frame is completely written, the remote system updating controller 104 sends a code back to the upper computer 3 to feed back whether the writing operation is successful or failed, and the upper computer 3 determines whether to retransmit the frame or send new frame data according to a feedback result of the remote system updating controller 104.
S205, if the firmware mapping data is not written completely, returning to the step S203 to request the firmware mapping data of the next frame and writing the firmware mapping data through the NVM controller 104 until all the firmware mapping data are written completely;
s206, the upper computer 3 sends a read-back command to the remote system update controller 102, after receiving the command, the remote system update controller 102 controls the NVM controller 104 to read back a frame of firmware image data in a frame, and the frame is read back, wherein each frame is read back for 256B until all frames are read back;
s207, the upper computer 3 compares all written data with all read data, and if the written data and the read data are not all equal, the step S201 is returned to start again; if the written data and the read-back data are all equal, the verification is successful and the process jumps to step S208.
S208, after the verification is successful, the upper computer 3 sends an update success notification to the remote system update controller 102, and the remote system update controller 102 modifies the Image _ set through the NVM controller 104 and writes the modified Image _ set into the user NVM;
s209, the remote system update controller 102 sets a register through the dual configuration controller 103 to trigger reconfiguration.
Various corresponding changes and modifications can be made by those skilled in the art based on the above technical solutions and concepts, and all such changes and modifications should be included in the protection scope of the present invention.
Claims (3)
1. An FPGA remote updating device is characterized by comprising an FPGA module, wherein a communication controller, a remote system updating controller, a dual-configuration controller and an NVM controller are arranged in the FPGA module; the remote system updating controller is respectively in communication connection with the communication controller, the dual-configuration controller and the NVM controller; the dual-configuration controller and the NVM controller are connected with a user NVM, a first configuration NVM and a second configuration NVM, the user NVM is used for storing user data, and the first configuration NVM and the second configuration NVM are respectively used for storing first firmware image data and second firmware image data; the FPGA module is in communication connection with the communication controller, the communication controller is in communication connection with the interface circuit, and the communication controller is in communication connection with the upper computer through the interface circuit;
the remote system updating controller is used for realizing power-on loading flow control and remote updating flow control in remote updating and is provided with a keyword Image _ load; the dual-configuration controller is used for completing a power-on loading process in remote updating under the control of the remote system updating controller; the NVM controller is used for completing a remote updating process in remote updating under the control of the remote system updating controller and is responsible for controlling, reading and writing access to the user NVM, the first configuration NVM and the second configuration NVM; the user NVM is provided with a keyword Image _ set.
2. The FPGA remote updating device of claim 1, wherein the interface circuit is any one of an Ethernet interface, a serial interface, a USB interface and a PCIe interface.
3. A method for remotely updating a device by using the FPGA of any one of claims 1-2, comprising the following steps:
s1, power-on loading:
s101, after being electrified, the FPGA module samples CONFIG _ SEL pin level or reads a configuration initial address to determine firmware mapping data;
s102, loading corresponding firmware mapping data by the FPGA module: the remote system updating controller determines the value of Image _ load by inquiring the dual-configuration controller;
s103, reading the Image _ set in the user NVM by the remote system updating controller through the NVM controller;
s104, the remote system updating controller compares whether the Image _ load is equal to the Image _ set or not; if the Image _ load is equal to the Image _ set, ending the electrifying and loading process; if the Image _ load is not equal to the Image _ set, the remote system updating controller sets a CONFIG _ SEL register bit value or a configuration starting address as the value of the Image _ set saved by the user NVM through the dual-configuration controller, triggers reconfiguration and shifts to S102;
s2, remote updating:
s201, the upper computer sends a remote updating request to the FPGA module;
s202, after the remote system updating controller receives the remote updating request through the communication controller, determining whether the first configuration NVM or the second configuration NVM needs to be erased according to the current Image _ load, and completing erasing through the NVM controller;
s203, the remote system updating controller requests a frame of firmware mapping data, and then the first configuration NVM or the second configuration NVM which finishes erasing is written into the data word by word through the NVM controller;
s204, after the frame of firmware image data is written, the remote system updating controller sends a code back to the upper computer;
s205, if the firmware mapping data is not written completely, returning to the step S203 to request the firmware mapping data of the next frame and writing the firmware mapping data through the NVM controller, and jumping to the step S206 after all the firmware mapping data are written completely;
s206, the upper computer sends a read-back command to the remote system updating controller, after receiving the command, the remote system updating controller controls the NVM controller to read back a frame of firmware mapping data, and the reading back is carried out in frames until all the frames are read back;
s207, the upper computer compares whether all written data and read data are equal or not; if not, returning to the step S201 to restart, otherwise, jumping to the step S208;
s208, the upper computer sends a successful updating notification to the remote system updating controller, and the remote system updating controller modifies the Image _ set through the NVM controller and writes the modified Image _ set into the user NVM;
and S209, triggering reconfiguration by the remote system updating controller through the setting register of the double configuration controller.
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| US20200133654A1 (en) * | 2018-10-25 | 2020-04-30 | Mitac Computing Technology Corporation | Method for remotely updating firmware of field programmable gate array |
| CN110837488A (en) * | 2019-07-15 | 2020-02-25 | 华为技术有限公司 | Message transmission method and device |
| CN214409968U (en) * | 2021-03-26 | 2021-10-15 | 公安部第一研究所 | FPGA remote updating device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN114546453A (en) * | 2022-04-27 | 2022-05-27 | 成都凯天电子股份有限公司 | FPGA configuration item online upgrading method, system, equipment and storage medium |
| CN114546453B (en) * | 2022-04-27 | 2022-09-09 | 成都凯天电子股份有限公司 | FPGA configuration item online upgrading method, system, equipment and storage medium |
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