CN114546453B - FPGA configuration item online upgrading method, system, equipment and storage medium - Google Patents

FPGA configuration item online upgrading method, system, equipment and storage medium Download PDF

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CN114546453B
CN114546453B CN202210448179.1A CN202210448179A CN114546453B CN 114546453 B CN114546453 B CN 114546453B CN 202210448179 A CN202210448179 A CN 202210448179A CN 114546453 B CN114546453 B CN 114546453B
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fpga
dsp
configuration
upgrading
online
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CN114546453A (en
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郭朋飞
胡青云
张竹
王乾丞
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Chengdu CAIC Electronics Co Ltd
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Chengdu CAIC Electronics Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/60—Software deployment
    • G06F8/65—Updates
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/70—Software maintenance or management
    • G06F8/71—Version control; Configuration management
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The invention provides an FPGA configuration item online upgrading method, system, equipment and storage medium, belonging to the technical field of communication. The method comprises the following steps: the upper computer sends an FPGA online upgrading instruction to the DSP, and the DSP sends an upgrading initialization instruction to the FPGA according to the online upgrading instruction; according to the upgrading initialization instruction, the FPGA executes online upgrading; after the FPGA is subjected to online upgrade, the FPGA loads logic codes from the 0 address of the configuration chip, and loads the logic codes corresponding to the board position signals according to the difference of the board position signals, so that the online upgrade of the FPGA configuration items and the multi-state loading of the logic codes are completed. The invention solves the problems of complex circuit and high hardware cost of FPGA online upgrade, multi-state code loading hardware, and simultaneously adopts two methods to ensure the FPGA configuration item to be upgraded online, thereby solving the problem that the working state of the product is still in a safe state after the FPGA configuration item fails to be upgraded online.

Description

FPGA configuration item online upgrading method, system, equipment and storage medium
Technical Field
The invention belongs to the technical field of communication, and particularly relates to an FPGA configuration item online upgrading method, system, equipment and storage medium.
Background
As avionic products become more complex and the requirement for processing data becomes higher, FPGAs are widely used in the avionic field, and more host vendors put higher requirements on loading and management of FPGA configuration items. The traditional upgrading of the FPGA configuration item through a board-level JTAG interface mode cannot meet the requirements of a host computer, and a host computer manufacturer preferably needs to complete the upgrading of the FPGA configuration item without opening a product or on an airplane through a special upgrading interface reserved outside the product, so that the host computer can conveniently upgrade the FPGA configuration item. In addition, host merchants face to FPGA configuration items of a plurality of onboard electronic products, generally require a set of products to ensure that one configuration item is owned as much as possible for convenient management, but in non-similarity dual-redundancy onboard products, FPGA implementation functions are different, and in order to facilitate logic development and hardware circuit design, when only one configuration item is provided, the FPGA needs to be provided with corresponding product function codes which are loaded in a self-adaptive manner according to different redundancy positions of the products.
The traditional Xilinx company K7 series FPGA configuration item online upgrading method mainly comprises the following two methods, one method is realized in a mode of MCU + CPLD + FPGA, in the mode, the MCU writes the configuration file of the FPGA into a configuration chip FLASH of the FPGA, after a product is electrified, the MCU reads configuration data in the FPGA configuration chip, the MCU sends the read configuration data to the CPLD, the CPLD simulates the loading time sequence of the FPGA to load the configuration data into the FPGA, the power-on configuration process of the FPGA is completed, the loading speed of the process is low, and an independent CPLD is needed to load service for codes of the FPGA, extra device overhead is provided, printing space is enlarged, and cost is high. The other mode is realized by a mode of MCU plus FPGA, in the mode, the MCU receives the FPGA configuration file data sent remotely, the MCU directly writes the received configuration file data into a configuration chip, and after the product is electrified, the FPGA reads the configuration data through a control bus to complete the loading of a logic code program, but the structural mode can not realize the loading of the logic program of the SPI FLASH based on a master-slave mode.
The traditional FPGA multi-state code loading implementation mode is mainly realized by a plug-in CPLD (complex programmable logic device). The method comprises the following steps: the method is realized by means of the plug-in CPLD, after the product is electrified, the CPLD gives a loading version, a loading trigger signal and a version selection signal, and the FPGA loads corresponding configuration items from the configuration chip again according to the version selection signal to complete multi-state code loading. The second method comprises the following steps: the method is realized by means of the MCU of the product, the MCU receives or identifies the version information of the logic codes and sends the version information of the logic codes to the FPGA, and after the FPGA receives the corresponding version information, the FPGA loads the corresponding configuration program from the configuration chip again to finish the loading of the multi-state codes. The method comprises the following steps: the realization mode has extra CPLD device overhead, increases printing space, has high cost, and has version information transmission and extra time overhead. The second method comprises the following steps: also, version information is transferred, extra time is consumed, and the MCU needs to be started prior to the FPGA before the FPGA can load the corresponding configuration version. For safety, the aviation onboard product generally requires that the FPGA and the MCU be started first to ensure the safety of the system output.
Disclosure of Invention
Aiming at the defects in the prior art, the method, the system, the electronic equipment and the storage medium for on-line upgrading of the FPGA configuration items solve the problems of complex circuit and high hardware cost of FPGA on-line upgrading and multi-state code loading hardware. Meanwhile, two methods are adopted to ensure the reliability and the safety of the on-line upgrading of the FPGA configuration items, and the problem that the working state of a product is still in a safe state after the on-line upgrading of the FPGA configuration items fails is solved.
In order to achieve the above purpose, the invention adopts the technical scheme that:
in a first aspect, the present disclosure provides an FPGA configuration item online upgrade method, including the following steps:
s1, sending an FPGA online upgrading instruction to the DSP by the upper computer, and sending an upgrading initialization instruction to the FPGA by the DSP according to the online upgrading instruction;
s2, according to the upgrading initialization instruction, the FPGA executes online upgrading;
and S3, after the FPGA is subjected to online upgrade, loading logic codes from the 0 address of the configuration chip by the FPGA, and loading the logic codes corresponding to the board position signals according to the difference of the board position signals to finish the online upgrade of the FPGA configuration items.
The invention has the beneficial effects that: the FPGA configuration item online upgrading method borrows an online upgrading channel of the DSP (a special connector interface is not reserved when the FPGA configuration file is transmitted from the outside, but the DSP online upgrading channel is used for transmitting the FPGA configuration file into the product and sending the FPGA configuration file to the FPGA by the DSP to complete data transmission), and a communication channel is used when the DSP and the FPGA work normally. The method is suitable for the field of online upgrade and multi-state configuration loading of configuration items of K7 series FPGA of Xilinx company by aviation onboard electronic products.
Further, in the step S2, the function codes of the running products of the FPGA are kept unchanged when the FPGA executes the online upgrade.
The beneficial effects of the further scheme are as follows: in the invention, the product is still in a normal working state in the on-line upgrading process of the FPGA configuration item, and special configuration item upgrading operation is carried out without interrupting the function of the product, so that the whole configuration item upgrading process is convenient and efficient.
Still further, the step S2 includes the steps of:
s201, initializing a configuration chip of the FPGA according to the upgrading initialization instruction;
s202, sending an initialization result to the DSP by the FPGA through the bus, and sending the initialization result to an upper computer by the DSP through a special upgrading port of the DSP;
s203, judging whether the initialization of the configuration chip is successful, if so, entering a step S204, otherwise, returning to the step S1;
s204, erasing the configuration chip by the FPGA, and erasing a code storage area outside the Golden area;
s205, sending the configuration chip erasing result to the DSP through a bus, and sending the configuration chip erasing result to an upper computer through a special upgrading port of the DSP by the DSP;
s206, according to the erasing result of the configuration chip, the upper computer sends the generated bin format configuration file to the DSP through a DSP special upgrading port;
s207, the DSP checks the received configuration file and sends the checked configuration file to the FPGA through a bus;
s208, receiving the configuration file by the FPGA, retrieving the product function code to be upgraded according to the synchronization head, and writing the product function code to be upgraded into the configuration chip from the function storage area address of the configuration chip;
and S209, the FPGA sends the state information written into the configuration chip to the DSP, the DSP sends the state information to an upper computer, and the FPGA finishes on-line upgrading.
The beneficial effects of the further scheme are as follows: in the invention, in the process of upgrading the configuration items of the FPGA, the operation state of the FPGA to the configuration chip is uploaded to the upper computer, so that the operation process of the FPGA to the configuration chip is transparent, the fault problem is easy to position and troubleshoot in the process of upgrading the configuration items, and the maintainability of the whole product is enhanced.
Further, in the step S2, the FPGA needs to monitor the configuration file during the online upgrade execution process, and if the configuration file is abnormal, the FPGA closes the online upgrade function, and notifies the DSP to wait for sending a new online upgrade instruction.
The beneficial effects of the above further scheme are: in the invention, two methods are adopted to ensure the reliability of upgrading, one is that: the FPGA monitors the integrity and continuity of the configuration data in the processes of receiving the configuration data and reading and writing the configuration chip, if the configuration data is abnormal or discontinuous, the FPGA informs the DSP that the upgrading is abnormal, and under the condition of no power failure, the DSP can send a request instruction again and upgrade again until the configuration data is completely written into the configuration chip, so that the FPGA can perform code online upgrading again and the reliability of code online upgrading is ensured.
Still further, the bin format profile is generated from a Golden region code and a number of product function codes.
The beneficial effects of the further scheme are as follows: in the invention, in the process of realizing the upgrading of the FPGA configuration item, the Golden region code and a plurality of product function codes are combined to generate a configuration item, so that the whole product is ensured to be finished by one configuration item no matter the upgrading of the configuration item is realized or the function of non-similar redundancy, the management of the configuration item by a host manufacturer is facilitated, the simultaneous existence of the upgrading of the configuration item and the realization of the product function is ensured, and the upgrading of the configuration item is efficient and rapid.
Still further, the step S3 includes the following steps:
s301, completing on-line upgrading aiming at the FPGA, and loading Golden region codes in the address of the configuration chip 0 by the FPGA after the FPGA is electrified again;
s302, reading the state of a BOOTSTS register in the FPGA through ICAPE 2;
s303, judging whether a Golden region code is loaded for the first time of power-on according to the state of the BOOTSTS register, if so, entering the step S304, otherwise, loading the Golden region code for fallback operation, and entering the step S307;
s304, setting a DSP reset signal low, and keeping the DSP in a reset state;
s305, recognizing board position signals, reconfiguring a configuration register of the FPGA through ICAPE2 according to different board position signals, determining a jump address of the configuration register of the FPGA, and generating an IPROG instruction;
s306, according to the IPROG instruction, the FPGA reloads the product function codes corresponding to the board position signals, and online upgrade of FPGA configuration items is completed;
s307, setting a DSP reset signal high, and starting a DSP function;
and S308, uploading the version information of the FPGA running codes, and instructing the upper computer to perform online upgrade of the FPGA configuration items again.
The beneficial effects of the above further scheme are: in the invention, two methods are adopted to ensure the reliability of upgrading, and the second method is as follows: the invention adopts a fallback mechanism in the code loading process. Even if the upgrading code has a fault in the process of writing the upgrading code into the configuration chip and the FPGA cannot normally load the product function code, the FPGA performs fallback to reload the Golden region (the configuration chip 0 address start guide region) code, so that the FPGA can perform online upgrading of the code again, and the reliability of online upgrading of the code is ensured. Meanwhile, the loading of the FPGA multiple configuration items is realized by adopting the external or internal discrete board position signal guidance of the product, the circuit is simple and reliable to realize, and the response speed is high.
In a second aspect, the present invention provides an FPGA configuration item online upgrade system, including:
the upgrading request module is used for sending an FPGA online upgrading instruction to the DSP by the upper computer and sending an upgrading initialization instruction to the FPGA by the DSP according to the online upgrading instruction;
the upgrade execution module is used for executing online upgrade by the FPGA according to the upgrade initialization instruction;
and the upgrading module is used for loading logic codes from the 0 address of the configuration chip by the FPGA after the FPGA executes online upgrading, loading the logic codes corresponding to the board position signals according to the difference of the board position signals and finishing the online upgrading of the FPGA configuration items.
The invention has the beneficial effects that: the FPGA configuration item online upgrading method borrows an online upgrading channel of the DSP (a special connector interface is not reserved when the FPGA configuration file is transmitted from the outside, but the DSP online upgrading channel is used for transmitting the FPGA configuration file into the product and sending the FPGA configuration file to the FPGA by the DSP to complete data transmission), and a communication channel is used when the DSP and the FPGA work normally. The method is suitable for the field of online upgrade and multi-state configuration loading of configuration items of K7 series FPGA of Xilinx company by aviation onboard electronic products.
Furthermore, the FPGA keeps the function codes of the running products of the FPGA unchanged when the FPGA executes online upgrading.
The beneficial effects of the above further scheme are: in the invention, the product is still in a normal working state in the on-line upgrading process of the FPGA configuration item, and special configuration item upgrading operation is carried out without interrupting the function of the product, so that the whole configuration item upgrading process is convenient and efficient.
Still further, the upgrade execution module includes:
the initialization unit is used for initializing a configuration chip of the FPGA according to the upgrading initialization instruction;
the first transmission unit is used for sending an initialization result to the DSP through the bus by the FPGA and sending the initialization result to the upper computer through the DSP special upgrading port by the DSP;
the first judging unit is used for judging whether the initialization of the configuration chip is successful or not;
the erasing unit is used for erasing the configuration chip by the FPGA and erasing the code storage area outside the Golden area;
the second transmission unit is used for sending the configuration chip erasing result to the DSP through a bus, and the DSP sends the configuration chip erasing result to the upper computer through a special upgrading port of the DSP;
the third transmission unit is used for transmitting the generated bin format configuration file to the DSP through the DSP special upgrading port by the upper computer according to the configuration chip erasing result;
the fourth transmission unit is used for checking the received configuration file by the DSP and sending the checked configuration file to the FPGA through the bus;
the writing-in unit is used for receiving the configuration file by the FPGA, retrieving the product function code to be upgraded according to the synchronous head and writing the product function code to be upgraded into the configuration chip from the function storage area address of the configuration chip;
and the fifth transmission unit is used for sending the state information written into the configuration chip to the DSP by the FPGA and sending the state information to the upper computer by the DSP, and the FPGA finishes on-line upgrading.
The beneficial effects of the further scheme are as follows: in the invention, in the process of realizing the upgrading of the configuration items of the FPGA, the operation state of the configuration chip by the FPGA is uploaded to the upper computer, so that the operation process of the configuration chip by the FPGA is transparent, the fault problem is easy to position and troubleshoot in the process of upgrading the configuration items, and the maintainability of the whole product is enhanced.
Furthermore, the configuration file needs to be monitored in the process of executing the online upgrade by the FPGA, if the configuration file is abnormal, the FPGA closes the online upgrade function, informs the DSP and waits for sending a new online upgrade instruction.
The beneficial effects of the further scheme are as follows: in the invention, two methods are adopted to ensure the reliability of upgrading, one is that: the FPGA monitors the integrity and continuity of the configuration data in the processes of receiving the configuration data and reading and writing the configuration chip, if the configuration data is abnormal or discontinuous, the FPGA informs the DSP that the upgrading is abnormal, and under the condition of no power failure, the DSP can send a request instruction again and upgrade again until the configuration data is completely written into the configuration chip, so that the FPGA can perform code online upgrade again and the reliability of code online upgrade is ensured.
Still further, the bin format profile is generated from a Golden region code and a number of product function codes.
The beneficial effects of the further scheme are as follows: in the invention, in the process of realizing the upgrading of the FPGA configuration item, the Golden region code and a plurality of product function codes are combined to generate a configuration item, so that the whole product is ensured to be finished by one configuration item no matter the upgrading of the configuration item is realized or the function of non-similar redundancy, the management of the configuration item by a host manufacturer is facilitated, the simultaneous existence of the upgrading of the configuration item and the realization of the product function is ensured, and the upgrading of the configuration item is efficient and rapid.
Still further, the upgrade module includes:
the logic code loading unit is used for completing on-line upgrading aiming at the FPGA, and loading Golden region codes in the address of the configuration chip 0 by the FPGA after the FPGA is electrified again;
the reading unit is used for reading the state of the BOOTSTS register in the FPGA through ICAPE 2;
the second judging unit is used for judging whether to load a Golden region code for first power-on or load the Golden region code for fallback operation according to the state of the BOOTSTS register;
the first reset unit is used for setting a DSP reset signal and keeping the DSP in a reset state;
the instruction generating unit is used for identifying the board bit signals, reconfiguring the configuration register of the FPGA through ICAPE2 according to different board bit signals, determining the jump address of the FPGA configuration register and generating an IPROG instruction;
the first upgrading unit is used for reloading the product function codes corresponding to the board position signals by the FPGA according to the IPROG instruction so as to complete the online upgrading of the FPGA configuration items;
the second reset unit is used for setting a DSP reset signal high and starting a DSP function;
and the second upgrading unit is used for uploading the version information of the FPGA running codes and instructing the upper computer to carry out online upgrading on the FPGA configuration items again.
The beneficial effects of the further scheme are as follows: in the invention, two methods are adopted to ensure the reliability of upgrading, and the second method is as follows: the invention adopts a fallback mechanism in the code loading process. Even if the upgrading code has a fault in the process of writing the upgrading code into the configuration chip and the FPGA cannot normally load the product function code, the FPGA performs fallback to reload the Golden region (the configuration chip 0 address start guide region) code, so that the FPGA can perform online upgrading of the code again, and the reliability of online upgrading of the code is ensured. Meanwhile, the loading of the FPGA multi-configuration items is realized by adopting the external or internal discrete board position signal guidance of the product, the circuit is simple and reliable to realize, and the response speed is high.
In a third aspect, the present invention provides an apparatus, including a memory, a processor, and a computer program stored in the memory and running on the processor, where the processor executes the program to implement any of the steps of the FPGA configuration item online upgrade method.
In a fourth aspect, the present invention provides a computer-readable storage medium, where a computer program is stored, and when the computer program is executed, the steps of the FPGA configuration item online upgrade method are implemented.
Drawings
FIG. 1 is a flow chart of the method of the present invention.
Fig. 2 is a block diagram of an online configuration file in the embodiment.
Fig. 3 is a block diagram of the hardware system for on-line FPGA upgrade in this embodiment.
FIG. 4 is a schematic diagram of the system of the present invention.
Detailed Description
The following description of the embodiments of the present invention is provided to facilitate the understanding of the present invention by those skilled in the art, but it should be understood that the present invention is not limited to the scope of the embodiments, and it will be apparent to those skilled in the art that various changes may be made without departing from the spirit and scope of the invention as defined and defined in the appended claims, and all matters produced by the invention using the inventive concept are protected.
Example 1
As shown in fig. 1, the present invention provides an online upgrade method for FPGA configuration items, which includes:
s1, sending an FPGA online upgrading instruction to the DSP by the upper computer, and sending an upgrading initialization instruction to the FPGA by the DSP according to the online upgrading instruction;
in this embodiment, the upper computer sends an FPGA online upgrade instruction to the DSP through the dedicated upgrade port for the DSP, and the DSP sends an upgrade initialization instruction to the FPGA through the communication interface with the FPGA according to the online upgrade instruction.
In this embodiment, the bin configuration file needs to be configured to the FPGA once through the JTAG configuration port before the product is assembled. When the product normally works and an external upper computer (PC) needs to carry out code online upgrading, firstly, the upper computer (PC) sends an FPGA online upgrading instruction to the DSP through a special code upgrading port of the DSP, and the DSP sends an upgrading initialization instruction to the FPGA after receiving the instruction.
And S2, performing online upgrade by the FPGA according to the upgrade initialization instruction, keeping the function code of the product which runs normally unchanged when the FPGA performs online upgrade, monitoring a configuration file in the process of performing online upgrade by the FPGA, closing the online upgrade function by the FPGA if the configuration file is abnormal, informing the DSP, and waiting for sending a new online upgrade instruction. The FPGA execution online upgrade realization method comprises the following steps:
s201, initializing a configuration chip of the FPGA according to the upgrading initialization instruction;
s202, sending an initialization result to the DSP by the FPGA through the bus, and sending the initialization result to an upper computer by the DSP through a special upgrading port of the DSP;
s203, judging whether the initialization of the configuration chip is successful, if so, entering a step S204, otherwise, returning to the step S1;
s204, erasing the configuration chip by the FPGA, and erasing a code storage area outside the Golden area;
s205, sending the configuration chip erasing result to the DSP through a bus, and sending the configuration chip erasing result to an upper computer through a DSP special upgrading port by the DSP;
s206, according to the configuration chip erasing result, the upper computer sends the generated bin format configuration file to the DSP through the DSP special upgrading port;
s207, checking the received configuration file by the DSP, and sending the checked configuration file to the FPGA through a bus;
s208, receiving the configuration file by the FPGA, retrieving the product function code to be upgraded according to the synchronization head, and writing the product function code to be upgraded into the configuration chip from the function storage area address of the configuration chip;
and S209, sending the state information written into the configuration chip to the DSP by the FPGA, sending the state information to an upper computer by the DSP, and executing online upgrade by the FPGA. In the invention, the FPGA sends the state information of whether the configuration chip is successfully written to the DSP, the DSP sends the state information to the upper computer, and the upper computer receives the successful state information and the FPGA finishes on-line upgrading. If the upper computer receives the failure status message, it may return to S1 to execute again.
In this embodiment, as shown in fig. 2, the configuration file of the online upgrade is a file in the bin format, which can be generated by Xilinx development tools Vivado and ISE.
In the embodiment, after the FPGA judges that the initialization of the configuration chip is successful, the process of erasing the configuration chip is automatically started without receiving any instruction. In the invention, the configured chip erasing result is sent to the upper computer through the DSP special upgrading port, aiming at ensuring that an operator knows whether the initialization step is successful, if an error occurs in the upgrading process and the initialization step cannot be completed, the operator can determine an error link according to the returned step state information, such as: initialization error or chip erasure error is convenient for subsequent problem positioning and troubleshooting work.
In the embodiment, the FPGA upgrading is finished by using the DSP upgrading port without additionally designing a circuit, so that the complexity of an external interface of a product can be effectively reduced.
In this embodiment, for performing online upgrade on an FPGA, the MCU in the implementation of the present invention is replaced with a DSP, but the present invention is also applicable to an MCU.
In this embodiment, the Golden region code of the present invention mainly has functions including: completing the on-line upgrading function of the FPGA configuration item; recognizing board bit signals, configuring a jump address of an FPGA configuration register through ICAPE2 (FPGA primitive) according to different board bit signals, generating an IPROG instruction (FPGA reset instruction), and enabling the FPGA to jump to a storage area corresponding to a configuration chip to load a product function code; reading a BOOTSTS register (a guide history state register) of the FPGA, controlling a reset signal of the DSP according to the state of the BOOTSTS register, if the reset signal is loaded due to fallback, pulling up the reset signal of the DSP to enable the DSP function, and if the code is loaded for the first time due to power-on, keeping the reset signal of the DSP at a low level to enable the DSP to be in a reset state; and running a code version state uploading function.
In this embodiment, the main functions of the product function code in the present invention include: a product logic function; the FPGA configuration item has an online upgrading function; after the uploading function of the running code version state is completed, the FPGA starts to load the logic code from the 0 address of the configuration chip, and the FPGA configuration item is upgraded on line according to the loaded logic code.
In this embodiment, when online upgrade is required, the DSP sends an online upgrade request instruction to the FPGA, and after the FPGA receives the upgrade instruction, the FPGA opens the online upgrade function, and the FPGA still operates normal function codes. After receiving an online upgrading instruction of the FPGA, the DSP receives an FPGA configuration file sent from the outside from a product connector through an online upgrading port of the DSP under the condition of not opening a product; the DSP checks the received FPGA configuration file, and the DSP sends the checked FPGA configuration file to the FPGA through a bus (an EMIF (external memory interface) bus or a serial bus) connected with the FPGA; the FPGA writes the received FPGA configuration file into a configuration chip through a bus (a parallel bus or an SPI bus); in the process of writing the FPGA configuration file into the configuration chip, the FPGA sends necessary state information such as successful initialization of the configuration chip, ongoing writing of the FPGA configuration file, successful writing of the FPGA configuration file and the like to the DSP through a bus (an EMIF bus or a serial bus) connected with the DSP, and meanwhile, the DSP sends the state information to an upper computer for being checked by an online upgrade worker. And the FPGA monitors configuration data in the upgrading process, and if the FPGA judges that the data is abnormal (incomplete or discontinuous in transmission), the FPGA closes the online upgrading function, informs the DSP and waits for a DSP upgrading request instruction again to carry out next upgrading.
In the embodiment, after receiving an online upgrade instruction request of a DSP, an FPGA needs to initialize a configuration chip of the FPGA, if the initialization is successful, the FPGA erases a product function code stored in the configuration chip, if the initialization of the configuration chip is failed, the FPGA does not erase the configuration chip, and enters a state of waiting for the request instruction so as to upgrade the configuration item of the FPGA again; after receiving the state that the configuration chip is successfully erased, the DSP sends configuration data to the FPGA, the FPGA packages the received data and writes the packaged data into the configuration chip, after one packet of data is written, the write address is added, and the next packet of data is waited to be received and written until the configuration data is completely written.
As shown in FIG. 3, taking Xilinx family FPGA-K7 as an example, the bin configuration file needs to be solidified once for the FPGA through the JTAG configuration interface before the product is assembled. When online upgrade is needed, a PC (upper computer) sends a loading command (upgrade instruction) and an FPGA configuration file to a DSP special online upgrade interface (SCI) through a TX bus by using an RS232 interface, after receiving the loading instruction and the FPGA configuration file, the DSP sends the loading instruction and the FPGA configuration file to an FPGA internal programming interface through a bus (an EMIF (external memory interface) bus or a serial bus) connected with the FPGA, and after receiving the upgrade instruction, the FPGA opens an online upgrade function and still runs normal function codes. The FPGA writes the received FPGA configuration file into a configuration chip through a bus (a parallel bus or an SPI bus); in the process of writing the FPGA configuration file into the configuration chip, the FPGA sends necessary state information such as successful initialization of the configuration chip, ongoing writing of the FPGA configuration file, successful writing of the FPGA configuration file and the like to the DSP through a bus (an EMIF bus or a serial bus) connected with the DSP, meanwhile, the DSP sends the state information to an upper computer through a TX bus, and the upper computer displays the loading state information for online upgrade personnel to check. The FPGA monitors the FPGA configuration file in the upgrading process, if the FPGA judges that the file data is abnormal (incomplete or discontinuous in transmission), the FPGA closes the online upgrading function, informs the DSP through a bus connected with the DSP and waits for a DSP upgrading request instruction again to carry out next upgrading. After the FPGA finishes on-line upgrading, after a product is electrified again, the FPGA starts to load logic codes from an address 0 of a configuration chip, Golden region codes are loaded and run, the state in a BOOTSTS register in the FPGA is read through ICAPE2, whether the Golden region codes are loaded due to first electrification or due to fallback is judged, if the Golden region codes are loaded due to first electrification, a DSP reset signal is kept low, meanwhile, input board signals are identified, the configuration register of the FPGA is reconfigured through ICAPE2 according to different board signals, a jump address is determined, an IPROG signal is generated, the FPGA reloads function codes corresponding to the board signals, multi-state configuration of the FPGA codes is finished, the reset signal is pulled up, and the product enters a normal function; if the reason of fallback results in, setting up a reset signal of the DSP, and starting a DSP software function; uploading the version information of the FPGA running code and instructing an upper computer (PC) to perform online upgrade of the configuration item again.
In this embodiment, the product design architecture of the present invention is DSP + FPGA, the DSP function is to implement a software control function, the FPGA function implements a hardware logic function, the two implementation functions are different, and the two functions together constitute a product software function.
S3, after the FPGA is subjected to online upgrade, the FPGA loads logic codes from the 0 address of the configuration chip, and loads the logic codes corresponding to the board position signals according to the difference of the board position signals to complete the online upgrade of the FPGA configuration items, and the implementation method comprises the following steps:
s301, completing on-line upgrading aiming at the FPGA, and loading Golden region codes in the address of the configuration chip 0 by the FPGA after the FPGA is electrified again;
s302, reading the state of a BOOTSTS register in the FPGA through ICAPE 2;
s303, judging whether to load a Golden region code for the first power-on according to the state of the BOOTSTS register, if so, entering a step S304, otherwise, loading the Golden region code for a fallback operation, and entering a step S307;
s304, setting a DSP reset signal low, and keeping the DSP in a reset state;
s305, recognizing board position signals, reconfiguring a configuration register of the FPGA through ICAPE2 according to different board position signals, determining a jump address of the configuration register of the FPGA, and generating an IPROG instruction;
s306, according to the IPROG instruction, the FPGA reloads the product function codes corresponding to the board position signals, and the on-line upgrading of the FPGA configuration items is completed, namely the multi-state code loading of the FPGA configuration items is completed;
s307, setting a DSP reset signal high, and starting a DSP function;
and S308, uploading the version information of the FPGA running code, and instructing the upper computer to perform online upgrade of the FPGA configuration item again, wherein the output of the output port is in a safe state.
In the embodiment, after the FPGA finishes on-line upgrading, the FPGA loads logic codes from the 0 address of the configuration chip after the product is electrified again, that is, Golden region (configuring chip 0 address starting guide region) codes are loaded in the FPGA configuration chip, the Golden region (configuring chip 0 address starting guide region) codes identify plate position signals, after Golden region codes are loaded and run, reading the state in a BOOTSTS register in the FPGA through ICAPE2, judging whether the Golden region code is loaded due to first power-on or the fallback reason, if the Golden region code is loaded due to the first power-on, keeping the DSP reset signal low, ensuring that the DSP is in a reset state, identifying an externally input board position signal, reconfiguring a configuration register of the FPGA through ICAPE2, determining a jump address, generating an IPROG instruction, and enabling the FPGA to reload a function code corresponding to a board position signal to complete multi-state configuration of the FPGA; if the FPGA has an error in loading the function code and is caused by the reason of fallback, setting up a reset signal of the DSP, and starting the DSP function; uploading the version information of the FPGA running code and instructing an upper computer (PC) to perform online upgrade of the configuration item again.
In the embodiment, the on-line upgrading mode of the FPGA configuration item borrows the on-line upgrading channel of the MCU/DSP and the communication channel of the MCU/DSP and the FPGA, so that additional circuit components are not required to be added, and the hardware design cost is reduced. Firstly, the FPGA monitors the integrity and the continuity of an FPGA configuration file in the processes of receiving configuration data and reading and writing a configuration chip, if the FPGA configuration file is abnormal or discontinuous, the FPGA informs the DSP that the upgrading is abnormal, and under the condition of no power failure, the DSP can send a request instruction again and upgrade the FPGA configuration file again until the FPGA configuration file is completely written into the configuration chip. Secondly, a fallback mechanism in the code loading process is adopted, so that even if an upgrading code is wrongly written into a configuration chip, and an FPGA cannot normally load a product function code, the FPGA needs to perform fallback, and a Golden region (a 0-address starting guide region of the configuration chip) code can be reloaded, thereby ensuring that the FPGA can perform code online upgrading again. Thereby ensuring the reliability of code on-line upgrade. The online upgrading method of the invention adopts the FPGA to directly operate the configuration chip to read and write the configuration item code, thereby avoiding the phenomenon of sharing an interface with the MCU/DSP, and being applicable to NOR FLASH and FLASH based on an SPI bus.
Example 2
As shown in fig. 4, the present invention provides an FPGA configuration item online upgrade system, including:
the upgrading request module is used for sending an FPGA online upgrading instruction to the DSP by the upper computer and sending an upgrading initialization instruction to the FPGA by the DSP according to the online upgrading instruction;
the upgrade execution module is used for executing online upgrade by the FPGA according to the upgrade initialization instruction;
and the upgrading module is used for loading logic codes from the 0 address of the configuration chip by the FPGA after the FPGA executes online upgrading, loading the logic codes corresponding to the board position signals according to the difference of the board position signals and finishing the online upgrading of the FPGA configuration items.
In one embodiment, the FPGA keeps the function codes of the running products of the FPGA unchanged when the FPGA executes online upgrading.
In one embodiment, the upgrade execution module includes:
the initialization unit is used for initializing a configuration chip of the FPGA according to the upgrading initialization instruction;
the first transmission unit is used for sending an initialization result to the DSP through the bus by the FPGA and sending the initialization result to the upper computer through the DSP special upgrading port by the DSP;
the first judging unit is used for judging whether the initialization of the configuration chip is successful or not;
the erasing unit is used for erasing the configuration chip by the FPGA and erasing a code storage area outside the Golden area;
the second transmission unit is used for sending the configuration chip erasing result to the DSP through a bus, and the DSP sends the configuration chip erasing result to the upper computer through a special upgrading port of the DSP;
the third transmission unit is used for transmitting the generated bin format configuration file to the DSP through the DSP special upgrading port by the upper computer according to the configuration chip erasing result;
the fourth transmission unit is used for checking the received configuration file by the DSP and sending the checked configuration file to the FPGA through the bus;
the writing unit is used for receiving the configuration file by the FPGA, retrieving the product function code to be upgraded according to the synchronization head and writing the product function code to be upgraded into the configuration chip from the function storage area address of the configuration chip;
and the fifth transmission unit is used for sending the state information written into the configuration chip to the DSP by the FPGA and sending the state information to the upper computer by the DSP, and the FPGA executes online upgrade.
In one embodiment, the configuration file needs to be monitored in the process of performing online upgrade by the FPGA, if the configuration file is abnormal, the FPGA closes the online upgrade function, and notifies the DSP to wait for sending a new online upgrade instruction.
In one embodiment, the bin format profile is generated from a Golden region code and a number of product function codes.
In one embodiment, the upgrade module includes:
the logic code loading unit is used for completing on-line upgrading aiming at the FPGA, and loading Golden region codes in the address of the configuration chip 0 by the FPGA after the FPGA is electrified again;
the reading unit is used for reading the state of the BOOTSTS register in the FPGA through ICAPE 2;
the second judging unit is used for judging whether to load a Golden region code for first power-on or load the Golden region code for fallback operation according to the state of the BOOTSTS register;
the first reset unit is used for setting a DSP reset signal low and keeping the DSP in a reset state;
the instruction generating unit is used for identifying the board position signals, reconfiguring a configuration register of the FPGA through ICAPE2 according to different board position signals, determining a jump address of the configuration register of the FPGA and generating an IPROG instruction;
the first upgrading unit is used for reloading the product function codes corresponding to the board position signals by the FPGA according to the IPROG instruction so as to complete the online upgrading of the FPGA configuration items;
the second reset unit is used for setting a DSP reset signal high and starting a DSP function;
and the second upgrading unit is used for uploading the version information of the FPGA running codes and instructing the upper computer to carry out online upgrading on the FPGA configuration items again.
The FPGA configuration item online upgrade system provided in the embodiment shown in fig. 4 can execute the technical solution shown in the FPGA configuration item online upgrade method in the above method embodiment, and the implementation principle and the beneficial effect are similar, which are not described herein again.
In the embodiment of the invention, the functional units can be divided according to the FPGA configuration item online upgrading method, for example, each function can be divided into each functional unit, and two or more functions can be integrated into one processing unit. The integrated unit may be implemented in the form of hardware, or may be implemented in the form of a software functional unit. It should be noted that the division of the cells in the present invention is schematic, and is only a logical division, and there may be another division manner in actual implementation.
In the embodiment of the invention, the FPGA configuration item online upgrading system comprises a hardware structure and/or a software module corresponding to each function in order to realize the principle and the beneficial effect of the FPGA configuration item online upgrading method. Those of skill in the art will readily appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as hardware and/or combinations of hardware and computer software, where a function is performed in a hardware or computer software-driven manner, and that the function described may be implemented in any suitable manner for each particular application depending upon the particular application and design constraints imposed on the technology, but such implementation is not to be considered as beyond the scope of the present application.
In the embodiment, the on-line upgrading mode of the FPGA configuration item borrows the on-line upgrading channel of the MCU/DSP and the communication channel of the MCU/DSP and the FPGA, so that additional circuit components are not required to be added, and the hardware design cost is reduced. Meanwhile, two methods are adopted in the invention to ensure the online reliability of the FPGA configuration items. Firstly, the FPGA monitors the integrity and continuity of an FPGA configuration file in the processes of receiving configuration data and reading and writing a configuration chip, if the FPGA configuration file is abnormal or interrupted, the FPGA informs the DSP that the upgrading is abnormal, and under the condition of not powering off, the DSP can send a request instruction again and upgrade again until the FPGA configuration file is completely written into the configuration chip. Secondly, a fallback mechanism in the code loading process is adopted, so that even if an upgrading code is wrongly written into a configuration chip, and an FPGA cannot normally load a product function code, the FPGA needs to perform fallback and can reload a Golden region (a configuration chip 0 address start guide region) code, thereby ensuring that the FPGA can perform code online upgrading again, and ensuring the reliability of code online upgrading. The online upgrading method of the invention adopts the FPGA to directly operate the configuration chip to read and write the configuration item code, thereby avoiding the phenomenon of sharing an interface with the MCU/DSP, and being applicable to NOR FLASH and FLASH based on an SPI bus.
Example 3
The invention provides equipment which comprises a memory, a processor and a computer program stored on the memory and operated on the processor, wherein the processor executes the program to realize the steps of the FPGA configuration item online upgrading method in embodiment 1.
In this embodiment, the device may include: the system comprises a processor, a memory, a bus and a communication interface, wherein the processor, the communication interface and the memory are connected through the bus, a computer program capable of running on the processor is stored in the memory, and when the processor runs the computer program, part or all of the steps of the FPGA configuration item online upgrading method provided by the foregoing embodiment 1 of the present application are executed.
Example 4
The invention provides a computer-readable storage medium, which stores a computer program, and when the computer program is executed, the steps of the FPGA configuration item online upgrade method described in embodiment 1 are realized.
The computer-readable storage medium described above may be implemented in any type or combination of volatile or non-volatile memory devices such as Static Random Access Memory (SRAM), erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic or optical disks, and may be any available medium that can be accessed by a general purpose or special purpose computer. A readable storage medium is coupled to the processor such that the processor can read information from, and write information to, the readable storage medium, which may also be a component of the processor, and the processor and the readable storage medium may reside in an Application Specific Integrated Circuit (ASIC), and the processor and the readable storage medium may also reside as discrete components in the FPGA-configuration item online upgrade system.
Embodiments of the present invention may be provided as a method, apparatus, or computer program product, and as such, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) having computer-usable program code embodied therein. While the methods, apparatus (devices), and computer program products according to embodiments of the invention have been described with reference to flowchart illustrations and/or block diagrams, it is to be understood that each flowchart illustration and/or block diagram block or blocks, and combinations of flowchart illustrations and/or block diagrams, can be implemented by computer program instructions which are provided to a computer-readable memory of a general purpose computer, special purpose computer, embedded computer, or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart illustration of one or more flow diagrams and/or block diagrams block or blocks. These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart block or blocks and/or flowchart block or blocks.
It will be appreciated by those skilled in the art that the embodiments described herein are intended to assist the reader in understanding the principles of the invention and it is to be understood that the scope of the invention is not to be limited to such specific statements and embodiments. Those skilled in the art, having the benefit of this disclosure, may effect numerous modifications thereto and changes may be made without departing from the scope of the invention in its aspects.

Claims (10)

1. An FPGA configuration item online upgrading method is characterized by comprising the following steps:
s1, sending an FPGA online upgrading instruction to the DSP by the upper computer, and sending an upgrading initialization instruction to the FPGA by the DSP according to the online upgrading instruction;
s2, according to the upgrading initialization instruction, the FPGA executes online upgrading;
the step S2 includes the steps of:
s201, initializing a configuration chip of the FPGA according to the upgrading initialization instruction;
s202, sending an initialization result to the DSP by the FPGA through the bus, and sending the initialization result to an upper computer by the DSP through a special upgrading port of the DSP;
s203, judging whether the initialization of the configuration chip is successful, if so, entering a step S204, otherwise, returning to the step S1;
s204, erasing the configuration chip by the FPGA, and erasing a code storage area outside the Golden area;
s205, sending the configuration chip erasing result to the DSP through a bus, and sending the configuration chip erasing result to an upper computer through a special upgrading port of the DSP by the DSP;
s206, according to the configuration chip erasing result, the upper computer sends the generated bin format configuration file to the DSP through the DSP special upgrading port;
s207, checking the received configuration file by the DSP, and sending the checked configuration file to the FPGA through a bus;
s208, receiving the configuration file by the FPGA, retrieving the product function code to be upgraded according to the synchronization head, and writing the product function code to be upgraded into the configuration chip from the function storage area address of the configuration chip;
s209, the FPGA sends the state information written into the configuration chip to the DSP, the DSP sends the state information to an upper computer, and the FPGA finishes on-line upgrading;
s3, after the FPGA is subjected to online upgrade, loading logic codes from the 0 address of the configuration chip by the FPGA, and loading the logic codes corresponding to the board position signals according to the difference of the board position signals to complete the online upgrade of the FPGA configuration items;
the step S3 includes the steps of:
s301, completing on-line upgrading aiming at the FPGA, and loading Golden region codes in the address of the configuration chip 0 by the FPGA after the FPGA is electrified again;
s302, reading the state of a BOOTSTS register in the FPGA through ICAPE 2;
s303, judging whether a Golden region code is loaded for the first time of power-on according to the state of the BOOTSTS register, if so, entering the step S304, otherwise, loading the Golden region code for fallback operation, and entering the step S307;
s304, setting a DSP reset signal low, and keeping the DSP in a reset state;
s305, recognizing the board bit signals, reconfiguring the configuration register of the FPGA through ICAPE2 according to different board bit signals, determining the jump address of the FPGA configuration register, and generating an IPROG instruction;
s306, according to the IPROG instruction, the FPGA reloads the product function codes corresponding to the board position signals, and online upgrade of FPGA configuration items is completed;
s307, setting a DSP reset signal high, and starting a DSP function;
and S308, uploading the version information of the FPGA running code and instructing the upper computer to perform online upgrade of the FPGA configuration item again.
2. The method for upgrading an FPGA configuration item on line according to claim 1, wherein in the step S2, the function codes of the running products of the FPGA are kept unchanged when the FPGA executes the on-line upgrading.
3. The on-line upgrade method for the FPGA configuration item according to claim 2, wherein in the step S2, the FPGA needs to monitor the configuration file during the on-line upgrade process, and if the configuration file is abnormal, the FPGA closes the on-line upgrade function and notifies the DSP to wait for sending a new on-line upgrade instruction.
4. The FPGA configuration item on-line upgrading method of claim 3, wherein the bin format configuration file is generated by a Golden region code and a plurality of product function codes.
5. An FPGA configuration item online upgrading system is characterized by comprising:
the upgrading request module is used for sending an FPGA online upgrading instruction to the DSP by the upper computer and sending an upgrading initialization instruction to the FPGA by the DSP according to the online upgrading instruction;
the upgrade execution module is used for executing online upgrade by the FPGA according to the upgrade initialization instruction;
the upgrade execution module includes:
the initialization unit is used for initializing a configuration chip of the FPGA according to the upgrading initialization instruction;
the first transmission unit is used for sending an initialization result to the DSP through the bus by the FPGA and sending the initialization result to the upper computer through the DSP special upgrading port by the DSP;
the first judging unit is used for judging whether the initialization of the configuration chip is successful or not;
the erasing unit is used for erasing the configuration chip by the FPGA and erasing the code storage area outside the Golden area;
the second transmission unit is used for sending the configuration chip erasing result to the DSP through a bus, and the DSP sends the configuration chip erasing result to the upper computer through a special upgrading port of the DSP;
the third transmission unit is used for transmitting the generated bin format configuration file to the DSP through the DSP special upgrading port according to the configuration chip erasing result;
the fourth transmission unit is used for checking the received configuration file by the DSP and sending the checked configuration file to the FPGA through the bus;
the writing unit is used for receiving the configuration file by the FPGA, retrieving the product function code to be upgraded according to the synchronization head and writing the product function code to be upgraded into the configuration chip from the function storage area address of the configuration chip;
the fifth transmission unit is used for sending the state information written into the configuration chip to the DSP by the FPGA and sending the state information to the upper computer by the DSP, and the FPGA finishes on-line upgrading;
the upgrading module is used for loading logic codes from the 0 address of the configuration chip by the FPGA after the FPGA executes online upgrading, loading the logic codes corresponding to the board position signals according to the difference of the board position signals and finishing the online upgrading of the FPGA configuration items;
the upgrade module includes:
the logic code loading unit is used for completing on-line upgrading aiming at the FPGA, and loading Golden region codes in the address of the configuration chip 0 by the FPGA after the FPGA is electrified again;
the reading unit is used for reading the state of the BOOTSTS register in the FPGA through ICAPE 2;
the second judging unit is used for judging whether to load a Golden area code for the first power-on or load the Golden area code for a fallback operation according to the state of the BOOTSTS register;
the first reset unit is used for setting a DSP reset signal and keeping the DSP in a reset state;
the instruction generating unit is used for identifying the board position signals, reconfiguring a configuration register of the FPGA through ICAPE2 according to different board position signals, determining a jump address of the configuration register of the FPGA and generating an IPROG instruction;
the first upgrading unit is used for reloading the product function codes corresponding to the board position signals by the FPGA according to the IPROG instruction so as to complete the online upgrading of the FPGA configuration items;
the second reset unit is used for setting a DSP reset signal high and starting a DSP function;
and the second upgrading unit is used for uploading the version information of the FPGA running code and instructing the upper computer to carry out online upgrading of the FPGA configuration item again.
6. The FPGA configuration item online upgrade system of claim 5, wherein the FPGA performs online upgrade while keeping the FPGA running product function code unchanged.
7. The FPGA configuration item online upgrade system of claim 6, wherein the FPGA needs to monitor the configuration file during the process of executing online upgrade, and if the configuration file is abnormal, the FPGA closes the online upgrade function, and notifies the DSP to wait for sending a new online upgrade instruction.
8. The FPGA configuration item online upgrade system of claim 7, wherein the bin format configuration file is generated from a Golden region code and a number of product function codes.
9. An electronic device comprising a memory, a processor and a computer program stored on the memory and running on the processor, the processor executing the program to implement the steps of the FPGA configuration item online upgrade method according to any one of claims 1 to 4.
10. A computer-readable storage medium, storing a computer program, wherein the steps of the FPGA configuration item online upgrade method according to any one of claims 1 to 4 are implemented when the computer program is executed.
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MultiBoot and Fallback Using ICAP in UltraScale+ FPGAs;Guruprasad Kempahonnaiah;《https://www.eeweb.com/wp-content/uploads/articles-multiboot-and-fallback-using-icap-in-ultrascale-fpgas.pdf》;20170623;1-21 *
Xilinx 7 series FPGA multiboot技术的使用(转);limanjihe等;《https://www.bbsmax.com/A/l1dyMlB9de/》;20181208;1-5 *
一种FPGA的远程在线加载和更新系统设计;宋凯林等;《单片机与嵌入式系统应用》;20201001;7-10 *

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