CN117290286A

CN117290286A - Memory operation method, memory storage device and memory control circuit unit

Info

Publication number: CN117290286A
Application number: CN202311328232.5A
Authority: CN
Inventors: 许建平; 林纬; 陈思玮; 李安秦
Original assignee: Phison Electronics Corp
Current assignee: Phison Electronics Corp
Priority date: 2023-10-13
Filing date: 2023-10-13
Publication date: 2023-12-26

Abstract

The invention provides a memory operation method, a memory storage device and a memory control circuit unit. The method comprises the following steps: receiving first data from a host system; storing the first data to a first entity unit, which is mapped to a first logic unit; in the first operation mode, performing a target operation according to the first data and the second data stored in the second entity unit to obtain third data which is different from the first data; storing third data to a third entity unit, which is also mapped to the first logic unit; and transmitting the third data to the host system. Therefore, the operation efficiency of the host system can be improved.

Description

Memory operation method, memory storage device and memory control circuit unit

Technical Field

The present invention relates to a memory operation technology, and more particularly, to a memory operation method, a memory storage device and a memory control circuit unit.

Background

Portable electronic devices such as mobile phones and notebook computers have grown very rapidly over the years, and consumer demand for storage media has also increased rapidly. Since a rewritable non-volatile memory module (e.g., flash memory) has characteristics of non-volatility of data, power saving, small size, and no mechanical structure, it is very suitable for being built in the above-exemplified various portable electronic devices. In addition, the use of artificial intelligence models (or artificial intelligence chips) is becoming increasingly popular to provide functions such as image recognition or speech recognition.

However, although the operation speed of the artificial intelligence model is faster and faster, the actual operation performance of the artificial intelligence model may be reduced due to the need to wait for a large amount of data to be transferred between the artificial intelligence model and the rewritable nonvolatile memory module in the operation process, which results in poor user experience.

Disclosure of Invention

The invention provides a memory operation method, a memory storage device and a memory control circuit unit, which can improve the operation efficiency of a host system.

An exemplary embodiment of the present invention provides a memory operation method for a memory storage device, wherein the memory storage device includes a rewritable nonvolatile memory module including a plurality of physical units, and the memory operation method includes: receiving first data from a host system; storing the first data to a first entity unit of the plurality of entity units, wherein the first entity unit is mapped to a first logical unit; in a first operation mode, performing a target operation according to the first data and second data of a second entity unit stored in the plurality of entity units to obtain third data, wherein the third data is different from the first data; storing the third data to a third entity unit of the plurality of entity units, wherein the third entity unit is also mapped to the first logical unit; and transmitting the third data to the host system.

In an example embodiment of the present invention, the step of performing the target operation according to the first data and the second data of the second entity unit stored in the plurality of entity units to obtain the third data includes: in the target operation, updating target data into the third data according to the first data and the second data.

In an exemplary embodiment of the invention, the memory operation method further includes: receiving fourth data from the host system; and in the first operation mode, executing the target operation according to the fourth data and the third data stored in the third entity unit so as to update the target data into fifth data.

In an example embodiment of the invention, the second entity unit is also mapped to the first logic unit.

In an example embodiment of the present invention, the second entity unit is mapped to a second logic unit, the first logic unit is different from the second logic unit, and there is an association between the first logic unit and the second logic unit.

In an exemplary embodiment of the invention, the memory operation method further includes: recording first mapping information in a first mapping table, wherein the first mapping information reflects a mapping relationship between the first logic unit and the first entity unit; and recording second mapping information in a second mapping table, wherein the second mapping information reflects a mapping relationship between the first logic unit and the second entity unit, and the first mapping table is different from the second mapping table.

In an exemplary embodiment of the invention, the memory operation method further includes: and in response to the third data being stored in the third entity unit, updating the first mapping information recorded in the first mapping table, wherein the updated first mapping information reflects a mapping relationship between the first logic unit and the third entity unit.

In an exemplary embodiment of the invention, the memory operation method further includes: reading the third entity unit is prohibited until the target operation is completed to obtain the third data.

In an exemplary embodiment of the invention, the memory operation method further includes: receiving a start request from the host system; and starting the first operation mode according to the starting request.

In an exemplary embodiment of the invention, the memory operation method further includes: and determining whether to start the first operation mode according to the first logic unit to which the first data belong.

In an example embodiment of the invention, the target operation is used to assist an artificial intelligence model in the host system in performing data updates.

In an exemplary embodiment of the invention, the memory operation method further includes: receiving a write instruction from the host system, wherein the write instruction is to write the first data to the first logic unit; receiving a read instruction from the host system, wherein the read instruction is to read the first logic unit; and transmitting the third data to the host system in response to the read instruction.

In an exemplary embodiment of the invention, the memory operation method further includes: performing a handshake operation with the host system prior to performing the target operation; and in the handshake operation, performing an initialization setting related to the target operation.

In an example embodiment of the present invention, the handshake operation includes: receiving an interrogation instruction from the host system, wherein the interrogation instruction is used to confirm the memory storage device's ability to support assisted operations of an artificial intelligence model; and sending a reply message to the host system, wherein the reply message is used to illustrate the ability of the memory storage device to support the auxiliary operation of the artificial intelligence model.

The exemplary embodiments of the present invention further provide a memory storage device, which includes a connection interface unit, a rewritable nonvolatile memory module, and a memory control circuit unit. The connection interface unit is used for being connected to a host system. The rewritable nonvolatile memory module includes a plurality of physical units. The memory control circuit unit is connected to the connection interface unit and the rewritable nonvolatile memory module. The memory control circuit unit is used for: receiving first data from the host system; storing the first data to a first entity unit of the plurality of entity units, wherein the first entity unit is mapped to a first logical unit; in a first operation mode, performing a target operation according to the first data and second data of a second entity unit stored in the plurality of entity units to obtain third data, wherein the third data is different from the first data; storing the third data to a third entity unit of the plurality of entity units, wherein the third entity unit is also mapped to the first logical unit; and transmitting the third data to the host system.

In an example embodiment of the present invention, the operation of the memory control circuit unit performing the target operation according to the first data and the second data of the second entity unit stored in the plurality of entity units to obtain the third data includes: in the target operation, updating target data into the third data according to the first data and the second data.

In an example embodiment of the present invention, the memory control circuit unit is further configured to: receiving fourth data from the host system; and in the first operation mode, executing the target operation according to the fourth data and the third data stored in the third entity unit so as to update the target data into fifth data.

In an example embodiment of the present invention, the memory control circuit unit is further configured to: recording first mapping information in a first mapping table, wherein the first mapping information reflects a mapping relationship between the first logic unit and the first entity unit; and recording second mapping information in a second mapping table, wherein the second mapping information reflects a mapping relationship between the first logic unit and the second entity unit, and the first mapping table is different from the second mapping table.

In an example embodiment of the present invention, the memory control circuit unit is further configured to: and in response to the third data being stored in the third entity unit, updating the first mapping information recorded in the first mapping table, wherein the updated first mapping information reflects a mapping relationship between the first logic unit and the third entity unit.

In an example embodiment of the present invention, the memory control circuit unit is further configured to: reading the third entity unit is prohibited until the target operation is completed to obtain the third data.

In an example embodiment of the present invention, the memory control circuit unit is further configured to: receiving a start request from the host system; and starting the first operation mode according to the starting request.

In an example embodiment of the present invention, the memory control circuit unit is further configured to: and determining whether to start the first operation mode according to the first logic unit to which the first data belong.

In an example embodiment of the present invention, the memory control circuit unit is further configured to: receiving a write instruction from the host system, wherein the write instruction is to write the first data to the first logic unit; receiving a read instruction from the host system, wherein the read instruction is to read the first logic unit; and transmitting the third data to the host system in response to the read instruction.

In an example embodiment of the present invention, the memory control circuit unit is further configured to: performing a handshake operation with the host system prior to performing the target operation; and in the handshake operation, performing an initialization setting related to the target operation.

The exemplary embodiments of the present invention further provide a memory control circuit unit for controlling a rewritable nonvolatile memory module, wherein the rewritable nonvolatile memory module comprises a plurality of physical units. The memory control circuit unit comprises a host interface, a memory interface and a memory management circuit. The host interface is configured to connect to a host system. The memory interface is configured to connect to the rewritable non-volatile memory module. The memory management circuit is connected to the host interface and the memory interface. The memory management circuit is to: receiving first data from the host system; storing the first data to a first entity unit of the plurality of entity units, wherein the first entity unit is mapped to a first logical unit; in a first operation mode, performing a target operation according to the first data and second data of a second entity unit stored in the plurality of entity units to obtain third data, wherein the third data is different from the first data; storing the third data to a third entity unit of the plurality of entity units, wherein the third entity unit is also mapped to the first logical unit; and transmitting the third data to the host system.

In an example embodiment of the present invention, the operation of the memory management circuit to perform the target operation according to the first data and the second data of the second entity unit stored in the plurality of entity units to obtain the third data includes: in the target operation, updating target data into the third data according to the first data and the second data.

In an example embodiment of the invention, the memory management circuit is further to: receiving fourth data from the host system; and in the first operation mode, executing the target operation according to the fourth data and the third data stored in the third entity unit so as to update the target data into fifth data.

In an example embodiment of the invention, the memory management circuit is further to: recording first mapping information in a first mapping table, wherein the first mapping information reflects a mapping relationship between the first logic unit and the first entity unit; and recording second mapping information in a second mapping table, wherein the second mapping information reflects a mapping relationship between the first logic unit and the second entity unit, and the first mapping table is different from the second mapping table.

In an example embodiment of the invention, the memory management circuit is further to: and in response to the third data being stored in the third entity unit, updating the first mapping information recorded in the first mapping table, wherein the updated first mapping information reflects a mapping relationship between the first logic unit and the third entity unit.

In an example embodiment of the invention, the memory management circuit is further to: reading the third entity unit is prohibited until the target operation is completed to obtain the third data.

In an example embodiment of the invention, the memory management circuit is further to: receiving a start request from the host system; and starting the first operation mode according to the starting request.

In an example embodiment of the invention, the memory management circuit is further to: and determining whether to start the first operation mode according to the first logic unit to which the first data belong.

In an example embodiment of the invention, the memory management circuit is further to: receiving a write instruction from the host system, wherein the write instruction is to write the first data to the first logic unit; receiving a read instruction from the host system, wherein the read instruction is to read the first logic unit; and transmitting the third data to the host system in response to the read instruction.

In an example embodiment of the invention, the memory management circuit is further to: performing a handshake operation with the host system prior to performing the target operation; and in the handshake operation, performing an initialization setting related to the target operation.

Based on the above, in the first operation mode of the memory storage device, the memory storage device may perform a target operation according to the first data from the host system and the second data stored in the rewritable non-volatile memory module and transmit the third data generated by the operation to the host system. Therefore, the operation efficiency of the host system can be improved.

Drawings

FIG. 1 is a schematic diagram of a host system, a memory storage device, and an input/output (I/O) device, according to an example embodiment of the invention;

FIG. 2 is a schematic diagram of a host system, a memory storage device, and an I/O device according to an example embodiment of the invention;

FIG. 3 is a schematic diagram of a host system and a memory storage device according to an example embodiment of the invention;

FIG. 4 is a schematic diagram of a memory storage device according to an example embodiment of the invention;

FIG. 5 is a schematic diagram of a memory control circuit unit shown according to an example embodiment of the invention;

FIG. 6 is a schematic diagram illustrating managing a rewritable non-volatile memory module according to an example embodiment of the present invention;

FIG. 7 is a schematic diagram illustrating a host system exchanging data with a memory storage device according to an example embodiment of the present invention;

FIGS. 8A and 8B are diagrams illustrating a memory storage device performing a target operation and exchanging data with a host system according to an example embodiment of the invention;

FIGS. 9A-9D are diagrams illustrating a memory storage device performing a target operation and exchanging data with a host system according to an example embodiment of the invention;

FIG. 10 is a diagram illustrating recording and updating mapping information according to an exemplary embodiment of the present invention;

fig. 11 is a flowchart of a memory operation method according to an exemplary embodiment of the present invention.

Detailed Description

Reference will now be made in detail to the exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings and the description to refer to the same or like parts.

Generally, a memory storage device (also referred to as a memory storage system) includes a rewritable nonvolatile memory module (rewritable non-volatile memory module) and a controller (also referred to as a control circuit). The memory storage device may be used with a host system such that the host system may write data to or read data from the memory storage device.

FIG. 1 is a schematic diagram of a host system, a memory storage device, and an input/output (I/O) device according to an example embodiment of the invention. FIG. 2 is a schematic diagram of a host system, a memory storage device, and an I/O device according to an example embodiment of the invention.

Referring to fig. 1 and 2, the host system 11 may include a processor 111, a random access memory (random access memory, RAM) 112, a Read Only Memory (ROM) 113, and a data transfer interface 114. The processor 111, the random access memory 112, the read only memory 113, and the data transfer interface 114 may be connected to a system bus 110.

In an example embodiment, host system 11 may be coupled to memory storage device 10 via data transfer interface 114. For example, host system 11 may store data to memory storage device 10 or read data from memory storage device 10 through data transfer interface 114. In addition, host system 11 may be connected to I/O device 12 via system bus 110. For example, host system 11 may transmit output signals to I/O device 12 or receive input signals from I/O device 12 via system bus 110.

In an exemplary embodiment, the processor 111, the ram 112, the rom 113, and the data transfer interface 114 may be disposed on the motherboard 20 of the host system 11. The number of data transfer interfaces 114 may be one or more. The motherboard 20 may be connected to the memory storage device 10 by a wired or wireless connection through the data transmission interface 114.

In an example embodiment, the memory storage device 10 may be, for example, a usb flash disk 201, a memory card 202, a solid state disk (Solid State Drive, SSD) 203, or a wireless memory storage device 204. The wireless memory storage 204 may be, for example, a near field communication (Near Field Communication, NFC) memory storage, a wireless facsimile (WiFi) memory storage, a Bluetooth (Bluetooth) memory storage, or a Bluetooth low energy memory storage (such as iBeacon) or the like based on a wide variety of wireless communication technologies. In addition, the motherboard 20 may also be connected to various I/O devices such as a global positioning system (Global Positioning System, GPS) module 205, a network interface card 206, a wireless transmission device 207, a keyboard 208, a screen 209, and a speaker 210 through the system bus 110. For example, in an exemplary embodiment, the motherboard 20 may access the wireless memory storage device 204 through the wireless transmission device 207.

In an example embodiment, host system 11 is a computer system. In an example embodiment, host system 11 may be any system that may substantially cooperate with a memory storage device to store data. In an example embodiment, the memory storage device 10 and the host system 11 may include the memory storage device 30 and the host system 31 of fig. 3, respectively.

FIG. 3 is a schematic diagram of a host system and a memory storage device according to an example embodiment of the invention. Referring to fig. 3, the memory storage device 30 may be used with the host system 31 to store data. For example, the host system 31 may be a system such as a digital camera, video camera, communication device, audio player, video player, or tablet computer. For example, the memory storage device 30 may be a Secure Digital (SD) card 32, a Compact Flash (CF) card 33, or an embedded memory device 34 used by a host system 31. The embedded storage device 34 includes embedded storage devices of various types such as an embedded multimedia card (embedded Multi Media Card, eMMC) 341 and/or an embedded multi-chip package (embedded Multi Chip Package, eMCP) storage device 342 that directly connect the memory module to a substrate of the host system.

Fig. 4 is a schematic diagram of a memory storage device according to an example embodiment of the invention. Referring to fig. 4, the memory storage device 10 includes a connection interface unit 41, a memory control circuit unit 42, and a rewritable nonvolatile memory module 43.

The connection interface unit 41 is used to connect the memory storage device 10 to the host system 11. The memory storage device 10 may communicate with the host system 11 through the connection interface unit 41. In an exemplary embodiment, the connection interface unit 41 is compatible with the high speed peripheral component interconnect (Peripheral Component Interconnect Express, PCI Express) standard. However, it should be understood that the present invention is not limited thereto, and the connection interface unit 41 may be a serial advanced technology attachment (Serial Advanced Technology Attachment, SATA) compliant standard, a parallel advanced technology attachment (Parallel Advanced Technology Attachment, PATA) standard, an institute of electrical and electronics engineers (Institute of Electrical and Electronic Engineers, IEEE) 1394 standard, a universal serial bus (Universal Serial Bus, USB) standard, an SD interface standard, a Ultra High Speed-I (UHS-I) interface standard, a Ultra High Speed-II (UHS-II) interface standard, a Memory Stick (MS) interface standard, an MCP interface standard, an MMC interface standard, an eMMC interface standard, a universal flash Memory (Universal Flash Storage, UFS) interface standard, an eMCP interface standard, a CF interface standard, an integrated drive electronics interface (Integrated Device Electronics, IDE) standard, or other suitable standard. The connection interface unit 41 may be packaged in one chip with the memory control circuit unit 42, or the connection interface unit 41 may be disposed outside a chip including the memory control circuit unit 42.

The memory control circuit unit 42 is connected to the connection interface unit 41 and the rewritable nonvolatile memory module 43. The memory control circuit unit 42 is used for executing a plurality of logic gates or control instructions implemented in hardware or firmware and performing operations of writing, reading and erasing data in the rewritable nonvolatile memory module 43 according to the instructions of the host system 11.

The rewritable nonvolatile memory module 43 is used for storing data written by the host system 11. The rewritable nonvolatile memory module 43 may include a single-Level memory Cell (Single Level Cell, SLC) NAND type flash memory module (i.e., a flash memory module that can store 1 bit in one memory Cell), a second-Level memory Cell (MLC) NAND type flash memory module (i.e., a flash memory module that can store 2 bits in one memory Cell), a third-Level memory Cell (Triple Level Cell, TLC) NAND type flash memory module (i.e., a flash memory module that can store 3 bits in one memory Cell), a fourth-Level memory Cell (QLC) NAND type flash memory module (i.e., a flash memory module that can store 4 bits in one memory Cell), other flash memory modules, or other memory modules having the same characteristics.

Each memory cell in the rewritable nonvolatile memory module 43 stores one or more bits with a change in voltage (hereinafter also referred to as a threshold voltage). Specifically, there is a charge trapping layer between the control gate (control gate) and the channel of each memory cell. By applying a write voltage to the control gate, the amount of electrons in the charge trapping layer can be changed, thereby changing the threshold voltage of the memory cell. This operation of changing the threshold voltage of the memory cell is also referred to as "writing data to the memory cell" or "programming" the memory cell. As the threshold voltage changes, each memory cell in the rewritable nonvolatile memory module 43 has a plurality of memory states. By applying a read voltage, it is possible to determine which memory state a memory cell belongs to, and thereby obtain one or more bits stored in the memory cell.

In an exemplary embodiment, the memory cells of the rewritable nonvolatile memory module 43 may constitute a plurality of physical program units, and the physical program units may constitute a plurality of physical erase units. Specifically, memory cells on the same word line may constitute one or more physical programming units. If each memory cell can store more than 2 bits, the physical programming units on the same word line can be categorized into at least a lower physical programming unit and an upper physical programming unit. For example, the least significant bit (Least Significant Bit, LSB) of a memory cell is that belonging to the lower physical programming cell, and the most significant bit (Most Significant Bit, MSB) of a memory cell is that belonging to the upper physical programming cell. In general, in MLC NAND-type flash memory, the writing speed of the lower physical programming unit is greater than the writing speed of the upper physical programming unit, and/or the reliability of the lower physical programming unit is higher than the reliability of the upper physical programming unit.

In an exemplary embodiment, the physical programming unit is a minimum unit of programming. That is, the physical programming unit is the smallest unit of write data. For example, the physical programming unit may be a physical page (page) or a physical sector (sector). If the physical programming units are physical pages, the physical programming units may include data bits and redundancy bits. The data bit area includes a plurality of physical sectors for storing user data, and the redundant bit area is used for storing system data (e.g., management data such as error correction codes). In an exemplary embodiment, the data bit area includes 32 physical sectors, and a physical sector has a size of 512 bytes (B). However, in other exemplary embodiments, 8, 16 or a greater or lesser number of physical fans may be included in the data bit zone, and the size of each physical fan may be greater or lesser. On the other hand, a physical erase unit is the minimum unit of erase. That is, each physically erased cell contains a minimum number of memory cells that are erased together. For example, the physical erased cells are physical blocks (blocks).

Fig. 5 is a schematic diagram of a memory control circuit unit according to an example embodiment of the invention. Referring to fig. 5, the memory control circuit unit 42 includes a memory management circuit 51, a host interface 52 and a memory interface 53.

The memory management circuit 51 is used for controlling the overall operation of the memory control circuit unit 42. Specifically, the memory management circuit 51 has a plurality of control commands, and when the memory storage device 10 is operated, the control commands are executed to perform operations such as writing, reading and erasing data. The operation of the memory management circuit 51 is explained as follows, which is equivalent to the explanation of the operation of the memory control circuit unit 42.

In an example embodiment, the control instructions of the memory management circuit 51 are implemented in firmware. For example, the memory management circuit 51 has a microprocessor unit (not shown) and a read-only memory (not shown), and the control instructions are burned into the read-only memory. When the memory storage device 10 is in operation, the control instructions are executed by the microprocessor unit to perform operations such as writing, reading and erasing data.

In an exemplary embodiment, the control instructions of the memory management circuit 51 may also be stored in a program code format in a specific area of the rewritable nonvolatile memory module 43 (e.g., a system area dedicated to storing system data in the memory module). In addition, the memory management circuit 51 has a microprocessor unit (not shown), a read only memory (not shown), and a random access memory (not shown). In particular, the rom has a boot code (boot code), and when the memory control circuit unit 42 is enabled, the microprocessor unit executes the boot code to load the control instructions stored in the rewritable nonvolatile memory module 43 into the ram of the memory management circuit 51. Then, the microprocessor unit operates the control instructions to perform operations such as writing, reading and erasing of data.

In an exemplary embodiment, the control instructions of the memory management circuit 51 may also be implemented in a hardware type. For example, the memory management circuit 51 includes a microcontroller, a memory cell management circuit, a memory write circuit, a memory read circuit, a memory erase circuit, and a data processing circuit. The memory cell management circuit, the memory write circuit, the memory read circuit, the memory erase circuit and the data processing circuit are connected to the microcontroller. The memory cell management circuit is used to manage the memory cells or groups of memory cells of the rewritable nonvolatile memory module 43. The memory write circuit is used for issuing a write instruction sequence to the rewritable nonvolatile memory module 43 to write data into the rewritable nonvolatile memory module 43. The memory read circuit is used for issuing a read instruction sequence to the rewritable nonvolatile memory module 43 to read data from the rewritable nonvolatile memory module 43. The memory erase circuit is used for issuing an erase command sequence to the rewritable nonvolatile memory module 43 to erase data from the rewritable nonvolatile memory module 43. The data processing circuit is used for processing data to be written into the rewritable nonvolatile memory module 43 and data read from the rewritable nonvolatile memory module 43. The write command sequence, the read command sequence, and the erase command sequence may each include one or more program codes or command codes and are used to instruct the rewritable nonvolatile memory module 43 to perform corresponding writing, reading, and erasing operations. In an example embodiment, the memory management circuit 51 may also issue other types of instruction sequences to the rewritable nonvolatile memory module 43 to instruct the corresponding operations to be performed.

The host interface 52 is connected to the memory management circuit 51. Memory management circuitry 51 may communicate with host system 11 through host interface 52. The host interface 52 is used to receive and identify the commands and data transmitted by the host system 11. For example, instructions and data transmitted by host system 11 may be transmitted to memory management circuit 51 via host interface 52. In addition, the memory management circuitry 51 may communicate data to the host system 11 through the host interface 52. In the present example embodiment, host interface 52 is compatible with the PCI Express standard. However, it should be understood that the present invention is not limited thereto, and the host interface 52 may also be compatible with SATA standards, PATA standards, IEEE 1394 standards, USB standards, SD standards, UHS-I standards, UHS-II standards, MS standards, MMC standards, eMMC standards, UFS standards, CF standards, IDE standards, or other suitable data transfer standards.

The memory interface 53 is connected to the memory management circuit 51 and is used to access the rewritable nonvolatile memory module 43. For example, the memory management circuit 51 may access the rewritable nonvolatile memory module 43 through the memory interface 53. That is, the data to be written into the rewritable nonvolatile memory module 43 is converted into a format acceptable to the rewritable nonvolatile memory module 43 through the memory interface 53. Specifically, if the memory management circuit 51 is to access the rewritable nonvolatile memory module 43, the memory interface 53 transmits the corresponding instruction sequence. For example, the instruction sequences may include a write instruction sequence that indicates write data, a read instruction sequence that indicates read data, an erase instruction sequence that indicates erase data, and corresponding instruction sequences to indicate various memory operations (e.g., changing read voltage levels or performing garbage collection (Garbage Collection, GC) operations, etc.). These sequences of instructions are, for example, generated by the memory management circuit 51 and transferred to the rewritable non-volatile memory module 43 via the memory interface 53. These instruction sequences may include one or more signals, or data, on a bus. Such signals or data may include instruction code or program code. For example, the read instruction sequence may include information such as a read identification code and a memory address.

In an exemplary embodiment, the memory control circuit unit 42 further includes an error checking and correction circuit 54, a buffer memory 55, and a power management circuit 56.

The error checking and correcting circuit 54 is connected to the memory management circuit 51 and is used for performing error checking and correcting operations to ensure the correctness of the data. Specifically, when the memory management circuit 51 receives a write command from the host system 11, the error checking and correcting circuit 54 generates a corresponding error correction code (error correcting code, ECC) and/or error checking code (error detecting code, EDC) for the data corresponding to the write command, and the memory management circuit 51 writes the data corresponding to the write command and the corresponding error correction code and/or error checking code into the rewritable nonvolatile memory module 43. Then, when the memory management circuit 51 reads data from the rewritable nonvolatile memory module 43, the error correction code and/or the error check code corresponding to the data are read at the same time, and the error check and correction circuit 54 performs an error check and correction operation on the read data according to the error correction code and/or the error check code.

The buffer memory 55 is connected to the memory management circuit 51 and is used for temporarily storing data. The power management circuit 56 is connected to the memory management circuit 51 and is used to control the power of the memory storage device 10.

In an example embodiment, the rewritable non-volatile memory module 43 of fig. 4 may include a flash memory module. In an example embodiment, the memory control circuit unit 42 of fig. 4 may include a flash memory controller. In an example embodiment, the memory management circuit 51 of fig. 5 may include a flash memory management circuit.

FIG. 6 is a schematic diagram illustrating managing a rewritable non-volatile memory module according to an example embodiment of the present invention. Referring to FIG. 6, the memory management circuit 51 can logically group the physical units 610 (0) -610 (B) in the rewritable nonvolatile memory module 43 into a memory area 601 and a spare (spare) area 602.

In an exemplary embodiment, a physical unit refers to a physical address or a physical programming unit. In an exemplary embodiment, a physical unit may also be composed of a plurality of consecutive or non-consecutive physical addresses. In an exemplary embodiment, a physical unit may also be referred to as a Virtual Block (VB). A virtual block may include multiple physical addresses or multiple physical programming units. In an example embodiment, a dummy block may include one or more physical erase units.

The entity units 610 (0) -610 (a) in the storage area 601 are used to store user data (e.g., user data from the host system 11 of fig. 1). For example, the entity units 610 (0) to 610 (a) in the storage area 601 may store valid (valid) data and invalid (invalid) data. The physical units 610 (a+1) -610 (B) in the free area 602 do not store data (e.g., valid data). For example, if a physical unit does not store valid data, the physical unit may be associated (or added) to the idle area 602. In addition, the physical cells in the free area 602 (or the physical cells that do not store valid data) may be erased. When writing new data, one or more physical units may be extracted from the spare area 602 to store the new data. In an exemplary embodiment, the free area 602 is also referred to as a free pool (free pool).

The memory management circuit 51 may configure the logic units 612 (0) through 612 (C) to map the physical units 610 (0) through 610 (A) in the memory area 601. In an exemplary embodiment, each logical unit corresponds to a logical address. For example, a logical address may include one or more logical block addresses (Logical Block Address, LBAs) or other logical management units. In an exemplary embodiment, a logic unit may also correspond to a logic programming unit or be composed of a plurality of consecutive or non-consecutive logic addresses.

It should be noted that a logical unit may be mapped to one or more physical units. If a certain entity unit is currently mapped by a certain logic unit, the data currently stored in the entity unit includes valid data. Otherwise, if a certain entity unit is not mapped by any logic unit, the data stored in the entity unit is invalid.

The memory management circuit 51 may record management data (also referred to as logic-to-entity mapping information) describing a mapping relationship between the logic units and the entity units in at least one logic-to-entity mapping table. When the host system 11 wants to read data from the memory storage device 10 or write data to the memory storage device 10, the memory management circuit 51 can access the rewritable nonvolatile memory module 43 according to the information in the logical-to-physical mapping table.

FIG. 7 is a schematic diagram illustrating a host system exchanging data with a memory storage device according to an example embodiment of the present invention. Referring to FIG. 7, in an example embodiment, host system 11 may run one or more artificial intelligence (artificial intelligence, AI) models 71. For example, artificial intelligence model 71 may be run by processor 111 of host system 11. For example, the processor 111 may include a central processing unit (Central Processing Unit, CPU), a graphics processor (Graphics Processing Unit, GPU), or other programmable general purpose or special purpose microprocessor, digital signal processor (Digital Signal Processor, DSP), programmable controller, application specific integrated circuit (Application Specific Integrated Circuits, ASIC), programmable logic device (Programmable Logic Device, PLD), or other similar device or combination of devices. In the following exemplary embodiments, the operations performed by the host system 11 may be considered to be performed by the processor 111 alone or by the processor 111 in combination with other electronic circuits in the host system 11.

In an example embodiment, the artificial intelligence model 71 may include a machine learning (machine learning) model, a deep learning (deep learning) model, and/or other computer computing engines. The artificial intelligence model may employ neural network architectures or artificial neural networks (Artificial Neural Network, ANN) such as deep neural networks (Deep Neural Networks, DNN), recurrent neural networks (Recurrent Neural Network, RNN), and/or convolutional neural networks (Convolutional Neural Network, CNN). The processor 111 may perform various automation functions such as image recognition, voice recognition, or natural language processing (Natural language processing, NLP) through the artificial intelligence model 71, and the automation functions that the artificial intelligence model 71 may support are not limited thereto. Furthermore, artificial intelligence model 71 may be implemented as software, hardware, and/or firmware, and the invention is not limited.

In an example embodiment, the memory management circuit 51 may receive data (also referred to as first data) 701 from the host system 11 through the host interface 52. The data 701 belongs to a particular logical unit (also referred to as a first logical unit). For example, the first logic unit may include one of logic units 612 (0) -612 (C) in fig. 6. The memory management circuit 51 may store the data 701 to a specific physical unit (also referred to as a first physical unit) in the rewritable nonvolatile memory module 43. For example, the first entity unit may be one of entity units 610 (a+1) to 610 (B) in fig. 6. The first physical unit is mapped to the first logical unit.

In an exemplary embodiment, in a specific operation mode (also referred to as a first operation mode) of the memory storage device 10, the memory management circuit 51 may perform an operation (also referred to as a target operation) according to the data 701 and the data (also referred to as a second data) stored in a specific physical unit (also referred to as a second physical unit) in the rewritable nonvolatile memory module 43 to obtain the data (also referred to as a third data) 702. The data 702 is different from the data 701. That is, the content of data 702 is different from the content of data 701. The memory management circuit 51 may then store the data 702 to a specific physical unit (also referred to as a third physical unit) in the rewritable nonvolatile memory module 43. For example, the third entity may be another one of entity units 610 (A+1) -610 (B) in FIG. 6. The third physical unit is also mapped to the first logical unit. Further, after obtaining the data 703, the memory management circuitry 51 may communicate the data 703 to the host system 11 via the host interface 52.

In an example embodiment, the target operation is to assist the artificial intelligence model 71 in the host system 11 in performing data updates. For example, the data update includes updating parameters such as weights or vector function values used by the artificial intelligence model 71 during the operation. Taking fig. 7 as an example, in the target operation, the memory management circuit 51 may update specific data (also referred to as target data) to third data (such as data 702) according to the first data (such as data 701) and the second data.

In an example embodiment, the memory management circuit 51 may perform the target operation through the operation model 72. The operational model 72 is installed in the memory storage device 10. For example, the memory management circuit 51 may run the operational model 72 to update the target data to the third data (e.g., data 702) based on the first data (e.g., data 701) and the second data. Furthermore, the operational model 72 may be implemented as software, hardware, and/or firmware, as the invention is not limited.

In an example embodiment, the operational model 72 may be used to replace one or more operational models that were originally provided in the host system 11 (or the artificial intelligence model 71) and used to perform the target operation. In an example embodiment, installing the operational model 72 in the memory storage device 10 to perform the target operation is equivalent to migrating at least one target operation that is preset to be responsible for by the host system 11 (or the artificial intelligence model 71) into the memory storage device 10 and performing the target operation by the memory storage device 10. Thus, the amount of data transfer between the host system 11 and the memory storage device 10 can be reduced in the course of the artificial intelligence model 71 performing data update.

Conventionally, during the time that the artificial intelligence model 71 performs data update, the host system 11 reads a large amount of data (including the second data) required for the operation from the memory storage device 10, thereby resulting in a decrease in the actual operation performance of the artificial intelligence model 71 (influenced by the bandwidth of the data transmission). Thus, regardless of how fast the artificial intelligence model 71 or the processor 111 itself operates, the actual operational performance of the artificial intelligence model 71 may be reduced by waiting for a significant amount of data transfer between the host system 11 and the memory storage device 10, thereby reducing the operational performance of the host system 11 (or the artificial intelligence model 71) and/or affecting the user experience.

In an example embodiment, by transmitting a small portion of data (e.g., data 701) to be processed by a target operation to the memory storage device 10 and receiving the operation result (e.g., data 702) of the memory storage device 10 for the target operation, the host system 11 may at least not perform an operation of reading the second data from the memory storage device 10 (i.e., skip the operation of reading the second data from the memory storage device 10). Therefore, the data transmission amount between the host system 11 and the memory storage device 10 during the data update of the artificial intelligence model 71 can be effectively reduced, so that the actual operation performance of the artificial intelligence model 71 is more close to the optimal or preset operation performance.

Fig. 8A and 8B are schematic diagrams illustrating a memory storage device performing a target operation and exchanging data with a host system according to an exemplary embodiment of the invention. Referring to fig. 8A, it is assumed that the communication processing unit 81 is further installed in the host system 11. For example, the communication processing unit 81 may include a driver (driver) or an application program. The communication processing unit 81 may be configured to perform data exchange between the host system 11 and the memory storage device 10 related to the target operation.

In an exemplary embodiment, the communication processing unit 81 may transmit the data 810 (i.e., the first data) to the memory storage device 10. For example, data 810 includes data A provided by artificial intelligence model 71. Data a belongs to the first logical unit. The memory management circuit 51 may receive data 810 from the host system 11 through the host interface 52 and store data a to the entity unit 801 (i.e., the first entity unit) in the rewritable non-volatile memory module 43.

In the first mode of operation, the memory management circuit 51 may read data A from the physical unit 801 and data B-D (i.e., second data) from the physical units 802-804 (i.e., second physical units) in the rewritable nonvolatile memory module 43, respectively. Then, the memory management circuit 51 may run the operation module 72 to perform the target operation according to the data a (i.e., the first data) and the data B to D (i.e., the second data) to obtain the data a' (i.e., the third data) in fig. 8B. For example, in a target operation, the memory management circuit 51 may update the data 82 (i.e., target data) from data a to data a' through the operation module 72. In the target operation, the memory management circuit 51 may update the data B to D to the data B 'to D' in fig. 8B based on the data a to D, respectively.

Referring to fig. 8B, in an exemplary embodiment, after generating the data a '(i.e., the third data), the memory management circuit 51 may store the data a' to the physical units 811 (i.e., the third physical units) in the rewritable nonvolatile memory module 43 and the data B 'to D' to the physical units 812 to 814 in the rewritable nonvolatile memory module 43, respectively. Then, the memory management circuit 51 may read the data a 'from the entity unit 811 and transfer the data 820 including the data a' to the host system 11. On the other hand, after receiving the data 820, the communication processing unit 81 may provide the data a' in the data 820 to the artificial intelligence model 71 for the artificial intelligence model 71 to perform corresponding data update.

In an example embodiment, after transferring the third data to the host system 11, the memory management circuit 51 may receive another data (also referred to as fourth data) from the host system 11. The memory management circuit 51 may store the fourth data to a specific physical unit (also referred to as a fourth physical unit) in the rewritable nonvolatile memory module 43. For example, the fourth entity unit may be one of entity units 610 (a+1) to 610 (B) in fig. 6. The fourth physical unit is also mapped to the first logical unit. Then, in the first operation mode, the memory management circuit 51 may perform a target operation according to the fourth data and the third data stored in the third entity unit to further update the target data to another data (also referred to as a fifth data). For example, in the target operation, the memory management circuit 51 may update the target data to the fifth data according to the fourth data, the previously generated third data and at least part of the second data. The memory management circuit 51 may then transfer the fifth data to the host system 11.

Fig. 9A to 9D are schematic diagrams illustrating a memory storage device performing a target operation and exchanging data with a host system according to an exemplary embodiment of the present invention. Referring to fig. 9A, in an exemplary embodiment, the communication processing unit 81 in the host system 11 may transmit the data 910 (i.e., the first data) to the memory storage device 10. For example, data 910 includes data A and B provided by artificial intelligence model 71. Data A and B both belong to the first logic unit. The memory management circuit 51 may receive data 910 from the host system 11 through the host interface 52 and store data a and B to the entity units 901 and 902 (i.e., the first entity unit) in the rewritable nonvolatile memory module 43, respectively.

In the first operation mode, the memory management circuit 51 may read data a and B from the entity units 901 and 902, respectively. In addition, the memory management circuit 51 can read the data C and D (i.e. the second data) from the entity units 903 and 904 (i.e. the second entity unit) in the rewritable nonvolatile memory module 43, respectively. Then, the memory management circuit 51 may run the operation module 72 to perform the target operation according to the data a and B (i.e. the first data) and the data C and D (i.e. the second data) to obtain the data a' (i.e. the third data) in fig. 9B. For example, in a target operation, the memory management circuit 51 may update the data 82 (i.e., target data) from data a to data a' through the operation module 72. In the target operation, the memory management circuit 51 may update the data B to D to the data B 'to D' in fig. 9B based on the data a to D, respectively.

Referring to fig. 9B, in an exemplary embodiment, after generating the data a '(i.e., the third data), the memory management circuit 51 may store the data a' to the physical units 911 (i.e., the third physical units) in the rewritable nonvolatile memory module 43 and the data B 'to D' to the physical units 912 to 914 in the rewritable nonvolatile memory module 43, respectively. The memory management circuit 51 may then read the data a 'from the entity unit 911 and transmit the data 920 containing the data a' to the host system 11.

On the other hand, after receiving the data 920, the communication processing unit 81 may provide the data a' in the data 920 to the artificial intelligence model 71 for the artificial intelligence model 71 to perform corresponding data update. For example, after the artificial intelligence model 71 obtains the data A ', the artificial intelligence model 71 may update the data 91 according to the data A'. For example, data 91 includes data B. The artificial intelligence model 71 may update the data 91 from data B to data E in fig. 9C according to data a'.

Referring to fig. 9C, in succession to fig. 9B, in an exemplary embodiment, after obtaining the data E, the communication processing unit 81 may transmit the data (i.e. the fourth data) 930 to the memory storage device 10. For example, data 930 includes data E provided by artificial intelligence model 71. Data E also belongs to the first logical unit. The memory management circuit 51 may receive data 930 from the host system 11 through the host interface 52 and store data E to the entity 922 (i.e., the fourth entity) in the rewritable non-volatile memory module 43.

In the first mode of operation, the memory management circuit 51 may read data A ', E, C ' and D ' from the physical units 911, 922, 913 and 914, respectively. The memory management circuit 51 may then run the operation module 72 to perform the target operation according to the data a ', E, C ' and D ' to obtain the data a "(i.e., the fifth data) in fig. 9D. For example, in a target operation, the memory management circuit 51 may update the data 82 (i.e., target data) from data a 'to data a' via the operation module 72. In addition, in the target operation, the memory management circuit 51 may update the data E, C 'and D' to the data E ', C "and D" according to the data a', E, C 'and D', respectively.

Referring to FIG. 9D, in an exemplary embodiment, after generating the data A "(i.e. the fifth data), the memory management circuit 51 may store the data A", E', C ", and D" to the physical units 931 to 934 in the rewritable nonvolatile memory module 43, respectively. Then, the memory management circuit 51 may read the data a″ from the entity unit 931 and transmit the data 940 including the data a″ to the host system 11.

Upon receiving the data 940, the communication processing unit 81 may provide the data a″ in the data 940 to the artificial intelligence model 71 for the artificial intelligence model 71 to perform a corresponding data update. For example, after the artificial intelligence model 71 obtains the data a ", the artificial intelligence model 71 may update the data 91 again according to the data a", for example, update the data 91 from the data E to another data, which is not repeated here.

In an exemplary embodiment, by migrating the operation module 72 for performing the target operation into the memory storage device 10 and transferring only a portion of the data (e.g., the data 810 and 820 in fig. 8A and 8B and/or the data 910-940 in fig. 9A-9D) required for the artificial intelligence model 71 to perform the data update between the host system 11 and the memory storage device 10, the amount of data transferred between the host system 11 and the memory storage device 10 during the data update performed by the artificial intelligence model 71 can be effectively reduced. Thus, the operation performance of the host system 11 (or the artificial intelligence model 71) can be effectively improved.

In an exemplary embodiment, the memory management circuit 51 may record a plurality of mapping information in a plurality of management tables, respectively. For example, the first mapping information is recorded in the first management table, and the second mapping information is recorded in the second management table. The first mapping information may reflect a mapping relationship between the first logical unit and the first physical unit. The second mapping information may reflect a mapping relationship between the first logical unit and the second physical unit. In a first mode of operation, the memory management circuitry 51 may read or store data related to a target operation according to such management tables.

Fig. 10 is a diagram illustrating recording and updating of mapping information according to an exemplary embodiment of the present invention. Referring to fig. 8A, 8B and 10, in an exemplary embodiment, it is assumed that at least part of the data required for performing the target operation belongs to the logic unit 1001 (i.e. the first logic unit). The memory management circuit 51 may query the management tables 1011-1014 according to the logic unit 1001 to obtain mapping information 1021-1024, respectively. Different management tables may be used to manage different stages or functions of operation.

Taking fig. 8A as an example, mapping information 1021 to 1024 may reflect the mapping relationship between the logical unit 1001 and the physical units 801 to 804, respectively. The memory management circuit 51 may query the management tables 1011-1014 according to the logic unit 1001 to obtain mapping information 1021-1024, respectively. Based on the mapping information 1021-1024, the memory management circuit 51 can read the data A-D from the physical units 801-804, respectively. For example, data A-D all belong to logical unit 1001.

Taking fig. 8B as an example, the memory management circuit 51 may update the mapping information 1021-1024 in response to storing the data a 'to D' to the entity units 811-814, respectively. For example, the updated mapping information 1021-1024 may reflect the mapping relationship between the logical unit 1001 and the physical units 811-814, respectively. The updated mapping information 1021 through 1024 may be recorded again in the management tables 1011 through 1014.

It should be noted that in the exemplary embodiment of fig. 10, the mapping of the logic unit 1001 to the entity units 801-804 (or 811-814) is taken as an example. However, in an example embodiment, logical unit 1001 may be mapped to physical unit 801 (or 811), and at least one logical unit (also referred to as a second logical unit) may be mapped to physical units 802-804 (or 812-814). The first logic unit is different from the second logic unit. For example, the second logic unit may include another one of logic units 612 (0) -612 (C) in FIG. 6. There may be an association (e.g., a mapping relationship) between the first logical unit and the second logical unit.

Taking fig. 10 as an example, in an exemplary embodiment, mapping information 1021 may respectively reflect the mapping relationship between a first logical unit (i.e., logical unit 1001) and physical units 801 (or 811), and mapping information 1022-1024 may respectively reflect the mapping relationship between one or more second logical units and physical units 802-804 (or 812-814). Before querying the management tables 1012-1014, the memory management circuit 51 may determine the second logical unit based on the first logical unit and the association between the first logical unit and the second logical unit. The memory management circuit 51 may then query the management tables 1012-1014 according to the second logic unit to obtain the mapping information 1022-1024. Similar operations may also be applied to the exemplary embodiments of fig. 9A-9D, and the description is not repeated here.

In an example embodiment of fig. 8B, the memory management circuit 51 may disable reading of the physical unit 811 (i.e., the third physical unit) before the target operation is completed (i.e., the data a 'is written into the physical unit 811), so as to avoid reading of the erroneous data a' (i.e., the third data). The related operations may also be applied to the exemplary embodiments of fig. 9A to 9D, and the detailed description is omitted herein.

In an example embodiment, the memory management circuitry 51 may receive a request (also referred to as a boot request) from the host system 11 via the host interface 52. The memory management circuit 51 may initiate the first mode of operation in response to the initiation request. Thereafter, in the first mode of operation, the memory management circuit 51 may perform a target operation to obtain third data. However, in an example embodiment, the memory management circuit 51 may not initiate the first mode of operation without receiving a startup request. Furthermore, in an example embodiment, the memory management circuit 51 may leave or shut down the first mode of operation after one or more target operations are completed. In an example embodiment, if the first mode of operation is not enabled, the memory management circuit 51 may not perform the target operation.

In an exemplary embodiment, the memory management circuit 51 may determine whether to activate the first operation mode according to the logic unit to which the first data belongs (i.e., the first logic unit) after receiving the first data. For example, the memory management circuit 51 may determine whether the first logic unit to which the first data belongs is within a specific logic range. In response to the first logic unit being within a particular logic range, the memory management circuit 51 may initiate a first mode of operation. However, if the first logic unit is not within the specific logic range, the memory management circuit 51 may not activate the first operation mode.

In an example embodiment, the memory management circuitry 51 may receive write instructions from the host system 11 through the host interface 52. The write command is used for writing first data to the first logic unit. For example, such a write instruction may entrain the first data and the first logical unit to which the first data belongs. In the first mode of operation, the memory management circuit 51 may perform operations related to the target operation according to the first data and the first logic unit to generate third data. Details of the related operations are described above, and the detailed description thereof is not repeated here.

In an example embodiment, after receiving the write instruction, the memory management circuitry 51 may receive a read instruction from the host system 11 through the host interface 52. The read instruction is used for reading the first logic unit. Thus, after obtaining the third data, the memory management circuit 51 may transfer the third data to the host system 11 through the host interface 52 according to the read instruction, in response to the read instruction.

In an example embodiment, the memory management circuitry 51 may perform a handshake (handshake) operation with the host system 11 before performing the target operation. In this handshake operation, the memory management circuit 51 may perform initialization settings related to the target operation. For example, in this handshake operation, the memory management circuit 51 may perform an initialization operation that initiates the first mode of operation and/or initiates the operational model 72, etc.

In an example embodiment, in the handshake operation, memory management circuitry 51 may receive an inquiry instruction from host system 11. This query instruction may be used to confirm the ability of the memory storage device 10 to support the assisted operation of the artificial intelligence model 71. For example, such an interrogation instruction may be used to interrogate whether the memory storage device 10 supports an assisted operation of the artificial intelligence model 71, the type of algorithm that the memory storage device 10 supports for the assisted operation of the artificial intelligence model 71, and/or the resources (e.g., memory space required) that the memory storage device 10 requires to perform the assisted operation of the artificial intelligence model 71, etc. After receiving this query, the memory management circuit 51 may send a reply message to the host system 11 in the handshake operation. This reply message may be used to illustrate the ability of memory storage device 10 to support the assisted operations of artificial intelligence model 71. For example, this reply message may be used to reply to host system 11, whether memory storage device 10 supports the assisted operation of artificial intelligence model 71, the type of algorithm that memory storage device 10 supports the assisted operation of artificial intelligence model 71, and/or the resources (e.g., memory space required) that memory storage device 10 needs to perform the assisted operation of artificial intelligence model 71, etc. In addition, more information related to the target operation may also be exchanged with the host system 11 in the handshake operation, which is not limited by the present invention.

Fig. 11 is a flowchart of a memory operation method according to an exemplary embodiment of the present invention. Referring to fig. 11, in step S1101, first data is received from a host system. In step S1102, first data is stored to a first entity unit, wherein the first entity unit is mapped to a first logic unit. In step S1103, in the first operation mode, a target operation is performed according to the first data and the second data stored in the second entity unit to obtain third data, wherein the third data is different from the first data. In step S1104, the third data is stored to a third entity unit, wherein the third entity unit is also mapped to the first logic unit. In step S1105, the third data is transmitted to the host system.

However, the steps in fig. 11 are described in detail above, and will not be described again here. It should be noted that each step in fig. 11 may be implemented as a plurality of program codes or circuits, and the present invention is not limited thereto. In addition, the method of fig. 11 may be used with the above exemplary embodiment, or may be used alone, which is not limited by the present invention.

In summary, in the exemplary embodiment of the present invention, the target operation, which is preset to be responsible for the host system (or artificial intelligence model), is migrated to the memory storage device and executed by the memory storage device. Therefore, in the process of executing data updating by the artificial intelligent model, the data transmission quantity between the host system and the memory storage device can be reduced, and the operation efficiency of the host system (or the artificial intelligent model) can be further improved.

Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and not for limiting the same; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the invention.

Claims

1. A memory operation method for a memory storage device, wherein the memory storage device comprises a rewritable non-volatile memory module comprising a plurality of physical units, and the memory operation method comprises:

receiving first data from a host system;

storing the first data to a first entity unit of the plurality of entity units, wherein the first entity unit is mapped to a first logical unit;

in a first operation mode, performing a target operation according to the first data and second data of a second entity unit stored in the plurality of entity units to obtain third data, wherein the third data is different from the first data;

Storing the third data to a third entity unit of the plurality of entity units, wherein the third entity unit is also mapped to the first logical unit; and

the third data is transmitted to the host system.

2. The memory operation method according to claim 1, wherein the step of performing the target operation to obtain the third data from the first data and the second data of the second entity unit stored in the plurality of entity units comprises:

in the target operation, updating target data into the third data according to the first data and the second data.

3. The memory operation method according to claim 2, further comprising:

receiving fourth data from the host system; and

in the first operation mode, the target operation is performed according to the fourth data and the third data stored in the third entity unit to update the target data to fifth data.

4. The memory operation method according to claim 1, wherein the second entity unit is also mapped to the first logic unit.

5. The memory operation method according to claim 1, wherein the second entity unit is mapped to a second logic unit, the first logic unit is different from the second logic unit, and there is an association between the first logic unit and the second logic unit.

6. The memory operation method according to claim 1, further comprising:

recording first mapping information in a first mapping table, wherein the first mapping information reflects a mapping relationship between the first logic unit and the first entity unit; and

and recording second mapping information in a second mapping table, wherein the second mapping information reflects the mapping relation between the first logic unit and the second entity unit, and the first mapping table is different from the second mapping table.

7. The memory operation method according to claim 6, further comprising:

and in response to the third data being stored in the third entity unit, updating the first mapping information recorded in the first mapping table, wherein the updated first mapping information reflects a mapping relationship between the first logic unit and the third entity unit.

8. The memory operation method according to claim 1, further comprising:

reading the third entity unit is prohibited until the target operation is completed to obtain the third data.

9. The memory operation method according to claim 1, further comprising:

receiving a start request from the host system; and

And starting the first operation mode according to the starting request.

10. The memory operation method according to claim 1, further comprising:

and determining whether to start the first operation mode according to the first logic unit to which the first data belong.

11. The memory operation method according to claim 1, wherein the target operation is used to assist an artificial intelligence model in the host system in performing data update.

12. The memory operation method according to claim 1, further comprising:

receiving a write instruction from the host system, wherein the write instruction is to write the first data to the first logic unit;

receiving a read instruction from the host system, wherein the read instruction is to read the first logic unit; and

transmitting the third data to the host system in response to the read command.

13. The memory operation method according to claim 1, further comprising:

performing a handshake operation with the host system prior to performing the target operation; and

in the handshake operation, an initialization setting related to the target operation is performed.

14. The memory operation method of claim 13, wherein the handshake operation comprises:

Receiving an interrogation instruction from the host system, wherein the interrogation instruction is used to confirm the memory storage device's ability to support assisted operations of an artificial intelligence model; and

sending a reply message to the host system, wherein the reply message is used to illustrate the ability of the memory storage device to support the auxiliary operation of the artificial intelligence model.

15. A memory storage device, comprising:

a connection interface unit for connecting to a host system;

a rewritable non-volatile memory module including a plurality of physical units; and

a memory control circuit unit connected to the connection interface unit and the rewritable nonvolatile memory module,

wherein the memory control circuit unit is configured to:

receiving first data from the host system;

the third data is transmitted to the host system.

16. The memory storage device of claim 15, wherein the operation of the memory control circuit unit to perform the target operation from the first data and the second data stored in the second one of the plurality of entity units to obtain the third data comprises:

17. The memory storage device of claim 16, wherein the memory control circuit unit is further to:

receiving fourth data from the host system; and

18. The memory storage device of claim 15, wherein the second physical unit is also mapped to the first logical unit.

19. The memory storage device of claim 15, wherein the second physical unit maps to a second logical unit, the first logical unit is different from the second logical unit, and there is an association between the first logical unit and the second logical unit.

20. The memory storage device of claim 15, wherein the memory control circuit unit is further to:

21. The memory storage device of claim 20, wherein the memory control circuit unit is further to:

22. The memory storage device of claim 15, wherein the memory control circuit unit is further to:

23. The memory storage device of claim 15, wherein the memory control circuit unit is further to:

receiving a start request from the host system; and

and starting the first operation mode according to the starting request.

24. The memory storage device of claim 15, wherein the memory control circuit unit is further to:

25. The memory storage device of claim 15, wherein the target operation is to assist an artificial intelligence model in the host system in performing data updates.

26. The memory storage device of claim 15, wherein the memory control circuit unit is further to:

transmitting the third data to the host system in response to the read command.

27. The memory storage device of claim 15, wherein the memory control circuit unit is further to:

28. The memory storage device of claim 27, wherein the handshake operation comprises:

29. A memory control circuit unit for controlling a rewritable nonvolatile memory module, the rewritable nonvolatile memory module comprising a plurality of physical units, the memory control circuit unit comprising:

A host interface for connecting to a host system;

a memory interface to connect to the rewritable non-volatile memory module; and

a memory management circuit coupled to the host interface and the memory interface,

wherein the memory management circuit is to:

receiving first data from the host system;

the third data is transmitted to the host system.

30. The memory control circuit unit of claim 29, wherein the operation of the memory management circuit to perform the target operation from the first data and the second data stored in the second one of the plurality of entity units to obtain the third data comprises:

31. The memory control circuit unit of claim 30, wherein the memory management circuit is further to:

receiving fourth data from the host system; and

32. The memory control circuit unit of claim 29, wherein the second physical unit is also mapped to the first logic unit.

33. The memory control circuit unit of claim 29, wherein the second physical unit maps to a second logical unit, the first logical unit is different from the second logical unit, and there is an association between the first logical unit and the second logical unit.

34. The memory control circuit unit of claim 29, wherein the memory management circuit is further to:

35. The memory control circuit unit of claim 34, wherein the memory management circuit is further to:

36. The memory control circuit unit of claim 29, wherein the memory management circuit is further to:

37. The memory control circuit unit of claim 29, wherein the memory management circuit is further to:

receiving a start request from the host system; and

and starting the first operation mode according to the starting request.

38. The memory control circuit unit of claim 29, wherein the memory management circuit is further to:

39. The memory control circuit unit of claim 29, wherein the target operation is to assist an artificial intelligence model in the host system in performing data updates.

40. The memory control circuit unit of claim 29, wherein the memory management circuit is further to:

transmitting the third data to the host system in response to the read command.

41. The memory control circuit unit of claim 29, wherein the memory management circuit is further to:

42. The memory control circuit unit of claim 41, wherein the handshake operation comprises:

Receiving an interrogation instruction from the host system, wherein the interrogation instruction is to confirm the ability of the memory control circuit unit to support auxiliary operations of an artificial intelligence model; and

sending a reply message to the host system, wherein the reply message is used for describing the capability of the memory control circuit unit to support the auxiliary operation of the artificial intelligence model.