CN113590153B - Firmware upgrading method, system, equipment and medium of CPLD - Google Patents
Firmware upgrading method, system, equipment and medium of CPLD Download PDFInfo
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F8/00—Arrangements for software engineering
- G06F8/60—Software deployment
- G06F8/65—Updates
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0646—Horizontal data movement in storage systems, i.e. moving data in between storage devices or systems
- G06F3/0652—Erasing, e.g. deleting, data cleaning, moving of data to a wastebasket
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- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
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Abstract
The invention discloses a firmware upgrading method of a CPLD, which comprises the following steps: the processor sends an upgrade instruction to the CPLD so that the CPLD erases the corresponding firmware storage area according to the upgrade instruction; in response to the CPLD completing the erasure of the firmware storage area, updating the value of the first register to a first preset value; in response to the processor detecting that the value of the first register is updated to a first preset value, writing firmware upgrade data into the second register, and updating the value of the third register to a second preset value after the completion of the updating; and in response to the CPLD detecting that the value of the third register is updated to a second preset value, reading firmware upgrading data in the second register and writing the firmware upgrading data into the firmware storage area. The invention also discloses a system, computer equipment and a readable storage medium. The scheme provided by the invention reduces the dependence on hardware design and upper MCU design, reduces IO application, and increases design flexibility and universality.
Description
Technical Field
The invention relates to the field of firmware upgrading, in particular to a firmware upgrading method, system and device of a CPLD and a storage medium.
Background
CPLD is a semi-customized special integrated circuit, has flexible programming, quick response, high integration level and other advantages, and is widely applied in the early development, verification and control application fields. In the switch system, the CPLD chip is used for controlling the power-on and power-off time sequence control, communication control, key detection, fan rotating speed control, SFP lighting control, serial port switching and the like of the whole switch, and the MCU is used for indicating the switch state, state detection, firmware upgrading, remote control, voltage control, log collection and the like.
CPLD firmware upgrade is an important content of CPLD design, and is to upgrade an image into an internal Flash or SRAM, wherein the Flash is used as a storage area and has the characteristic of no loss in power failure; the SRAM is used as a working area, is an actual working area of logic design, and has the characteristic of power failure and loss. The step of upgrading the CPLD is to upgrade the image to Flash firstly, the normal work of the CPLD is not affected in the process, and then whether to execute the refreshing action of the CPLD is determined by actual requirements, namely the image is loaded to the SRAM from Flash, and at the moment, the IO of the CPLD is out of control and the normal work is affected. The firmware upgrading mode is usually based on IIC hard cores or JTAG (joint test action group) provided by a chip, the IIC hard core upgrading is realized through IIC communication, the communication between MCU (micro control unit) and CPLD (complex programmable logic device) special IIC is required to be realized on hardware, and meanwhile, the MCU is required to realize the IIC upgrading time sequence required by the CPLD; CPLD upgrading realized by JTAG (joint test action group), on one hand, MCU IO realization and communication of CPLD special JTAG are realized, and meanwhile, MCU is required to realize JTAG time sequence simulation. Both designs are based on hardware design, while relying on upper MCU timing design.
Disclosure of Invention
In view of this, in order to overcome at least one aspect of the above-mentioned problems, an embodiment of the present invention provides a firmware upgrade method for a CPLD, including the following steps:
the processor sends an upgrade instruction to the CPLD so that the CPLD erases the corresponding firmware storage area according to the upgrade instruction;
in response to the CPLD completing the erasure of the firmware storage area, updating the value of the first register to a first preset value;
in response to the processor detecting that the value of the first register is updated to a first preset value, writing firmware upgrade data into a second register, and updating the value of a third register to a second preset value after the current firmware upgrade data is written;
and in response to the CPLD detecting that the value of the third register is updated to a second preset value, reading firmware upgrading data in the second register and writing the firmware upgrading data into the firmware storage area.
In some embodiments, further comprising:
the processor updates the value of the first register from a first preset value to a third preset value;
responding to the CPLD to write the firmware upgrade data in the second register into the firmware storage area, and judging whether the value of the fourth register is a fourth preset value;
and responding to the value of the fourth register as a fourth preset value, and checking the data in the firmware storage area.
In some embodiments, further comprising:
updating the value of the first register from a third preset value to a fifth preset value;
in response to successful verification, updating the value of the first register from a fifth preset value to a sixth preset value;
and in response to the verification failure, updating the value of the first register from a fifth preset value to a seventh preset value.
In some embodiments, further comprising:
and in response to the processor detecting that the value of the first register is updated to a sixth preset value, feeding back success of firmware upgrade of the CPLD to an upper layer.
In some embodiments, further comprising:
and in response to the processor detecting that the value of the first register is updated to a seventh preset value, feeding back a verification failure to an upper layer.
In some embodiments, further comprising:
and in response to the value of the fourth register not being the fourth preset value, the CPLD updates the value of the first register from the third preset value to the first preset value, so that when the processor detects that the value of the first register is the first preset value again, the processor continues to write data into the second register.
In some embodiments, reading firmware upgrade data in the second register and writing to the firmware storage area further comprises:
and writing the firmware upgrading data into the firmware storage area by utilizing a wishbone bus.
Based on the same inventive concept, according to another aspect of the present invention, an embodiment of the present invention further provides a firmware upgrade system of a CPLD, including:
the processor module is configured to enable the processor to send an upgrade instruction to the CPLD so that the CPLD erases the corresponding firmware storage area according to the upgrade instruction;
the updating module is configured to respond to the completion of the erasure of the firmware storage area by the CPLD and update the value of the first register to a first preset value;
the writing module is configured to respond to the processor detecting that the value of the first register is updated to a first preset value, write firmware upgrading data into the second register, and update the value of the third register to a second preset value after the current firmware upgrading data is written;
and the reading module is configured to respond to the CPLD detecting that the value of the third register is updated to a second preset value, read the firmware upgrading data in the second register and write the firmware upgrading data into the firmware storage area.
Based on the same inventive concept, according to another aspect of the present invention, an embodiment of the present invention further provides a computer apparatus, including:
at least one processor; and
a memory storing a computer program executable on the processor, wherein the processor, when executing the program, performs the steps of any one of the CPLD firmware upgrade methods described above.
Based on the same inventive concept, according to another aspect of the present invention, there is also provided a computer-readable storage medium storing a computer program which, when executed by a processor, performs the steps of the firmware upgrade method of any one of the CPLDs described above.
The invention has one of the following beneficial technical effects: according to the scheme provided by the invention, the processor accesses the custom register in the CPLD, firmware upgrading data is written into the register, then the CPLD realizes driving logic, and then the data in the register is written into Flash, so that the MCU indirectly accesses the Flash, and further the MCU burns and upgrades the CPLD. Thus, the dependence on hardware design and upper MCU design is reduced, IO application is reduced, and design flexibility and universality are improved.
Drawings
In order to more clearly illustrate the embodiments of the invention or the technical solutions in the prior art, the drawings that are necessary for the description of the embodiments or the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the invention and that other embodiments may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a flowchart of a firmware upgrade method of a CPLD according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a firmware upgrade system of a CPLD according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a computer device according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of a computer-readable storage medium according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the following embodiments of the present invention will be described in further detail with reference to the accompanying drawings.
It should be noted that, in the embodiments of the present invention, all the expressions "first" and "second" are used to distinguish two entities with the same name but different entities or different parameters, and it is noted that the "first" and "second" are only used for convenience of expression, and should not be construed as limiting the embodiments of the present invention, and the following embodiments are not described one by one.
According to an aspect of the present invention, an embodiment of the present invention proposes a firmware upgrade method of a CPLD, as shown in fig. 1, which may include the steps of:
s1, a processor sends an upgrade instruction to a CPLD so that the CPLD erases a corresponding firmware storage area according to the upgrade instruction;
s2, updating the value of a first register to a first preset value in response to the completion of the erasure of the firmware storage area by the CPLD;
s3, in response to the processor detecting that the value of the first register is updated to a first preset value, writing firmware upgrading data into a second register, and updating the value of a third register to a second preset value after the current firmware upgrading data is written;
and S4, responding to the CPLD to detect that the value of the third register is updated to a second preset value, reading firmware upgrading data in the second register and writing the firmware upgrading data into the firmware storage area.
According to the scheme provided by the invention, the processor accesses the custom register in the CPLD, firmware upgrading data is written into the register, then the CPLD realizes driving logic, and then the data in the register is written into Flash, so that the MCU indirectly accesses the Flash, and further the MCU burns and upgrades the CPLD. Thus, the dependence on hardware design and upper MCU design is reduced, IO application is reduced, and design flexibility and universality are improved.
In some embodiments, in step S1, the processor sends an upgrade instruction to the CPLD, so that the CPLD erases a corresponding firmware storage area according to the upgrade instruction, and specifically, a specific erasure area may be different in the erased area due to different executing commands issued by the processor.
In some embodiments, a Flash command module may be provided in the CPLD, and operations that may be implemented by the module include: wishbone bus enabling, flash operating area erasing, flash operating area burning, burnt data checking and firmware refreshing, wherein the firmware refreshing can be related to user logic, namely whether to execute a refreshing instruction according to user requirements. The specific erasing area is different in erasing area due to different executed commands, that is, different operations are executed on Flash due to different commands.
In some embodiments, in step S2, in response to the CPLD completing the erasing of the firmware storage area, the value of the first register is updated to a first preset value, and in particular, the first register may be an upgrade status indication register, which may be used to indicate that the CPLD is ready to receive data, i.e. the processor (MCU) may write firmware upgrade data to the CPLD only when the value of the first register is the first preset value.
In some embodiments, in step S3, in response to the processor detecting that the value of the first register is updated to the first preset value, firmware upgrade data is written into the second register, and after the current firmware upgrade data is written into the second register, the value of the third register is updated to the second preset value, specifically, when the processor detects that the value of the first register is the first preset value, the data is written into the second register in the CPLD, and when the MCU writes the data into the second register, a single-byte writing manner may be adopted. And because of the limited capacity of the registers, the processor may need to write data into the second register for multiple rounds, but each round needs to update the value of the first register to the first preset value, that is, the CPLD is ready to receive data, and then the data is written into the second register for the next round. The third register may be an upgrade data enable control register, which is used to indicate whether the current firmware upgrade data is written, and if so, update the value to a second preset value to tell the CPLD that the data can be fetched from the second register.
In some embodiments, in step S4, in response to the CPLD detecting that the value of the third register is updated to the second preset value, the firmware upgrade data in the second register is read and written into the firmware storage area, specifically, after the CPLD detecting that the value of the third register is updated to the second preset value, it is indicated that the data in the second register needs to be written into the firmware storage area (i.e. Flash), and at this time, the CPLD updates the value of the third register from the second preset value to the default value.
In some embodiments, reading firmware upgrade data in the second register and writing to the firmware storage area further comprises:
and writing the firmware upgrading data into the firmware storage area by utilizing a wishbone bus.
Specifically, the LocalBus interface module in the CPLD may be used to implement the CPLD to access the mirror configuration area (i.e. Flash), and the LocalBus interface module may be a Wishbone interface module, that is, the CPLD implements sending related instructions to the Flash command module through the Wishbone interface module, so that the Flash command module implements a corresponding operation, thereby implementing access to the Flash area of the CPLD. The Wishbone design conforms to Wishbone design specifications, and the user logic interfaces are wb_clk, wb_rst, wb_cyc, wb_stb, wb_cyc, wb_ack, wb_addr, wb_datain and wb_dataout, and each meaning is Wishbone clock signal, reset signal, transmission instruction, core selection, response, address, input data and output data.
In some embodiments, further comprising:
the processor updates the value of the first register from a first preset value to a third preset value;
responding to the CPLD to write the firmware upgrade data in the second register into the firmware storage area, and judging whether the value of the fourth register is a fourth preset value;
and responding to the value of the fourth register as a fourth preset value, and checking the data in the firmware storage area.
Specifically, when the processor detects that the value of the first register is updated to the first preset value, writing firmware upgrade data into the second register is started, and at this time, the processor may update the value of the first register from the first preset value to the third preset value. The fourth register may be an upgrade enabling controller, which may be used to indicate whether the firmware upgrade data is completely written, and when the processor has completely written the firmware upgrade data, the processor may update the value of the fourth register and the fourth preset value, and the CPLD may perform a verification process on the data in the firmware storage area.
In some embodiments, further comprising:
updating the value of the first register from a third preset value to a fifth preset value;
in response to successful verification, updating the value of the first register from a fifth preset value to a sixth preset value;
and in response to the verification failure, updating the value of the first register from a fifth preset value to a seventh preset value.
In some embodiments, further comprising:
and in response to the processor detecting that the value of the first register is updated to a sixth preset value, feeding back success of firmware upgrade of the CPLD to an upper layer.
In some embodiments, further comprising:
and in response to the processor detecting that the value of the first register is updated to a seventh preset value, feeding back a verification failure to an upper layer.
Specifically, during the verification process, the CPLD may modify the value of the first register from the third preset value to the fifth preset value, which indicates that the verification process is being performed at this time, if the verification is successful, the value of the first register is updated from the fifth preset value to the sixth preset value, and the corresponding processor detects that the value of the first register is updated to the sixth preset value, and feeds back to the upper layer that the firmware of the CPLD is successfully updated; if the verification fails, updating the value of the first register from a fifth preset value to a seventh preset value, and correspondingly, detecting that the value of the first register is the seventh preset value by the processor, and feeding back the verification failure to an upper layer.
In some embodiments, further comprising:
and in response to the value of the fourth register not being the fourth preset value, the CPLD updates the value of the first register from the third preset value to the first preset value, so that when the processor detects that the value of the first register is the first preset value again, the processor continues to write data into the second register.
Specifically, if the value of the fourth register is not the fourth preset value, it indicates that the MCU does not completely write the firmware upgrade data of the CPLD, at this time, if the CPLD has already written the data in the second register into the flash, the value of the first register may be updated from the third preset value to the first preset value again, which indicates that the CPLD has already made preparation for receiving the data, then the MCU writes the data into the second register again, and after the data of the present round is completely written (for example, the second register is fully written), the third register is updated from the default value to the second preset value again, so as to tell the CPLD that the data can be read, and the reading process is the same as the process described in the above embodiment, which is not repeated here.
The proposal provided by the invention realizes the online upgrading function of the CPLD mirror image configuration area through the read-write operation of the MCU on the general register, the access of the MCU on the CPLD general register is the basic function of each CPLD, the common access interfaces are IIC, LPC and the like, and the PCIe access can be realized for high-speed PLD equipment. The CPLD LocalBus interface and the Flash command interface module are realized by the CPLD, the MCU only needs to read and write access to a CPLD universal register for operating the CPLD mirror image configuration area, and the communication between the universal register and the CPLD LocalBus interface is realized by the logic adhesion of CPLD users.
According to the scheme provided by the invention, the processor accesses the custom register in the CPLD, firmware upgrading data is written into the register, then the CPLD realizes driving logic, and then the data in the register is written into Flash, so that the MCU indirectly accesses the Flash, and further the MCU burns and upgrades the CPLD. Thus, the dependence on hardware design and upper MCU design is reduced, IO application is reduced, and design flexibility and universality are improved.
Based on the same inventive concept, according to another aspect of the present invention, there is further provided a firmware upgrade system 400 of a CPLD, as shown in fig. 2, including:
the processor module 401 is configured to enable the processor to send an upgrade instruction to the CPLD so that the CPLD erases the corresponding firmware storage area according to the upgrade instruction;
an update module 402 configured to update a value of a first register to a first preset value in response to the CPLD completing erasing the firmware storage area;
a writing module 403 configured to respond to the processor detecting that the value of the first register is updated to a first preset value, write firmware upgrade data into the second register, and update the value of the third register to a second preset value after the current firmware upgrade data is written;
and the reading module 404 is configured to respond to the CPLD detecting that the value of the third register is updated to a second preset value, read the firmware upgrading data in the second register and write the firmware upgrading data into the firmware storage area.
In some embodiments, further comprising:
the processor updates the value of the first register from a first preset value to a third preset value;
responding to the CPLD to write the firmware upgrade data in the second register into the firmware storage area, and judging whether the value of the fourth register is a fourth preset value;
and responding to the value of the fourth register as a fourth preset value, and checking the data in the firmware storage area.
In some embodiments, further comprising:
updating the value of the first register from a third preset value to a fifth preset value;
in response to successful verification, updating the value of the first register from a fifth preset value to a sixth preset value;
and in response to the verification failure, updating the value of the first register from a fifth preset value to a seventh preset value.
In some embodiments, further comprising:
and in response to the processor detecting that the value of the first register is updated to a sixth preset value, feeding back success of firmware upgrade of the CPLD to an upper layer.
In some embodiments, further comprising:
and in response to the processor detecting that the value of the first register is updated to a seventh preset value, feeding back a verification failure to an upper layer.
In some embodiments, further comprising:
and in response to the value of the fourth register not being the fourth preset value, the CPLD updates the value of the first register from the third preset value to the first preset value, so that when the processor detects that the value of the first register is the first preset value again, the processor continues to write data into the second register.
In some embodiments, reading firmware upgrade data in the second register and writing to the firmware storage area further comprises:
and writing the firmware upgrading data into the firmware storage area by utilizing a wishbone bus.
According to the scheme provided by the invention, the processor accesses the custom register in the CPLD, firmware upgrading data is written into the register, then the CPLD realizes driving logic, and then the data in the register is written into Flash, so that the MCU indirectly accesses the Flash, and further the MCU burns and upgrades the CPLD. Thus, the dependence on hardware design and upper MCU design is reduced, IO application is reduced, and design flexibility and universality are improved.
Based on the same inventive concept, according to another aspect of the present invention, as shown in fig. 3, an embodiment of the present invention further provides a computer apparatus 501, including:
at least one processor 520; and
the memory 510, the memory 510 stores a computer program 511 executable on a processor, and the processor 520 executes the program to perform the steps of:
s1, a processor sends an upgrade instruction to a CPLD so that the CPLD erases a corresponding firmware storage area according to the upgrade instruction;
s2, updating the value of a first register to a first preset value in response to the completion of the erasure of the firmware storage area by the CPLD;
s3, in response to the processor detecting that the value of the first register is updated to a first preset value, writing firmware upgrading data into a second register, and updating the value of a third register to a second preset value after the current firmware upgrading data is written;
and S4, responding to the CPLD to detect that the value of the third register is updated to a second preset value, reading firmware upgrading data in the second register and writing the firmware upgrading data into the firmware storage area.
In some embodiments, further comprising:
the processor updates the value of the first register from a first preset value to a third preset value;
responding to the CPLD to write the firmware upgrade data in the second register into the firmware storage area, and judging whether the value of the fourth register is a fourth preset value;
and responding to the value of the fourth register as a fourth preset value, and checking the data in the firmware storage area.
In some embodiments, further comprising:
updating the value of the first register from a third preset value to a fifth preset value;
in response to successful verification, updating the value of the first register from a fifth preset value to a sixth preset value;
and in response to the verification failure, updating the value of the first register from a fifth preset value to a seventh preset value.
In some embodiments, further comprising:
and in response to the processor detecting that the value of the first register is updated to a sixth preset value, feeding back success of firmware upgrade of the CPLD to an upper layer.
In some embodiments, further comprising:
and in response to the processor detecting that the value of the first register is updated to a seventh preset value, feeding back a verification failure to an upper layer.
In some embodiments, further comprising:
and in response to the value of the fourth register not being the fourth preset value, the CPLD updates the value of the first register from the third preset value to the first preset value, so that when the processor detects that the value of the first register is the first preset value again, the processor continues to write data into the second register.
In some embodiments, reading firmware upgrade data in the second register and writing to the firmware storage area further comprises:
and writing the firmware upgrading data into the firmware storage area by utilizing a wishbone bus.
According to the scheme provided by the invention, the processor accesses the custom register in the CPLD, firmware upgrading data is written into the register, then the CPLD realizes driving logic, and then the data in the register is written into Flash, so that the MCU indirectly accesses the Flash, and further the MCU burns and upgrades the CPLD. Thus, the dependence on hardware design and upper MCU design is reduced, IO application is reduced, and design flexibility and universality are improved.
Based on the same inventive concept, according to another aspect of the present invention, as shown in fig. 4, an embodiment of the present invention further provides a computer-readable storage medium 601, the computer-readable storage medium 601 storing computer program instructions 610, the computer program instructions 610 when executed by a processor performing the steps of:
s1, a processor sends an upgrade instruction to a CPLD so that the CPLD erases a corresponding firmware storage area according to the upgrade instruction;
s2, updating the value of a first register to a first preset value in response to the completion of the erasure of the firmware storage area by the CPLD;
s3, in response to the processor detecting that the value of the first register is updated to a first preset value, writing firmware upgrading data into a second register, and updating the value of a third register to a second preset value after the current firmware upgrading data is written;
and S4, responding to the CPLD to detect that the value of the third register is updated to a second preset value, reading firmware upgrading data in the second register and writing the firmware upgrading data into the firmware storage area.
In some embodiments, further comprising:
the processor updates the value of the first register from a first preset value to a third preset value;
responding to the CPLD to write the firmware upgrade data in the second register into the firmware storage area, and judging whether the value of the fourth register is a fourth preset value;
and responding to the value of the fourth register as a fourth preset value, and checking the data in the firmware storage area.
In some embodiments, further comprising:
updating the value of the first register from a third preset value to a fifth preset value;
in response to successful verification, updating the value of the first register from a fifth preset value to a sixth preset value;
and in response to the verification failure, updating the value of the first register from a fifth preset value to a seventh preset value.
In some embodiments, further comprising:
and in response to the processor detecting that the value of the first register is updated to a sixth preset value, feeding back success of firmware upgrade of the CPLD to an upper layer.
In some embodiments, further comprising:
and in response to the processor detecting that the value of the first register is updated to a seventh preset value, feeding back a verification failure to an upper layer.
In some embodiments, further comprising:
and in response to the value of the fourth register not being the fourth preset value, the CPLD updates the value of the first register from the third preset value to the first preset value, so that when the processor detects that the value of the first register is the first preset value again, the processor continues to write data into the second register.
In some embodiments, reading firmware upgrade data in the second register and writing to the firmware storage area further comprises:
and writing the firmware upgrading data into the firmware storage area by utilizing a wishbone bus.
According to the scheme provided by the invention, the processor accesses the custom register in the CPLD, firmware upgrading data is written into the register, then the CPLD realizes driving logic, and then the data in the register is written into Flash, so that the MCU indirectly accesses the Flash, and further the MCU burns and upgrades the CPLD. Thus, the dependence on hardware design and upper MCU design is reduced, IO application is reduced, and design flexibility and universality are improved.
Finally, it should be noted that, as will be appreciated by those skilled in the art, all or part of the procedures in implementing the methods of the embodiments described above may be implemented by a computer program for instructing relevant hardware, and the program may be stored in a computer readable storage medium, and the program may include the procedures of the embodiments of the methods described above when executed.
Further, it should be appreciated that the computer-readable storage medium (e.g., memory) herein can be either volatile memory or nonvolatile memory, or can include both volatile and nonvolatile memory.
Those of skill would further appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the disclosure herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as software or hardware depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.
The foregoing is an exemplary embodiment of the present disclosure, but it should be noted that various changes and modifications could be made herein without departing from the scope of the disclosure as defined by the appended claims. The functions, steps and/or actions of the method claims in accordance with the disclosed embodiments described herein need not be performed in any particular order. Furthermore, although elements of the disclosed embodiments may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated.
It should be understood that as used herein, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly supports the exception. It should also be understood that "and/or" as used herein is meant to include any and all possible combinations of one or more of the associated listed items.
The foregoing embodiment of the present invention has been disclosed with reference to the number of embodiments for the purpose of description only, and does not represent the advantages or disadvantages of the embodiments.
It will be appreciated by those of ordinary skill in the art that all or part of the steps of implementing the above embodiments may be implemented by hardware, or may be implemented by a program to instruct related hardware, and the program may be stored in a computer readable storage medium, where the storage medium may be a read-only memory, a magnetic disk or an optical disk, etc.
Those of ordinary skill in the art will appreciate that: the above discussion of any embodiment is merely exemplary and is not intended to imply that the scope of the disclosure of embodiments of the invention, including the claims, is limited to such examples; combinations of features of the above embodiments or in different embodiments are also possible within the idea of an embodiment of the invention, and many other variations of the different aspects of the embodiments of the invention as described above exist, which are not provided in detail for the sake of brevity. Therefore, any omission, modification, equivalent replacement, improvement, etc. of the embodiments should be included in the protection scope of the embodiments of the present invention.
Claims (8)
1. The firmware upgrading method for the CPLD is characterized by comprising the following steps of:
the processor sends an upgrade instruction to the CPLD so that the CPLD erases the corresponding firmware storage area according to the upgrade instruction;
in response to the CPLD completing the erasure of the firmware storage area, updating the value of the first register to a first preset value;
in response to the processor detecting that the value of the first register is updated to a first preset value, writing firmware upgrade data into a second register, and updating the value of a third register to a second preset value after the current firmware upgrade data is written;
responding to the CPLD to detect that the value of the third register is updated to a second preset value, reading firmware upgrading data in the second register and writing the firmware upgrading data into the firmware storage area;
the processor updates the value of the first register from a first preset value to a third preset value;
responding to the CPLD to write the firmware upgrade data in the second register into the firmware storage area, and judging whether the value of the fourth register is a fourth preset value;
responding to the value of the fourth register as a fourth preset value, and checking the data in the firmware storage area;
and in response to the value of the fourth register not being the fourth preset value, the CPLD updates the value of the first register from the third preset value to the first preset value, so that when the processor detects that the value of the first register is the first preset value again, the processor continues to write data into the second register.
2. The method as recited in claim 1, further comprising:
updating the value of the first register from a third preset value to a fifth preset value;
in response to successful verification, updating the value of the first register from a fifth preset value to a sixth preset value;
and in response to the verification failure, updating the value of the first register from a fifth preset value to a seventh preset value.
3. The method as recited in claim 2, further comprising:
and in response to the processor detecting that the value of the first register is updated to a sixth preset value, feeding back success of firmware upgrade of the CPLD to an upper layer.
4. The method as recited in claim 2, further comprising:
and in response to the processor detecting that the value of the first register is updated to a seventh preset value, feeding back a verification failure to an upper layer.
5. The method of claim 1, wherein reading firmware upgrade data in the second register and writing to the firmware storage area, further comprises:
and writing the firmware upgrading data into the firmware storage area by utilizing a wishbone bus.
6. A firmware upgrade system for a CPLD, comprising:
the processor module is configured to enable the processor to send an upgrade instruction to the CPLD so that the CPLD erases the corresponding firmware storage area according to the upgrade instruction;
the updating module is configured to respond to the completion of the erasure of the firmware storage area by the CPLD and update the value of the first register to a first preset value;
the writing module is configured to respond to the processor detecting that the value of the first register is updated to a first preset value, write firmware upgrading data into the second register, and update the value of the third register to a second preset value after the current firmware upgrading data is written;
the reading module is configured to respond to the CPLD detecting that the value of the third register is updated to a second preset value, read firmware upgrading data in the second register and write the firmware upgrading data into the firmware storage area; a module for performing the steps of:
the processor updates the value of the first register from a first preset value to a third preset value;
responding to the CPLD to write the firmware upgrade data in the second register into the firmware storage area, and judging whether the value of the fourth register is a fourth preset value;
responding to the value of the fourth register as a fourth preset value, and checking the data in the firmware storage area;
and in response to the value of the fourth register not being the fourth preset value, the CPLD updates the value of the first register from the third preset value to the first preset value, so that when the processor detects that the value of the first register is the first preset value again, the processor continues to write data into the second register.
7. A computer device, comprising:
at least one processor; and
a memory storing a computer program executable on the processor, wherein the processor performs the steps of the method of any one of claims 1-5 when the program is executed.
8. A computer readable storage medium storing a computer program, characterized in that the computer program when executed by a processor performs the steps of the method according to any one of claims 1-5.
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| CN111142896A (en) * | 2019-12-09 | 2020-05-12 | 苏州浪潮智能科技有限公司 | Method and device for upgrading firmware of storage device and readable medium |
| CN112199231A (en) * | 2020-10-21 | 2021-01-08 | 苏州浪潮智能科技有限公司 | CPLD fault detection and repair method and device |
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| CN111090545A (en) * | 2019-11-28 | 2020-05-01 | 苏州浪潮智能科技有限公司 | Method, device and medium for recovering failed CPLD |
| CN111142896A (en) * | 2019-12-09 | 2020-05-12 | 苏州浪潮智能科技有限公司 | Method and device for upgrading firmware of storage device and readable medium |
| CN112199231A (en) * | 2020-10-21 | 2021-01-08 | 苏州浪潮智能科技有限公司 | CPLD fault detection and repair method and device |
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