CN104090792B - The dynamic loading method of logical file in a kind of broadband access network - Google Patents
The dynamic loading method of logical file in a kind of broadband access network Download PDFInfo
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Abstract
The invention discloses a kind of logical file dynamic loading method of broadband access network, fpga logic file dynamic load is realized by Transmission Control Protocol, it is not required to restart system after loading is completed, and in veneer running, the fpga logic file that whenever can load redaction removes to substitute the fpga logic file currently run, so improves the flexibility of system again while ensure that efficiency of transmission and reliability；In actual moving process, it is only necessary to which the connection IP address of client is set into the IP address of veneer, so again expand application, and it is simple and easy to apply meet current embedded system development the need for.
Description
Technical field
The invention belongs to embedded system technology field, more specifically, it is related to a kind of logic text of broadband access network
Part dynamic loading method.
Background technology
VxWorks are a set of real-time embedded operating systems of Wind River company exploitation, wide because of its excellent performance
General applies on each embedded device, especially passive optical network PON (Passive Optical Network), route
The network equipments such as device, interchanger；Transmission Control Protocol realizes being in communication with each other for some main frames, and a kind of application program accesses communication protocol
Operating system call socket；Embedded under more complicated demand based on access network, the file of required loading has
Multiple version files of difference in functionality need to chip controls on veneer to ensure overall operation in specific function；In access network
In, different PON mode logics files are being handled, it is necessary to which the compiling file of difference in functionality is loaded into operation on veneer.Access network
In passive optical network PON be a kind of prefect dielectric network, it is to avoid the electromagnetic interference and effects of lightning of external equipment, reduce line
Road and the fault rate of external equipment.PON service transparency preferably, is applicable to any standard and rate signal in principle.
It is well known that the logical file of generally any a embedded system compiling is required for being transferred on veneer and could controlled
The normal work of veneer processed.It may also be needed by the specific function of embedded Control, in current access network in access network application
Embedded logic file loading method in, its general loading is all based on serial ports and FTP TFTP (Trivial
File Transfer Protocol) it is transferred on veneer.The shortcoming existed is loaded using TFTP and serial ports：1st, it usually exists
When opening veneer or whole system reset after load, relative to being a kind of static loading mode；2nd, its need serial ports with
TFTP work simultaneously can loading logic file, i.e., while need serial ports and network interface all to be linked with veneer, the model of relative usage
Enclose comparison narrow；3rd, TFTP agreements transmitted data rates need the time especially long than relatively low when transmitting larger logical file；4、
The transmission of TFTP agreements is lower relative to Transmission Control Protocol reliability so that any mistake is likely to occur in transmitting procedure, biography is reduced
The reliability of defeated file；5th, the fpga logic file loaded for there is multiple versions to need, it can not be dynamic in the process of running
Loading so that for relatively complicated engineering, it can not complete corresponding function, reduce system availability.
In existing technology, the method for embedded system application program dynamic load, by by the firmware of application program
In the external memory space that file deposit embedded device is carried, and the function interface between operating system and application program is set
Carry out the dynamic load [method that Li Jing carrys out embedded system application program dynamic loads:Chinese [P]
.CN102541579A.2012-07-04]；A kind of method and embedded system of embedded OS loading logic file, will
Logical file is added in the data of embedded OS itself, allows embedded OS by calling its data
Come loading logic file [Yang Ting, Wang Wei, the method for a kind of embedded OS loading logic files of Zeng Yungang and embedded
System:China [P] .CN1900909.2007-01-24].It can only solve to load a kind of logical file of pattern in above patent,
In the process of running can not dynamic load online, the demand changed for there is various modes to need, it can not realize dynamic load,
Its loading procedure needs veneer to restart, and undoubtedly adds complexity, and can not realize in specific environment special function.
The content of the invention
Dynamically add it is an object of the invention to overcome the deficiencies of the prior art and provide a kind of logical file of broadband access network
Support method, realizes fpga logic file dynamic load by Transmission Control Protocol, so improves application, while having flexibility
High, transmission time is fast and transmits reliable advantage.
For achieving the above object, in a kind of broadband access network of the invention logical file dynamic loading method, it is special
Levy and be, comprise the following steps：
(1), compiling needs the fpga logic file loaded
The fpga chip model used at PC ends, selection correspondence, being compiled by quartus II needs the FPGA loaded to patrol
File is collected, the fpga logic file after compiling is stored under the loading catalogue at PC ends；
(2) FPGA of current version, is run
VxWorks system file is loaded to the CPU of veneer, treats after the completion of the loading of VxWorks system file, reads PC ends
The acquiescence fpga logic file of catalogue storage is loaded, by the fpga logic file of default version and is loaded on the CPU of veneer, and
The acquiescence fpga logic file is configured into FPGA, the fpga logic file of default version is normally run；
(3) the fpga logic file of default version, is changed
The transmission port of client in the transmission port at CPU TCP Socket service devices end in veneer and PC ends is set
It is identical, and the client in the TCP Socket service device ends and PC ends in veneer CPU is opened into TCP Socket services simultaneously,
And the connection IP address of client in PC ends is set to the IP address of veneer；
Selection needs client the adding from storage fpga logic file in the fpga logic file of dynamic load, PC ends
Carry and read this under catalogue and need the fpga logic file of dynamic load, and identify with power function document size information, then group
Dress up the TCP Socket service devices end that data frame sends CPU in veneer to；
CPU TCP Socket service devices end is received after listening to the data frame sent in veneer, further according to work(
The data frame that energy function parsing is received gets the size information of the fpga logic file for needing dynamic load, and dynamic is needed according to this
The fileinfo of the fpga logic of loading is to CPU application distribution Drams, and CPU is allocated and records distribution Dram
First address；
Client in PC ends continues packet transmission, and this needs the TCP of CPU in dynamic load fpga logic file content, veneer
Socket service device end often receive one group send from the client in PC ends this need in dynamic load fpga logic file
Rong Hou, sends and receives confirmation to the client in PC ends, the client in PC ends receives the TCP of CPU in veneer
Next group of fpga logic file content is sent after the reception confirmation that Socket service device end is sent, otherwise will persistently be sent
When previous group fpga logic file content number, if can not be successfully transmitted within the regular hour in one group of fpga logic file
Hold, then return and send failure information to the client in PC ends；
CPU TCP Socket services device does not stop skew reception according to the length for receiving fpga logic file content in veneer
First address, and be stored in veneer in CPU internal memory, the fpga logic file of dynamic load to be needed is completely transferred to veneer
After the completion of CPU, fpga logic file content is copied from the Dram of distribution into CPU flash, redaction is used as
Fpga logic file, and the fpga logic file of legacy version, the Dram of completion release application to be copied are covered simultaneously；
(4) the fpga logic file of redaction, is run；
By the control command of CPU in veneer, the redaction fpga logic file in CPU flash by CPU,
The localbus of FPGA connections is sent on fpga chip, it is to be transmitted after the completion of, configure redaction fpga logic file clock
And the input/output interface of data, redaction fpga logic file is run in the case where requiring clock, then control whole
VxWorks system is operated under the pattern of redaction fpga logic file.
Further, described data frame is made up of frame head and data division, and data division is by data type, data
Length, power function composition, wherein, data length is used to apply for Dram, the data frame that data type correspondence parsing is received
The power function called.
In described step (4), redaction fpga logic file is sent to by FPGA by the CPU of veneer control command
Process on chip is：Select mode that redaction fpga logic file is sent on fpga chip by piece；Wherein, redaction
The data transfer of fpga logic file is completed by localbus data wires and localbus address wires, and localbus data wires are used
To transmit the corresponding binary data of redaction fpga logic file, localbus address wires are used to specify the address of transmission.
What the goal of the invention of the present invention was realized in：
The dynamic loading method of logical file in broadband access network of the present invention, fpga logic file is realized by Transmission Control Protocol
Dynamic load, is not required to restart system after loading is completed, and in veneer running, whenever can load new
The fpga logic file of version removes to substitute the fpga logic file currently run, so ensure that efficiency of transmission and reliability
Improve the flexibility of system again simultaneously；In actual moving process, it is only necessary to which the connection IP address of client is set into list
The IP address of plate, so again expand application, and it is simple and easy to apply meet current embedded system development the need for.
Meanwhile, the logical file dynamic loading method of broadband access network of the present invention also has the advantages that：
(1) fpga logic file dynamic load, is realized by using Transmission Control Protocol, it is ensured that the high efficiency of data transfer and
Reliability；
(2) before and after, being loaded to fpga logic file, system should not be restarted, and dynamic loading multi version
Fpga logic file, so expands the scope of application, while ensure that the flexibility of system；
(3), the present invention is capable of the loading of the fpga logic file of compatible multi version, should not additionally increase hardware spending, again
The characteristics of with low cost.
Brief description of the drawings
Fig. 1 is the schematic diagram of the logical file dynamic loading method of broadband access network of the present invention；
Fig. 2 is the flow chart of the logical file dynamic loading method of broadband access network of the present invention；
Fig. 3 is the structure chart of data frame.
Embodiment
The embodiment to the present invention is described below in conjunction with the accompanying drawings, so as to those skilled in the art preferably
Understand the present invention.Requiring particular attention is that, in the following description, when known function and design detailed description perhaps
When can desalinate the main contents of the present invention, these descriptions will be ignored herein.
Embodiment
Fig. 1 is the schematic diagram of the dynamic loading method of logical file in broadband access network of the present invention.
In the present embodiment, as shown in figure 1, during the fpga logic file dynamic load of broadband access network, being used at PC ends
Be windows systems as client, veneer CPU use in the system of VxWorks 6.8, implementation process using C/C++ language with
Transmission Control Protocol carries out data transmission, and verifies transmission result.Here, replacing version with version 2 (needing loading) fpga logic file
This 1 (default version) fpga logic file, the process implemented, veneer starting load application version 1FPGA logical files were being run
Cheng Zhong, needs load application version 2 according to demand.
The dynamic loading method of logical file in broadband access network of the present invention, as shown in Fig. 2 comprising the following steps：
S1), compiling needs the fpga logic file loaded；
Being compiled by quartus II composing softwares needs the fpga logic file of the version 1 and version 2 loaded, during compiling
The fpga chip model for needing correct selection correspondence to use；Fpga logic file after compiling is constituted with binary data, due to
Binary data corresponding to the fpga logic file of different versions is different, therefore, is distinguished not with different names
With the fpga logic file of version；
S2), the fpga logic file after storage compiling；
Version 1 and the fpga logic file of version 2 after compiling is stored under the loading catalogue at PC ends；
S3 the FPGA of current version), is run；
VxWorks system file is loaded to the CPU of veneer, treats after the completion of the loading of VxWorks system file, reads PC ends
The loading catalogue of fpga logic file is deposited, version 1FPGA logical files are read and are loaded on the CPU of veneer, and are configured
The fpga logic file of version 1 makes the fpga logic file of version 1 normally run into FPGA；
S4 TCP Socket services), are opened；
The transmission port of client in the transmission port at CPU TCP Socket service devices end in veneer and PC ends is set
It is identical, and the client in the TCP Socket service device ends and PC ends in veneer CPU is opened into TCP Socket services simultaneously,
And the connection IP address of client in PC ends is set to the IP address of veneer；
S5), PC ends send the fpga logic document size information for needing to load；
Selection needs client the adding from storage fpga logic file in the fpga logic file of dynamic load, PC ends
Catalogue is carried, version 2 fpga logic file is read, and identifies with power function document size information, and version 2 fpga logic
Document size information is packaged into the TCP Socket service devices end that data frame sends CPU in veneer to.
Wherein, as shown in figure 3, data frame is made up of frame head and data division, and data division is by data type, data
Length, power function composition, wherein, data length is used to apply for Dram, the data frame that data type correspondence parsing is received
The power function called；
S6), TCP Socket services end receives the fpga logic document size information of PC ends transmission and applies distributing to CPU
Dram；
TCP Socket service devices end is received after listening to the data frame sent, is connect further according to power function parsing
The data frame of receipts gets the size information of version 2 fpga logic file, and records the size letter of version 2 fpga logic file
Breath, further according to version 2 fpga logic file size information to CPU application distribution Drams, CPU is allocated and recorded point
First address with Dram；
S7), TCP Socket services device receives the fpga logic file content that PC ends are sent；
Client in PC ends persistently sends version 2 fpga logic file content, and TCP Socket service devices are according to reception
The length of fpga logic file content ceaselessly offsets reception address, because Transmission Control Protocol can transmit 1518 byte datas every time,
This defines every group of byte of transmission 1024, and often receiving the corresponding address of one group of data needs to move 1024 bytes backward, prepares under storage
One group of reception fpga logic file content.
CPU TCP Socket service devices end often receives one group of need sent from the client in PC ends in veneer
After dynamic load fpga logic file content, send and receive confirmation to the client in PC ends, client's termination in PC ends
Next group of fpga logic file is sent after receiving the reception confirmation that the TCP Socket service devices end of CPU in veneer is sent
Content, otherwise will persistently send when previous group fpga logic file content number, if can not be successfully transmitted within the regular hour
One group of fpga logic file content, then return and send failure information to the client in PC ends.
S8), the fpga logic file that storage is received；
Treat that version 2 fpga logic file is completely transferred to after the completion of the CPU of veneer, the copy page from the Dram of distribution
Version 2 fpga logic file is so stored in CPU fixing address by this 2 fpga logic file content into CPU flash
Flash internal memories in, and cover version 1FPGA logical files, the Dram of completion release application to be copied；
S9 the fpga logic file of current version), is run；
By the control command of CPU in veneer, using version 2 fpga logic file in the flash by the way of piece is selected CPU
Be sent to by CPU, FPGA localbus connected on fpga chip, wherein, the data transfer of fpga logic file be by
Localbus data wires are completed with localbus address wires, and localbus data wires are used for transmitting fpga logic file corresponding two
Binary data, localbus address wires are used to specify the address of transmission；
Whole VxWorks system is operated under version 2 fpga logic file mode, it is to be transmitted after the completion of, configuration
The clock of version 2 fpga logic file and the input/output interface of data, make version 2 fpga logic file require clock
Lower operation, then controls whole VxWorks system to be operated under the pattern of version 2 fpga logic file.
Although illustrative embodiment of the invention is described above, in order to the technology of the art
Personnel understand the present invention, it should be apparent that the invention is not restricted to the scope of embodiment, to the common skill of the art
For art personnel, as long as various change is in the spirit and scope of the present invention that appended claim is limited and is determined, these
Change is it will be apparent that all utilize the innovation and creation of present inventive concept in the row of protection.
Claims (3)
1. the dynamic loading method of logical file, comprises the following steps in a kind of broadband access network：
(1), compiling needs the fpga logic file loaded
The fpga chip model used at PC ends, selection correspondence, the fpga logic text for needing to load is compiled by quartus II
Part, the fpga logic file after compiling is constituted with binary data, then to the fpga logic file designation after compiling, according to title
Fpga logic file after compiling is stored under the loading catalogue at PC ends；
(2) FPGA of current version, is run
VxWorks system file is loaded to the CPU of veneer, treats after the completion of the loading of VxWorks system file, reads the loading of PC ends
The default version fpga logic file of catalogue storage, the fpga logic file of default version is loaded on the CPU of veneer, and is matched somebody with somebody
The default version fpga logic file is put into FPGA, the fpga logic file of default version is normally run；
Characterized in that, further comprising the steps of：
(3), dynamic changes the fpga logic file of default version under operation
The transmission port of the transmission port at CPU TCP Socket service devices end in veneer and client in PC ends is set into phase
Together, and by the client in the TCP Socket service device ends and PC ends in veneer CPU TCP Socket services are opened simultaneously, and
The connection IP address of client in PC ends is set to the IP address of veneer；
Selection needs loading of the client in the fpga logic file name of dynamic load, PC ends from storage fpga logic file
Reading this according to title under catalogue needs the fpga logic file of dynamic load, and identifies document size information with power function,
Then it is assembled into the TCP Socket service devices end that data frame sends CPU in veneer to；
CPU TCP Socket service devices end is received after listening to the data frame sent in veneer, further according to function letter
The data frame that number parsing is received gets the size information of the fpga logic file for needing dynamic load, and dynamic load is needed according to this
Fpga logic document size information to CPU application distribution Drams, CPU is allocated and records distribution Dram
First address；
Client in PC ends continues packet transmission, and this needs the TCP of CPU in the fpga logic file content of dynamic load, veneer
Socket service device end often receive one group send from the client in PC ends this need the fpga logic file of dynamic load
After content, send and receive confirmation to the client in PC ends, the client in PC ends receives the TCP of CPU in veneer
Next group of fpga logic file content is sent after the reception confirmation that Socket service device end is sent, otherwise will persistently be sent
When previous group fpga logic file content number, if can not be successfully transmitted within the regular hour in one group of fpga logic file
Hold, then return and send failure information to the client in PC ends；
CPU TCP Socket services device does not stop the head that skew is received according to the length for receiving fpga logic file content in veneer
Address, and being stored in veneer in CPU internal memory, the CPU that the fpga logic file of dynamic load to be needed is completely transferred to veneer is complete
Cheng Hou, copies fpga logic file content into CPU flash from the Dram of distribution, is patrolled as the FPGA of redaction
File is collected, and covers the fpga logic file of legacy version, the Dram of completion release application to be copied simultaneously；
(4) the fpga logic file of redaction, is run；
By the control command of CPU in veneer, using the redaction fpga logic file in the flash by the way of piece is selected CPU
Be sent to by CPU, FPGA localbus connected on fpga chip, it is to be transmitted after the completion of, configuration redaction fpga logic text
The clock of part and the input/output interface of data, make redaction fpga logic file be run in the case where requiring clock, then control
Whole VxWorks system is operated under the pattern of redaction fpga logic file.
2. the dynamic loading method of logical file according to claim 1, it is characterised in that described data frame by frame head and
Data division is constituted, and data division is made up of data type, data length, power function, wherein, data length is used for Shen
Please Dram, the power function that the data frame that data type correspondence parsing is received is called.
3. the dynamic loading method of logical file according to claim 1, it is characterised in that in described step (4), leads to
The control command at CPU ends be by the process that redaction fpga logic file is sent on fpga chip：Mode is selected by piece
Fpga logic file is sent on fpga chip；Wherein, the data transfer of fpga logic file is by localbus data wires
Completed with localbus address wires, localbus data wires are used for transmitting the corresponding binary data of fpga logic file,
Localbus address wires are used to specify the address of transmission.
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| CN106354966B (en) * | 2016-09-06 | 2019-11-08 | 芯海科技（深圳）股份有限公司 | The method of the conversion of chip id E project file and rapid configuration artificial debugging environment |
| CN106534067B (en) * | 2016-09-29 | 2019-07-05 | 安徽华速达电子科技有限公司 | A kind of intelligent control method and system based on Internet of Things |
| CN108170490A (en) * | 2017-12-07 | 2018-06-15 | 中国航空工业集团公司西安航空计算技术研究所 | A kind of IMA system datas loading framework and loading method |
| CN111209056B (en) * | 2020-01-02 | 2021-02-19 | 北京东土科技股份有限公司 | Method and device for loading function, readable storage medium and electronic equipment |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101000550A (en) * | 2006-12-13 | 2007-07-18 | 青岛大学 | Remote on-line reconfiguration method of embedded system |
| CN102053850A (en) * | 2010-12-17 | 2011-05-11 | 天津曙光计算机产业有限公司 | Method for on-line FPGA logic upgrade |
| CN103313428A (en) * | 2013-06-17 | 2013-09-18 | 南京邮电大学 | Wi-Fi (wireless fidelity) communication system and Wi-Fi communication method for smartphone and upper computer in computer five-prevention system |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7746901B2 (en) * | 2006-12-14 | 2010-06-29 | Oracle America, Inc. | Method and system for offloaded transport layer protocol switching |
| CN101605078B (en) * | 2009-07-14 | 2012-01-11 | 南京稳步自动化设备有限公司 | Power system communication server based on WEB mass communication modes and control method thereof |
-
2014
- 2014-07-03 CN CN201410314207.6A patent/CN104090792B/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101000550A (en) * | 2006-12-13 | 2007-07-18 | 青岛大学 | Remote on-line reconfiguration method of embedded system |
| CN102053850A (en) * | 2010-12-17 | 2011-05-11 | 天津曙光计算机产业有限公司 | Method for on-line FPGA logic upgrade |
| CN103313428A (en) * | 2013-06-17 | 2013-09-18 | 南京邮电大学 | Wi-Fi (wireless fidelity) communication system and Wi-Fi communication method for smartphone and upper computer in computer five-prevention system |
Non-Patent Citations (1)
| Title |
|---|
| 基于SOPC的高速数据采集系统研究与设计;马霖;《中国优秀硕士学位论文全文数据库信息科技辑》;20071015(第04期);第20－21页 * |
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