CN106485020B

CN106485020B - Processor chips emulator with nonvolatile memory

Info

Publication number: CN106485020B
Application number: CN201610929709.9A
Authority: CN
Inventors: 许国泰
Original assignee: Shanghai Huahong Integrated Circuit Co Ltd
Current assignee: Shanghai Huahong Integrated Circuit Co Ltd
Priority date: 2016-10-31
Filing date: 2016-10-31
Publication date: 2019-10-01
Anticipated expiration: 2036-10-31
Also published as: CN106485020A

Abstract

The processor chips emulator implementation method with nonvolatile memory that the invention discloses a kind of, when equivalent control logic module is in user mode, analog equivalent nonvolatile memory read-write operation timing control function and performance, cooperation SRAM memory together in equivalent product chip nonvolatile memory read-write operation timing, function and performance；When user program out of service, when user downloads code, filling or modification data to non-volatile memory by Integrated Development Environment software, monitoring module control equivalent control logic module is in monitoring mode, equivalent control logic module is equivalent to SRAM memory operation timing, function and the performance of standard together with SRAM memory, and the operation standard SRAM memory instruction that Integrated Development Environment software issues directly accesses and operate this block non-volatile memory.While the present invention can guarantee emulator functional performance authenticity, the ease for use and debugging performance of emulator are improved.

Description

Processor chips emulator with nonvolatile memory

Technical field

The present invention relates to emulator fields, emulate more particularly to a kind of processor chips with nonvolatile memory Device.

Background technique

There is the user program of User Exploitation in processor chips, in the writing and debug of user program, used work Tool is usually emulator.The emulation chip comprising product treatment device chip various functions is used in emulator, is used for analog equipment The work behavior of processor chips, emulation chip and the other components of emulator (program storage, the storage number of storage user program According to data storage and user computer on Integrated Development Environment etc.) cooperation realizes the simulation run of user program and each Item debugging function.

Many processor chips have nonvolatile memory, such as EEPROM (Electrically Erasable Programmable Read-Only Memory, Electrically Erasable Programmable Read-Only Memory) etc., it can be used as program storage or number It is used according to memory, the functional characteristic that data are not lost after realization power down.Existing emulator is usually to use SRAM (Static Random Access Memory, static random access memory) add memory equivalent control logic (to be equivalent to memory control Device, such as EEPROM Control realize the analog equivalent on the memory read/write operation timing) come in equivalent substitution product chips Nonvolatile memory, it is equivalent in function and performance with nonvolatile memory in real chip to accomplish as far as possible. But the matching used Integrated Development Environment of emulator is all the debugging software of standard, such as KEIL, MDK, IAR etc..User is logical Cross memory downloading code of the Integrated Development Environment interface into emulator, by the window memory of Integrated Development Environment to imitative It is all directly to issue destination address and data, not nationwide examination for graduation qualification by operation SRAM mode when the memory of true device fills, rewrites data If considering target memory is nonvolatile memory, need according to corresponding mode of operation and sequential operation, so existing imitative Usually there are two types of implementations for true device, and it is special that nonvolatile memory is made into pure SRAM directly in emulator by the first Property, to ensure that the Integrated Development Environment by standard can be operated directly, but it will cause nonvolatile memory in emulator and exist It is inconsistent with product chips in function, performance；Second is that SRAM adds equivalent control logic to substitute nonvolatile memory Mode, it is ensured that the consistency of functional performance, but need to ask Integrated Development Environment manufacturer or voluntarily increase in Integrated Development Environment Storage operation patch is customized for the memory location, size, characteristic of the chip of oneself.But emulator debugs user's journey The consistency for only just paying close attention to memory function performance and product chips when sequence when full speed executes user program is stopping executing User program, when by Integrated Development Environment downloading, modification and filling memory content, be not concerned with the functional performance of memory with The consistency of product chips, and more concerned with performances such as speed of download, filling response speeds, using the second way due to increasing One layer of patch layer, when downloading, filling and modification require by, can make to debug performance decline, meanwhile, need for different chips Different non-volatile memory characteristics remove production patch layer, also cumbersome.

Summary of the invention

The technical problem to be solved in the present invention is to provide a kind of processor chips emulator with nonvolatile memory, While guaranteeing emulator functional performance authenticity, the ease for use and debugging performance of emulator can be improved.

In order to solve the above technical problems, the processor chips emulator with nonvolatile memory of the invention, comprising:

Emulation chip, monitoring module, the Integrated Development Environment software being mounted on user computer；The emulation chip includes Processor, equivalent control logic module and SRAM memory；The SRAM memory by the first normal data/address bus with The connection of equivalent control logic module, the equivalent control logic module are connected by the second normal data/address bus and processor It connects, the monitoring module is connect by mode control signal line with the equivalent control logic module in the emulation chip；It is described Monitoring module carries out information transmission by debugging channel and Integrated Development Environment software；

When the equivalent control logic module is in user mode, analog equivalent nonvolatile memory read-write operation timing Control function and performance, cooperation SRAM memory together the read-write operation timing of nonvolatile memory in equivalent product chip, Function and performance；

When user program out of service, user downloads generation to non-volatile memory by Integrated Development Environment software When code, filling or modification data, monitoring module control equivalent control logic module is in monitoring mode, equivalent control logic module It is equivalent to transparent channel, SRAM memory operation timing, function and the performance of standard are equivalent to together with SRAM memory, is integrated The operation standard SRAM memory instruction that exploitation environment software is issued in a manner of the addend evidence of address directly accesses and operates this block Non-volatile memory.

Using emulator of the invention in full speed running user program, true equivalent product chip nonvolatile memory Function and performance, user program out of service, by Integrated Development Environment software to non-volatile memory download generation When code, filling or modification data, without make or using Integrated Development Environment software memory interface patch, standard is integrated to be opened Hair environment software can normally and rapidly operate code and data in non-volatile memory.Guarantee emulator function Can performance authenticity while, improve emulator ease for use and debugging performance, facilitate user program exploitation, debugging and Test, helps to improve code development efficiency.

Detailed description of the invention

The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments:

Fig. 1 is the processor chips emulator structural schematic diagram with nonvolatile memory.

Specific embodiment

As shown in Figure 1, the processor chips emulator with nonvolatile memory, including emulation chip 2, monitoring Module 3, the Integrated Development Environment software 7 being mounted on user computer.The emulation chip 2 includes processor 4, and equivalent control is patrolled Collect module 5, SRAM memory 6.The SRAM memory 6 passes through the first normal data/address bus 9 and equivalent control logic mould Block 5 connects, and the equivalent control logic module 5 is connect by the second normal data/address bus 8 with processor 4, the monitoring Module 3 is connect by mode control signal line 11 with the equivalent control logic module 5 in the emulation chip 2.The monitoring mould Block 3 carries out information transmission by debugging channel 10 and Integrated Development Environment software 7.

The Integrated Development Environment software 7 issues debugging instruction to monitoring module 3 by debugging channel 10, receives return Response.The monitoring module 3 controls equivalent control logic module 5 by mode control signal line 11 and is in user mode or monitoring Mode.When the equivalent control logic module 5 is in user mode, analog equivalent nonvolatile memory read-write operation timing control Function and performance processed, cooperation SRAM memory 6 the read-write operation timing of nonvolatile memory, function in equivalent product chip together Energy and performance；It is transparent channel function when the equivalent control logic module 5 is in monitoring mode, in function and performance quite In the second normal data being connect with processor 4/address bus 8 and the first normal data being connect with SRAM memory 6/ground Location bus 9 is directly connected.

In this way, the emulator realized, in full speed running user program, monitoring module 3 controls equivalent control logic module 5 are in user mode, equivalent control logic module 5 and the SRAM memory 6 together equivalent implementation behaviour of nonvolatile memory Make timing, function and performance, when ensure that user program executes at full speed, real simulation product chips nonvolatile memories Function and performance.When user program out of service, user is by Integrated Development Environment software 7 under non-volatile memory When carrying code, filling or modification data, monitoring module 3 controls equivalent control logic module 5 and is in monitoring mode, and equivalent control is patrolled Volume module 5 is equivalent to transparent channel, with SRAM memory 6 be equivalent to together SRAM memory operation timing of standard, function and Performance, the operation standard SRAM memory instruction that Integrated Development Environment software 7 is issued in a manner of the addend evidence of address can be direct This block non-volatile memory is accessed and operated, the memory interface of Integrated Development Environment is made or used without specific aim Patch, simultaneously as without patch layer, and with the simple SRAM memory operational order operation of most standard, standard Integrated Development Environment can very efficiently, rapidly operate code and data in non-volatile memory.

Above by specific embodiment, invention is explained in detail, but these are not constituted to of the invention Limitation.Without departing from the principles of the present invention, those skilled in the art can also make many modification and improvement, these It should be regarded as protection scope of the present invention.

Claims

1. a kind of processor chips emulator with nonvolatile memory characterized by comprising emulation chip, monitoring Module, the Integrated Development Environment software being mounted on user computer；The emulation chip includes processor, equivalent control logic mould Block and SRAM memory；The SRAM memory is connect by the first normal data/address bus with equivalent control logic module, The equivalent control logic module is connect by the second normal data/address bus with processor, and the monitoring module passes through mould Formula control signal wire is connect with the equivalent control logic module in the emulation chip；The monitoring module by debugging channel with Integrated Development Environment software carries out information transmission；

When the equivalent control logic module is in user mode, analog equivalent nonvolatile memory read-write operation timing control Function and performance, cooperation SRAM memory together in equivalent product chip nonvolatile memory read-write operation timing, function And performance；

When user program out of service, user by Integrated Development Environment software to non-volatile memory download code, When filling or modification data, monitoring module control equivalent control logic module is in monitoring mode, equivalent control logic module phase It is integrated to open when SRAM memory operation timing, function and the performance in transparent channel, being equivalent to standard together with SRAM memory It is non-that the operation standard SRAM memory instruction that hair environment software is issued in a manner of the addend evidence of address directly accesses and operate this block Volatile memory area.

2. processor chips emulator as described in claim 1, it is characterised in that: the equivalent control logic module is in prison It is transparent channel function when control mode, is equivalent in function and performance the second normal data connected to the processor/address is total Line and the first normal data connecting with SRAM memory/address bus are directly connected.

3. processor chips emulator as claimed in claim 1 or 2, it is characterised in that: the Integrated Development Environment software is logical Toning pings to monitoring module and issues debugging instruction, receives the response of return；The monitoring module passes through mode control signal Line traffic control equivalent control logic module is in user mode or monitoring mode.