CN103207824A - Simulator free from interference of resetting in monitor mode - Google Patents
Simulator free from interference of resetting in monitor mode Download PDFInfo
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- CN103207824A CN103207824A CN2012100102805A CN201210010280A CN103207824A CN 103207824 A CN103207824 A CN 103207824A CN 2012100102805 A CN2012100102805 A CN 2012100102805A CN 201210010280 A CN201210010280 A CN 201210010280A CN 103207824 A CN103207824 A CN 103207824A
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Abstract
The invention discloses a simulator free from the interference of resetting in a monitor mode. The simulator comprises a simulation chip, a monitoring module, a user program memory, a monitor program memory, an external resetting signal source and an integrated development environment module on a user computer, wherein the simulation chip comprises a processor core, a resetting control module and an internal resetting signal source; when the resetting control module outputs an effective resetting signal to the processor core, the processor core is in a reset state; when the resetting control module outputs an ineffective resetting signal, the processor core works normally; and in the monitor state, the monitoring module outputs an effective control signal to the resetting control module, and the resetting control module outputs an ineffective resetting signal to the processor core no matter whether the resetting control module receives the effective or ineffective external resetting signal or the effective or ineffective internal resetting signal. According to the simulator, not only can the working states of a processor chip of a product during various kinds of resetting be truly simulated in an operation mode, but also the abnormal influence of various kinds of resetting on the work of the simulator can be shielded in the monitor mode.
Description
Technical field
The present invention relates to a kind of processor chips emulator, particularly relate to the emulator that is not resetted under a kind of monitoring mode and disturb.
Background technology
The user program that has the user to develop in the processor chips, in the writing and debug of user program, employed instrument generally is the processor chips emulator.Emulator can analog equipment processor chips carry out the process of user program, also can be when the user needs, stop to carry out user program and take out or fill data messages such as chip register that the user pays close attention to, storer.In the existing emulator, during the work of analog equipment processor chips, the emulation chip in the emulator reads and carries out user program, and this moment, emulator and emulation chip wherein were in operational mode; When needing taking-up or filling the chip data message, data such as chip register, storer are read or write to emulation chip by the watchdog routine that reads and carry out emulator and provide, observe or revise the chip data information of paying close attention to for the user, this moment, emulator and emulation chip wherein were in monitoring mode.As can be seen, no matter be under operational mode or the monitoring mode, emulation chip all needs to read and the executive routine code, these program codes are for emulation chip and indistinction, what just read and carry out under the operational mode is the user program that the client writes, with the duty of analog equipment processor chips, and what read under the monitoring mode and carry out is the watchdog routine that emulator provides, to take out or to fill the chip data message.
A lot of processor chips all have the various chips reset function, for example detect exceptional reset (coming equivalence with the input trigger pip usually in the emulation chip), register value exceptional reset, memory access from external reset, the internal security of external interface signals and cross the border and reset etc.Accordingly, in the emulation chip of emulator, also comprise or equivalence has realized these reset functions.When emulator is in operational mode, because the function of analog equipment processor chips as far as possible, can both be responded with the effect consistent with product treatment device chip by simulated chip after these reset generation, emulation chip will reset, and resets will be again carry out user program since place, 0 address after finishing.But, when existing emulator is in monitoring mode, need emulation chip to carry out the watchdog routine that emulator provides, during with taking-up or filling chip data message, if there be any one reset (external reset, internal abnormality state reset etc.) to produce, all still can be responded by simulated chip, emulation chip will reset, and emulation chip is carried out watchdog routine cause interference or destruction.Reset signal for the outside generation, for example from coming the processor chips internal security of equivalence to detect exceptional reset etc. with the input trigger pip in the external reset of external interface, the emulation chip, can be by increasing circuit at emulator, external reset signal is shielded under monitoring mode by emulator, make external reset signal can not enter emulation chip, emulation chip is carried out watchdog routine impact, this is that existing partial simulation device disturbs a kind of disposal route of monitoring mode at resetting.But, for resetting that emulation chip inside produces, for example register value exceptional reset, memory access are crossed the border and are resetted etc., this moment, emulator can't be shielded by external circuit, but need emulator can enter monitoring mode again for the user, so that the user observes or revise the chip data information after these exceptional resets produce, be very important and significant for the debugging of these abnormality to the user.
Summary of the invention
The technical problem to be solved in the present invention provides the emulator that is not resetted under a kind of monitoring mode and disturb, can can under monitoring mode, shield various resetting to the anomalous effects of emulator work again in the duty of real simulation product treatment device chip under the operational mode when various resetting taken place.
For solving the problems of the technologies described above, the emulator that is not resetted under the monitoring mode of the present invention and disturb comprises: the Integrated Development Environment module on emulation chip, monitoring module, user program memory, watchdog routine storer, external reset signal source and the user computer; Described emulation chip comprises processor core, the control module that resets and internal reset signal source;
Described emulation chip is connected with described monitoring module by first normal data/address bus, described user program memory is connected with described monitoring module by second normal data/address bus, and described watchdog routine storer is connected with described monitoring module by the 3rd normal data/address bus; The described control module that resets is connected with described processor core by reseting signal line;
Described Integrated Development Environment module is connected with described monitoring module by the simulation communication passage, and under user's control, this Integrated Development Environment module is switched between operational mode and monitoring mode by described simulation communication passage control monitoring module;
Described internal reset signal source is connected with the described control module that resets by the internal reset signal line, and when internal reset took place, this internal reset signal source was to the control module output effective internal reset signal that resets; When not having internal reset, described internal reset signal source is to the invalid internal reset signal of control module output that resets;
Described external reset signal source is connected with the described control module that resets by the external reset signal line, and when external reset took place, effective external reset signal was exported to the control module that resets in this external reset signal source; When not having external reset, described external reset signal source is invalid external reset signal to what reset control module output;
Described monitoring module, be connected with the described control module that resets by control signal wire, when described emulator is in operational mode, monitoring module is to the invalid control signal of control module output that resets, at this moment, the control module that resets is all exported effective reset signal by reset signal alignment processor core when receiving effective external reset signal or effective internal reset signal, make processor core be in reset mode; The control module that resets is all passed through the invalid reset signal of reset signal alignment processor core output when receiving invalid external reset signal and invalid internal reset signal, make processor core be in non-reset mode; When emulator is in monitoring mode, monitoring module is to the control module output effective control signal that resets, at this moment, no matter the control module that resets receives effective or invalid external reset signal, effective or invalid internal reset signal, all pass through the invalid reset signal of reset signal alignment processor core output, make processor core be in non-reset mode.
No matter emulator is in operational mode or monitoring mode to described emulation chip, all reads and executive routine from monitoring module by described first normal data/address bus.
When emulator is in operational mode, described monitoring module reads user program and gives emulation chip by the first normal data/address bus that is connected with emulation chip from user program memory by described second normal data/address bus, reads for emulation chip.
When emulator is in monitoring mode, described monitoring module reads watchdog routine and gives emulation chip by the first normal data/address bus that is connected with emulation chip from the watchdog routine storer by described the 3rd normal data/address bus, reads for emulation chip.
Owing to adopt the emulator that is not resetted and disturb under the monitoring mode of the present invention, can be in the duty of real simulation product treatment device chip under the operational mode when various resetting taken place, can under monitoring mode, shield various resetting to the anomalous effects of emulator work again, chip data information when making the user still can observe or revise emulator pattern out of service smoothly, no matter whether emulation chip is in reset mode during pattern out of service.The present invention has improved the job stability of emulator, and effective debugging method is provided, and helps to improve the program debug work efficiency.
Description of drawings
The present invention is further detailed explanation below in conjunction with the drawings and specific embodiments:
Accompanying drawing is the emulator one example structure synoptic diagram that is not resetted under the described monitoring mode and disturb.
Embodiment
As shown in drawings, in one embodiment, the emulator that is not resetted under the described monitoring mode and disturb comprises the Integrated Development Environment 5 on emulation chip 1, monitoring module 2, user program memory 3, watchdog routine storer 4, external reset signal source 8 and the user computer.Described emulation chip 1 comprises processor core 6, the control module that resets 7 and internal reset signal source 9.
The control module that resets 7 is connected with processor core 6 by reseting signal line 17.
When the control module that resets 7 was exported effective reset signals to processor core 6, processor core 6 was in reset mode; When the control module that resets 7 was exported invalid reset signal to processor core 6, processor core 6 was not in reset mode (namely be in non-reset mode, can normally read and the executive routine state).
The control module that resets 7 is connected with internal reset signal source 9 by internal reset signal line 15.
When internal reset took place, internal reset signal source 9 was to the control module 7 output effective internal reset signals that reset; When not having internal reset, internal reset signal source 9 is to the invalid internal reset signal of control module 7 outputs that resets.
The control module that resets 7 is connected with external reset signal source 8 by external reset signal line 16.When external reset took place, external reset signal source 8 was to the effective external reset signal of control module 7 outputs that resets; When not having external reset, external reset signal source 8 is invalid external reset signal to what reset control module 7 outputs.
The control module that resets 8 is connected with monitoring module 2 by control signal wire 14.When described emulator is in operational mode, monitoring module 2 is to the invalid control signal of control module 7 outputs that resets, reset control module 7 when receiving effective external reset signal or internal reset signal this moment, all pass through reseting signal line 17 to the effective reset signal of processor core 6 outputs, the control module that resets 7 is all passed through reseting signal line 17 to the invalid reset signal of processor core 6 outputs when receiving invalid external reset signal and invalid internal reset signal.When described emulator is in monitoring mode, monitoring module 2 is to the control module 7 output effective control signal that reset, no matter the control module 7 that resets this moment receives effective or invalid external reset signal, effective or invalid internal reset signal all passes through reseting signal line 17 to the invalid reset signal of processor core 6 outputs.
Emulation chip 1 is connected with monitoring module 2 by first normal data/address bus 13.No matter described emulator is in operational mode or monitoring mode, and emulation chip 1 all reads and executive routine from monitoring module 2 by described first normal data/address bus 13.
Monitoring module 2 is connected with user program memory 3 by second normal data/address bus 11.Described emulator is in operational mode, monitoring module 2 reads user program and gives emulation chip 1 by the first normal data/address bus 13 that is connected with emulation chip 1 from user program memory 3 by described second normal data/address bus 11, reads for emulation chip 1.
Monitoring module 2 is connected with watchdog routine storer 4 by the 3rd normal data/address bus 12.When described emulator is in monitoring mode, monitoring module 2 reads watchdog routine and gives emulation chip 1 by the first normal data/address bus 13 that is connected with emulation chip 1 from watchdog routine storer 4 by described the 3rd normal data/address bus 12, reads for emulation chip 1.
Monitoring module 2 is connected with Integrated Development Environment module 5 by the simulation communication path 10, and under user's control, Integrated Development Environment module 5 is switched between operational mode and monitoring mode by described simulation communication path 10 control monitoring module 2.
Like this, when the user is in operational mode by Integrated Development Environment module 5 control emulators, monitoring module 2 is equivalent to the transparent channel between user program memory 3 and the emulation chip 1, and emulation chip 1 energy analog equipment processor chips read and carry out the state of user program.And, this moment, monitoring module 2 was invalid control signal to what reset control module 7 outputs, if inside or external reset have taken place, Simulation Control module 7 all can be to the effective reset signal of processor core 6 outputs, emulation chip 1 will reset, and this situation with product treatment device chip is consistent.When the user is in monitoring mode by Integrated Development Environment module 5 control emulators, monitoring module 2 is equivalent to the transparent channel of 1 of watchdog routine storer 4 and emulation chip, emulation chip 1 can read and carry out watchdog routine, and emulator can take out or fill chip status information.This moment, monitoring module 2 was effective control signal to what reset control module 7 outputs, no matter inside or external reset have taken place, Simulation Control module 7 is all to the invalid reset signal of processor core 6 outputs, emulation chip 1 can not reset, and emulation chip can read and carry out watchdog routine uninterruptedly.If inside or external reset have taken place under operational mode, emulation chip 1 has entered reset mode.If user's this moment wants to observe or revise chip status information, the user can enter monitoring mode by Integrated Development Environment module 5 control emulators; Monitoring module 2 will be to the effective control signal of control module 7 outputs that resets of emulation chip 1, the control module that resets 7 is to the invalid reset signal of processor core 6 outputs, emulation chip 1 can withdraw from reset mode, normally read and carry out watchdog routine, the user just can observe or revise the chip status information after the resetting before this of paying close attention to.
Below through the specific embodiment and the embodiment the present invention is had been described in detail, but these are not to be construed as limiting the invention.Under the situation that does not break away from the principle of the invention, those skilled in the art also can make many distortion and improvement, and these also should be considered as protection scope of the present invention.
Claims (4)
1. the emulator that is not resetted under the monitoring mode and disturb is characterized in that, comprising: the Integrated Development Environment module on emulation chip, monitoring module, user program memory, watchdog routine storer, external reset signal source and the user computer; Described emulation chip comprises processor core, the control module that resets and internal reset signal source;
Described emulation chip is connected with described monitoring module by first normal data/address bus, described user program memory is connected with described monitoring module by second normal data/address bus, and described watchdog routine storer is connected with described monitoring module by the 3rd normal data/address bus; The described control module that resets is connected with described processor core by reseting signal line;
Described Integrated Development Environment module is connected with described monitoring module by the simulation communication passage, is used for the described monitoring module of control and switches between operational mode and monitoring mode;
Described internal reset signal source is connected with the described control module that resets by the internal reset signal line, and when internal reset took place, this internal reset signal source was to the control module output effective internal reset signal that resets; When not having internal reset, described internal reset signal source is to the invalid internal reset signal of control module output that resets;
Described external reset signal source is connected with the described control module that resets by the external reset signal line, and when external reset took place, effective external reset signal was exported to the control module that resets in this external reset signal source; When not having external reset, described external reset signal source is invalid external reset signal to what reset control module output;
Described monitoring module, be connected with the described control module that resets by control signal wire, when described emulator is in operational mode, to the invalid control signal of control module output that resets, at this moment, the control module that resets is all exported effective reset signal to described processor core when receiving effective external reset signal or effective internal reset signal, make processor core be in reset mode; The control module that resets all to the invalid reset signal of described processor core output, makes processor core be in non-reset mode when receiving invalid external reset signal and invalid internal reset signal; When described emulator is in monitoring mode, to the described control module output effective control signal that resets, at this moment, no matter the control module that resets receives effective or invalid external reset signal, effective or invalid internal reset signal, all to the invalid reset signal of described processor core output, make processor core be in non-reset mode.
2. emulator as claimed in claim 1, it is characterized in that: no matter described emulator is in operational mode or monitoring mode to described emulation chip, all reads and executive routine from monitoring module by described first normal data/address bus.
3. emulator as claimed in claim 1, it is characterized in that: when described emulator was in operational mode, described monitoring module read user program and gives emulation chip from user program memory, read for emulation chip.
4. emulator as claimed in claim 1, it is characterized in that: when described emulator was in monitoring mode, described monitoring module read watchdog routine and gives emulation chip from the watchdog routine storer, read for emulation chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210010280.5A CN103207824B (en) | 2012-01-13 | 2012-01-13 | Not by the emulator of the interference that resets under monitoring mode |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210010280.5A CN103207824B (en) | 2012-01-13 | 2012-01-13 | Not by the emulator of the interference that resets under monitoring mode |
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| CN103207824A true CN103207824A (en) | 2013-07-17 |
| CN103207824B CN103207824B (en) | 2016-04-27 |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105676981A (en) * | 2014-11-19 | 2016-06-15 | 湖南南车时代电动汽车股份有限公司 | Reset circuit, working method and reset method |
| CN106484585A (en) * | 2016-10-31 | 2017-03-08 | 上海华虹集成电路有限责任公司 | Contact type intelligent card chip emulator |
| CN106485020A (en) * | 2016-10-31 | 2017-03-08 | 上海华虹集成电路有限责任公司 | Processor chips emulator with nonvolatile memory |
| CN106484584A (en) * | 2016-10-31 | 2017-03-08 | 上海华虹集成电路有限责任公司 | Processor chips emulator |
| CN117009128A (en) * | 2023-09-14 | 2023-11-07 | 飞腾信息技术有限公司 | Error reporting method and computer system |
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- 2012-01-13 CN CN201210010280.5A patent/CN103207824B/en not_active Expired - Fee Related
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105676981A (en) * | 2014-11-19 | 2016-06-15 | 湖南南车时代电动汽车股份有限公司 | Reset circuit, working method and reset method |
| CN105676981B (en) * | 2014-11-19 | 2022-06-21 | 湖南南车时代电动汽车股份有限公司 | Reset circuit, working method and reset method |
| CN106484585A (en) * | 2016-10-31 | 2017-03-08 | 上海华虹集成电路有限责任公司 | Contact type intelligent card chip emulator |
| CN106485020A (en) * | 2016-10-31 | 2017-03-08 | 上海华虹集成电路有限责任公司 | Processor chips emulator with nonvolatile memory |
| CN106484584A (en) * | 2016-10-31 | 2017-03-08 | 上海华虹集成电路有限责任公司 | Processor chips emulator |
| CN106485020B (en) * | 2016-10-31 | 2019-10-01 | 上海华虹集成电路有限责任公司 | Processor chips emulator with nonvolatile memory |
| CN117009128A (en) * | 2023-09-14 | 2023-11-07 | 飞腾信息技术有限公司 | Error reporting method and computer system |
| CN117009128B (en) * | 2023-09-14 | 2023-12-22 | 飞腾信息技术有限公司 | Error reporting method and computer system |
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| CN103207824B (en) | 2016-04-27 |
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