CN113127291A

CN113127291A - Micro-controller

Info

Publication number: CN113127291A
Application number: CN202011560867.4A
Authority: CN
Inventors: 马纪哲
Original assignee: Nuvoton Technology Corp
Current assignee: Nuvoton Technology Corp
Priority date: 2019-12-31
Filing date: 2020-12-25
Publication date: 2021-07-16
Anticipated expiration: 2040-12-25
Also published as: TW202127234A; CN113127291B; TWI709907B

Abstract

A microcontroller includes a slave device, a master device and a bus. The slave device accesses a memory device according to an access instruction. The master device executes a program code for providing an access instruction. The bus is coupled between the slave device and the master device and used for transmitting the access command to the slave device. When a trigger event occurs, the main device monitors the access state of the storage device to generate a monitoring result to an external device. The microcontroller provided by the application can monitor the access state of the storage device per se.

Description

Micro-controller

Technical Field

The present invention relates to a microcontroller, and more particularly, to a microcontroller for monitoring the access status of a memory device.

Background

With the progress of technology, the types and functions of electronic devices are increasing. A microcontroller is generally provided in the electronic device. The microcontroller operates according to program code within itself. When the program code has an error (bug), the microcontroller will not work properly.

Disclosure of Invention

The invention provides a microcontroller, which comprises a slave device, a master device and a bus. The slave device accesses a memory device according to an access instruction. The master device executes a program code for providing an access instruction. The bus is coupled between the slave device and the master device and used for transmitting the access command to the slave device. When a trigger event occurs, the main device monitors the access state of the storage device to generate a monitoring result to an external device. The microcontroller provided by the application can monitor the access state of the storage device per se.

Drawings

FIG. 1 is a schematic diagram of an operating system of the present invention.

FIG. 2 is a schematic diagram of a microcontroller according to the present invention.

FIG. 3 is another schematic diagram of the microcontroller according to the present invention.

FIG. 4 is an internal schematic view of a memory module according to the present invention.

[ notation ] to show

100: an operating system;

110: an external device;

120: a connector;

130. 200 and 300: a microcontroller;

121. 122: a transmission interface;

210. 310, 320: a master device;

220. 230, 330, 340: a slave device;

240. 250, 350, 60: a bus bar;

CM₁、CM₂: an access instruction;

CM₃: a control instruction;

221. 231, 232, 331, 341: a storage device;

260. 270: a memory;

370: a storage module;

PRC: program code;

S_M、S_MA、S_MB: monitoring the result;

411 to 418: a repository;

addr _ A, addr _ B: an address parameter set;

DA _ A, DA _ B: a set of data parameters;

TMS _ A, TMS _ B: a time parameter set;

RorW _ A, RorW _ B: a parameter set is accessed.

Detailed Description

In order to make the objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below. The present description provides various examples to illustrate the technical features of various embodiments of the present invention. The arrangement of the elements in the embodiments is for illustration and not for limiting the invention. In addition, the reference numerals in the embodiments are partially repeated to simplify the description, and do not indicate the relationship between the different embodiments.

FIG. 1 is a schematic diagram of an operating system of the present invention. As shown, the operating system 100 includes an external device 110, a connector 120, and a microcontroller 130. The external device 110 communicates with the microcontroller 130 through the connector 120. In the present embodiment, the external device 110 analyzes the parameter set provided by the microcontroller 130 for the user to determine whether the flow of the program code in the microcontroller 130 is correct. The present invention does not limit the kind of the external device 110. In one possible embodiment, the external device 110 is a computer device. In this case, the external device 110 may install a monitoring application code. When the user starts the monitoring application code, the external device 110 presents an analysis screen for the user to refer to according to the parameter set provided by the microcontroller 130.

The connector 120 is coupled between the external device 110 and the microcontroller 130. In the present embodiment, the connector 120 has

transmission interfaces

121 and 122. The transmission interface 121 is used for coupling with an external device 110. The transmission interface 122 is coupled to the microcontroller 130. The present invention does not limit the kind of the transmission interfaces 121 and 122. In one embodiment, the transmission interface 121 is a USB interface. In other embodiments, the class of transport interface 121 may be the same or different from the class of transport interface 122.

In one embodiment, the connector 120 is used as a key. The microcontroller 130 is accessible to the external device 110 through the connector 120. Similarly, the microcontroller 130 provides the relevant parameter set to the external device 110 through the connector 120. In other embodiments, the connector 120 may be integrated into the external device 110 or the microcontroller 130. In some embodiments, the connector 120 may be omitted. In this example, the external device 110 and the microcontroller 130 have encryption and decryption functions to improve security.

The microcontroller 130 communicates with the external device 110 via the connector 120. When a trigger event occurs, the micro-controller 130 monitors the access status of its internal memory device and provides a monitoring result to the external device 110. In one possible embodiment, the triggering event is a button (not shown) being pressed. The button may be located in the microcontroller 130. When the user presses the button, the microcontroller 130 performs a monitoring operation. In another possible embodiment, the triggering event is the external device 110 issuing a monitoring trigger. In this example, when the user starts a monitoring application code of the external device 110, the external device 110 issues the monitoring trigger to command the microcontroller 130 to perform a monitoring operation.

Since the user knows the access status of the storage device inside the microcontroller 130 according to the monitoring result of the microcontroller 130, the user can quickly find the abnormal part and perform debugging (debug) when the access status of the storage device inside the microcontroller 130 does not meet the preset value. Furthermore, since the micro-controller 130 only monitors the access status of the storage device, the data flow can be known only by the binary file (binary file), and the external device 110 can reconstruct the program code flow executed by the micro-controller 130 without having the source code (source code), thereby simplifying the debugging process.

FIG. 2 is a schematic diagram of a microcontroller according to the present invention. As shown, the microcontroller 200 includes a master device 210,

slave devices

220, 230, and

buses

240 and 250. The master device 210 executes a program code PRC for issuing an access command CM₁And CM₂. The present invention does not limit the architecture of the master device 210. Any device that can issue an access command can be used as the master device 210. In one embodiment, the master device 210 is a Central Processing Unit (CPU) or a Peripheral Memory Direct Access controller (PDMA con)troller)。

The slave device 220 according to the access command CM₁ A memory device 221 is accessed. The present invention does not limit the number of storage devices. In other embodiments, slave device 220 has more storage devices. In addition, in the embodiment, the storage device 221 is integrated into the slave device 220, but the invention is not limited thereto. In other embodiments, storage 221 may be independent of slave 220. In one possible embodiment, the storage device 221 includes at least one register (register).

The slave 230 according to the access instruction CM₂At least one of the

memory devices

231 and 232 is accessed. In other embodiments, slave device 230 has more or fewer storage devices. In addition, in the embodiment, the

storage devices

231 and 232 are integrated into the slave device 230, but the invention is not limited thereto. In other embodiments, at least one of

storage devices

231 and 232 is independent of slave device 230. In one possible embodiment, both

storage devices

231 and 232 include at least one register (register).

The present invention is not limited to the types of

slave devices

220 and 230. The class of slave device 220 may be the same or different from the class of slave device 230. In one embodiment, the slave device 220 is an Inter-Integrated Circuit (I2C) Circuit, and the slave device 220 is a Universal Asynchronous Receiver/Transmitter (UART).

The bus 240 is coupled between the slave device 220 and the master device 210 for transmitting an access command CM₁. The bus 250 is coupled between the slave 230 and the master 210 for transmitting the access command CM₂. The present invention does not limit the types of the

busbars

240 and 250. The types of

buses

240 and 250 correspond to the transmission interfaces of

slave devices

220 and 230, respectively. For example, assume that the slave device 220 is an I2C circuit and the slave device 220 is a UART. In this example, bus 240 is an I2C bus and bus 250 is a UART bus.

The number of slave devices of microcontroller 200 is not limited by the present invention. In other embodiments, microcontroller 200 may have more or fewer slaves. In this case, the number of buses also varies with the number of slave devices. For example, when microcontroller 200 has more slaves, microcontroller 200 may need to send commands to the slaves using more busses.

In other embodiments, microcontroller 200 also includes a memory 260. The memory 260 is used for storing program codes PRC. When the master device 210 executes the program code PRC, the master device 210 generates an access command CM₁And CM₂For accessing the

memory devices

221, 231 and 232. When a first trigger event occurs, the master device 210 monitors the access status of the

memory devices

221, 231 and 232 to generate a monitoring result S_M. In one possible embodiment, the master device 210 directly outputs the monitoring result S_MTo the external device 110. In another possible embodiment, microcontroller 200 further includes a memory 270. The memory 270 is used for storing the monitoring result S_M. In this example, the master device 210 first monitors the result S_MStored in the memory 270, and reads the monitoring result S of the memory 270 at a specific time_MAnd outputs a monitoring result S_MTo the external device 110. The present invention is not limited to the kind of the memory 270. The memory 270 may be a volatile memory or a non-volatile memory. In one embodiment, memory 270 is a Static Random Access Memory (SRAM).

In other embodiments, the master device 210 stops monitoring the access status of the

memory devices

221, 231 and 232 when a second trigger event occurs. In this case, the master device 210 may read the monitoring result S stored in the memory 270_MAnd providing a monitoring result S_MTo the external device 110. The external device 110 analyzes the monitoring result S_MFor generating an analysis frame. In this example, the user determines whether the flow of the program code PRC is correct according to the analysis screen of the external device 110.

The present invention does not limit the types of the first and second trigger events. In one possible embodiment, the host device 210 determines whether a first button (not shown) and a second button (not shown) are pressed. When the first button is pressed, a first triggering event is indicated. Thus, the master device 210 performs a monitoring operation. When the second button is pressed, a second triggering event is indicated. Therefore, the master device 210 stops the monitoring operation.

In another embodiment, when the user turns on a monitoring application (not shown) of the external device 110 and clicks a monitoring option, the external device 110 sends a first trigger signal to the main device 210. The master device 210 starts monitoring the access status of the

memory devices

221, 231 and 232 according to the first trigger signal. When the user clicks a stop option, the external device 110 sends a second trigger signal to the main device 210. The master device 210 stops monitoring the access status of the

memory devices

221, 231 and 232 according to the second trigger signal. In this example, when the user clicks a transmission option, the external device 110 sends a third trigger signal to the main device 210. The master device 210 reports the monitoring result S according to the third trigger signal_M. In other embodiments, the second trigger event is indicated to occur when the master device 210 executes program code and reaches a breakpoint. Therefore, the master device 210 stops monitoring.

FIG. 3 is another schematic diagram of the microcontroller according to the present invention. FIG. 3 is similar to FIG. 2 except that the access instruction CM of FIG. 3₁And CM₂Are provided by different master devices, such as 310 and 320. In the present embodiment, the master device 310 transmits the access command CM via the bus 350₁To the slave device 330. The slave 330 CM according to the access instruction₁The storage device 331 is accessed. In addition, the master device 320 transmits the access command CM through the bus 360₂To the slave device 340. The slave device 340 according to the access instruction CM₂The storage device 341 is accessed.

In one embodiment, the master device 310 is a central processing unit and the master device 320 is a PDMA controller. When a first trigger event occurs, the master device 310 monitors the access operation of the slave device 330 to generate a monitoring result S_MA. When a second trigger event occurs, the master device 310 stops monitoring the access operation of the slave device 330. When a third trigger event occurs, the master device 320 monitors the access operation of the slave device 340 to generate a monitoring resultS_MB. When a fourth trigger event occurs, the master device 320 stops monitoring the access operation of the slave device 340.

In one embodiment, the

master devices

310 and 320 may store the monitoring result S respectively_MAAnd S_MBIn the memory module 370. In other embodiments, at least one of the

master devices

310 and 320 directly outputs the monitoring result (S)_MAAnd/or S_MB) To an external device. In this embodiment, the storage module 370 has at least one memory (not shown) for storing the program codes and the monitoring result S_MAAnd S_MB. Since the characteristics of the

slave devices

330, 340 and the

buses

350, 360 are similar to those of the

slave devices

220, 230 and the

buses

240, 250 in FIG. 2, the description thereof is omitted.

In some embodiments, the master device 310 executes a program code stored in the memory module 370 to generate a control command CM₃. The master device 320 according to the control command CM₃Generating an access instruction CM₂For accessing the slave device 340. In other embodiments, the master device 320 directly executes the program code stored in the memory module 370 to generate the access command CM₂. In one embodiment, the storage module 370 has a non-volatile memory for storing program codes. In this case, the storage module 370 further has a volatile memory for storing the monitoring result S_MAAnd S_MB. In other embodiments, the result S is monitored_MAAnd S_MBIs stored in non-volatile memory.

Fig. 4 is an internal schematic diagram of the memory module 370 of the present invention. As shown, the memory module 370 includes banks 411-418, but is not intended to limit the present invention. In other embodiments, storage module 370 has more or fewer storage banks. In the present embodiment, the banks 411-414 are used to store the monitoring result S_MAThe storage libraries 415-418 are used to store the monitoring result S_MB。

The storage bank 411 is used for storing the monitoring result S_MAThe address parameter set addr _ a in. For example, when the master device 310 stores data for addresses 0x4007003x and 0x4007000c of the storage device 331On fetch, the master device 310 records addresses 0x4007003x and 0x4007000c in the bank 411.

The storage library 412 is used for storing the monitoring result S_MAThe data parameter set DA _ a. In one embodiment, the data parameter set DA _ A represents the data values written by the master device 310 at addresses 0x4007003x and 0x4007000c or the data values obtained by the master device 310 at addresses 0x4007003x and 0x4007000 c.

The storage 413 is used for storing the monitoring result S_MAAnd (3) time parameter set TMS _ A. For example, the master device 310 may access the memory device 331 during the fifth cycle and the sixth cycle of an operating frequency. In this example, the master 310 records a cycle5 and a cycle6 in the store 413.

The storage library 414 is used for storing the monitoring result S_MAThe access parameter set RorW _ a. For example, the master device 310 may write two data into the storage devices 331 separately. Thus, the storage bank 414 records Write operations Write twice.

The storage libraries 415-418 record the monitoring results S respectively_MBThe address parameter set addr _ B, the data parameter set DA _ B, the time parameter set TMS _ B and the access parameter set RorW _ B. Since the characteristics of the address parameter group addr _ B, the data parameter group DA _ B, the time parameter group TMS _ B, and the access parameter group RorW _ B are the same as the characteristics of the address parameter group addr _ a, the data parameter group DA _ a, the time parameter group TMS _ a, and the access parameter group RorW _ a, no further description is given. In other embodiments, the address parameter set addr _ B, the data parameter set DA _ B, the time parameter set TMS _ B and the access parameter set RorW _ B may be stored in the storage banks 411-414, respectively.

Since the master device only monitors the access status of the memory devices (e.g., registers), the result S is monitored_MAAnd S_MBBut a purely binary format file. Analyzing the monitoring result S by an external device (e.g. a computer device)_MAAnd S_MBThe method is used for generating an easy-to-read format (such as a waveform) for a user to refer to, so that the user can quickly know whether the flow of the program code is correct or not.

Unless otherwise defined, all terms (including technical and scientific terms) used herein are to be interpreted as commonly understood by one of ordinary skill in the art to which this invention belongs. Moreover, unless expressly stated otherwise, the definition of a term in a general dictionary shall be construed as being consistent with its meaning in the context of the relevant art and shall not be construed as an idealized or overly formal definition.

Although the present invention has been described with reference to the preferred embodiments, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention. For example, the systems, devices, or methods described in the embodiments of the present invention may be implemented in hardware, software, or a combination of hardware and software. Therefore, the protection scope of the present invention is subject to the claims.

Claims

1. A microcontroller, comprising:

a first slave device accessing a first storage device according to a first access instruction;

a master device executing a program code for providing the first access instruction; and

a first bus coupled between the first slave device and the master device for transmitting the first access command to the first slave device;

when a first trigger event occurs, the main device monitors the access state of the first storage device to generate a monitoring result to an external device.

2. The microcontroller of claim 1, further comprising:

a second slave device accessing a second storage device according to a second access instruction; and

and a second bus coupled between the second slave device and the master device for transmitting the second access command to the second slave device, wherein the master device executes the program code to provide the second access command.

3. The microcontroller of claim 2 wherein the first slave device is a universal asynchronous receiver/transmitter and the second bus is an inter-integrated circuit bus.

4. The microcontroller of claim 1 wherein the master device is a cpu or a dma.

5. The microcontroller of claim 1, further comprising:

and the memory is used for storing the monitoring result.

6. The microcontroller of claim 1 wherein the master device outputs the monitoring result directly to the external device.

7. The microcontroller of claim 1, further comprising:

a button, when pressed, indicating the occurrence of the first triggering event.

8. The microcontroller of claim 1 wherein the master device stops monitoring the access status of the first memory device when a second triggering event occurs.

9. The microcontroller of claim 8 wherein the program code has a breakpoint that indicates the occurrence of the second trigger event when the master executes to the breakpoint.

10. The microcontroller according to claim 8, wherein the first and second trigger events are caused by the external device.