TWI709907B - Micro-controller - Google Patents

Abstract

A microcontroller including a slave device, a main device and a bus is provided. The slave device accesses a storage device according to an access command. The main device executes a program code to provide the access command. The bus is coupled between the slave device and the main device to transmit the access command to the slave. When a trigger event occurs, the main device detects the access state of the storage device to generate a detection result to an external device.

Description

Microcontroller

The present invention relates to a microcontroller, in particular to a microcontroller that monitors the access status of its own storage device.

With the advancement of technology, there are more and more types and functions of electronic devices. Generally, an electronic device has a microcontroller inside. The microcontroller operates according to its own internal code. When there is a bug in the code, the microcontroller will not work properly.

The present invention provides a microcontroller including a slave device, a master device and a bus. The slave device accesses a storage device according to an access command. The main device executes a program code to provide access instructions. The bus is coupled between the slave device and the master device for sending access commands to the slave device. When a trigger event occurs, the main device monitors the access state of the storage device to generate a monitoring result to an external device.

In order to make the purpose, features and advantages of the present invention more comprehensible, embodiments are specifically listed below, in conjunction with the accompanying drawings, for detailed description. The specification of the present invention provides different examples to illustrate the technical features of different embodiments of the present invention. Wherein, the configuration of each element in the embodiment is for illustrative purposes, and is not intended to limit the present invention. In addition, the part of the repetition of the drawing symbols in the embodiments is for simplifying the description and does not mean the relevance between different embodiments.

Figure 1 is a schematic diagram of the operating system of the present invention. As shown in the figure, the operating system 100 includes an external device 110, a connector 120, and a microcontroller 130. The external device 110 communicates with the microcontroller 130 through the connector 120. In this embodiment, the external device 110 analyzes the parameter set provided by the microcontroller 130 for the user to determine whether the flow of the program code inside the microcontroller 130 is correct. The invention does not limit the type of external device 110. In a possible embodiment, the external device 110 is a computer device. In this example, the external device 110 may install a monitoring application. When the user opens the monitoring application, the external device 110 presents an analysis screen for the user's reference according to the parameter set provided by the microcontroller 130.

The connector 120 is coupled between the external device 110 and the microcontroller 130. In this embodiment, the connector 120 has transmission interfaces 121 and 122. The transmission interface 121 is used for coupling to the external device 110. The transmission interface 122 is used for coupling to the microcontroller 130. The invention does not limit the types of transmission interfaces 121 and 122. In one possible embodiment, the transmission interface 121 is a USB interface. In other embodiments, the type of the transmission interface 121 may be the same or different from the type of the transmission interface 122.

In one possible embodiment, the connector 120 serves as a key. Through the connector 120, the external device 110 can access the microcontroller 130. Similarly, through the connector 120, the microcontroller 130 provides the relevant parameter set to the external device 110. In other embodiments, the connector 120 may be integrated in the external device 110 or the microcontroller 130. In some embodiments, the connector 120 may be omitted. In this example, the external device 110 and the microcontroller 130 have encryption and decryption functions to improve security.

The microcontroller 130 communicates with the external device 110 through the connector 120. When a trigger event occurs, the microcontroller 130 monitors the access status of its internal storage device and provides a monitoring result to the external device 110. In one possible embodiment, the trigger event refers to a button (not shown) being pressed. The button may be provided in the microcontroller 130. When the user presses the button, the microcontroller 130 performs a monitoring operation. In another possible embodiment, the trigger event refers to the external device 110 issuing a monitoring trigger. In this example, when the user starts a monitoring application of the external device 110, the external device 110 issues the monitoring trigger to command the microcontroller 130 to perform a monitoring operation.

Since the user knows the access status of the storage device inside the microcontroller 130 according to the monitoring result of the microcontroller 130, when the access status of the storage device inside the microcontroller 130 does not meet the preset value, the user It can quickly find out the anomaly and perform debugging (debug). Furthermore, since the microcontroller 130 only monitors the access status of the storage device, it only needs a binary file to know the data flow, and the external device 110 does not need to have a source code (source code), the program flow executed by the microcontroller 130 can be reconstructed, thus simplifying the debugging process.

Figure 2 is a schematic diagram of the microcontroller of the present invention. As shown in the figure, the microcontroller 200 includes a master device 210, slave devices 220 and 230, and bus bars 240 and 250. The main device 210 executes a program code PRC to issue access commands CM ₁ and CM ₂ . The present invention does not limit the structure of the main device 210. Any device that can issue access commands can serve as the master device 210. In one possible embodiment, the main device 210 is a central processing unit (CPU) or a Peripheral Direct Memory Access controller (PDMA controller).

The slave device 220 accesses a storage device 221 according to the access command CM ₁ . The invention does not limit the number of storage devices. In other embodiments, the slave device 220 has more storage devices. In addition, in this embodiment, the storage device 221 is integrated in the slave device 220, but it is not used to limit the present invention. In other embodiments, the storage device 221 may be independent of the slave device 220. In a possible embodiment, the storage device 221 includes at least one register.

The slave device 230 accesses at least one of the storage devices 231 and 232 according to the access command CM ₂ . In other embodiments, the slave device 230 has more or less storage devices. In addition, in this embodiment, the storage devices 231 and 232 are integrated in the slave device 230, but they are not used to limit the present invention. In other embodiments, at least one of the storage devices 231 and 232 is independent of the slave device 230. In a possible embodiment, the storage devices 231 and 232 both include at least one register.

The invention does not limit the types of slave devices 220 and 230. The type of the slave device 220 may be the same or different from the type of the slave device 230. In a possible embodiment, the slave device 220 is an Inter-Integrated Circuit (I2C) circuit, and the slave device 220 is a Universal Asynchronous Receiver/Transmitter (UART).

The bus 240 is coupled between the slave device 220 and the master device 210 for transmitting the access command CM ₁ . The bus 250 is coupled between the slave device 230 and the master device 210 for transmitting the access command CM ₂ . The present invention does not limit the types of bus bars 240 and 250. The types of bus bars 240 and 250 correspond to the transmission interfaces of the slave devices 220 and 230, respectively. For example, suppose that the slave device 220 is an I2C circuit, and the slave device 220 is a UART. In this example, the bus 240 is an I2C bus, and the bus 250 is a UART bus.

The present invention does not limit the number of slave devices of the microcontroller 200. In other embodiments, the microcontroller 200 may have more or fewer slave devices. In this example, the number of buses will also vary with the number of slave devices. For example, when the microcontroller 200 has more slave devices, the microcontroller 200 needs to use more buses to transmit commands to the slave devices.

In other embodiments, the microcontroller 200 further includes a memory 260. The memory 260 is used to store the program code PRC. When the main device 210 executes the program code PRC, the main device 210 generates access commands CM ₁ and CM ₂ to access the storage devices 221, 231 and 232. When a first trigger event occurs, the main device 210 monitors the access status of the storage devices 221, 231, and 232 to generate a monitoring result S _M. In a possible embodiment, the main device 210 directly outputs the monitoring result _SM to the external device 110. In another possible embodiment, the microcontroller 200 further includes a memory 270. The memory 270 is used to store the monitoring result S _M. In this embodiment, the master device 210 first monitoring result S _M stored in the memory 270, and at a particular time, reads the monitoring result memory 270 of the S _M, S _M and outputs the monitoring result to the external device 110. The invention does not limit the type of the memory 270. The memory 270 may be a volatile memory or a non-volatile memory. In one possible embodiment, the memory 270 is a static random access memory (SRAM).

In other embodiments, when a second trigger event occurs, the main device 210 stops monitoring the access status of the storage devices 221, 231, and 232. In this example, the main device 210 may read the monitoring result S _M stored in the memory 270 and provide the monitoring result S _M to the external device 110. The external device 110 analyzes the monitoring result S _M to generate an analysis screen. In this example, the user judges whether the flow of the code PRC is correct according to the analysis screen of the external device 110.

The invention does not limit the types of the first and second trigger events. In one possible embodiment, the main device 210 determines whether a first button (not shown) and a second button (not shown) are pressed. When the first button is pressed, it indicates that the first trigger event has occurred. Therefore, the main device 210 performs a monitoring operation. When the second button is pressed, it indicates that a second trigger event has occurred. Therefore, the main device 210 stops the monitoring operation.

In another possible embodiment, when the user opens a monitoring application (not shown) of the external device 110 and clicks a monitoring option, the external device 110 sends a first trigger signal to the main device 210. The main device 210 starts to monitor the access status of the storage devices 221, 231, and 232 according to the first trigger signal. When the user clicks a stop option, the external device 110 sends a second trigger signal to the main device 210. The main device 210 stops monitoring the access status of the storage devices 221, 231, and 232 according to the second trigger signal. In this example, when the user clicks a transmission option, the external device 110 sends a third trigger signal to the main device 210. The main device 210 reports the monitoring result S _M according to the third trigger signal. In other embodiments, when the main device 210 executes the program code and reaches a breakpoint, it means that the second trigger event occurs. Therefore, the main device 210 stops monitoring.

Figure 3 is another schematic diagram of the microcontroller of the present invention. Figure 3 is similar to Figure 2, except that the access commands CM ₁ and CM _{2 in} Figure 3 are provided by different master devices (such as 310 and 320). In this embodiment, the master device 310 transmits the access command CM ₁ to the slave device 330 through the bus 350. Device 330 from accessing storage access command CM ₁ The apparatus 331. In addition, the master device 320 transmits the access command CM ₂ to the slave device 340 through the bus 360. The slave device 340 accesses the storage device 341 according to the access command CM ₂ .

In a possible embodiment, the main device 310 is a central processing unit, and the main device 320 is a PDMA controller. When a first trigger event occurs, the master device 310 monitors the access operation of the slave device 330 to generate a monitoring result S _MA . When a second trigger event occurs, the master device 310 stops monitoring the access operation of the slave device 330. When a third trigger event occurs, the master device 320 monitors the access operation of the slave device 340 to generate a monitoring result S _MB . When a fourth trigger event occurs, the master device 320 stops monitoring the access operation of the slave device 340.

In a possible embodiment, the main devices 310 and 320 may store the monitoring results S _MA and S _MB in the memory module 370, respectively. In other embodiments, at least one of the main devices 310 and 320 directly outputs the monitoring results (S _MA and/or S _MB ) to an external device. In this embodiment, the memory module 370 has at least one memory (not shown) for storing program codes and monitoring results S _MA and S _MB . Since the characteristics of the slave devices 330, 340, and the bus bars 350, 360 are similar to the characteristics of the slave devices 220, 230, and the bus bars 240, 250 in FIG. 2, they will not be repeated.

In some embodiments, the main device 310 executes a program code stored in the memory module 370 to generate a control command CM ₃ . The master device 320 generates an access command CM ₂ according to the control command CM ₃ to access the slave device 340. In other embodiments, the main device 320 directly executes the program code stored in the memory module 370 to generate the access command CM ₂ . In one possible embodiment, the memory module 370 has a non-volatile memory for storing program codes. In this example, the memory module 370 further has a volatile memory for storing the monitoring results S _MA and S _MB . In other embodiments, the monitoring results S _MA and S _MB are stored in non-volatile memory.

FIG. 4 is an internal schematic diagram of the memory module 370 of the present invention. As shown in the figure, the memory module 370 includes banks 411 to 418, but it is not used to limit the present invention. In other embodiments, the memory module 370 has more or less memory banks. In this embodiment, the memory banks 411 to 414 are used to store the monitoring results S _MA , and the memory banks 415 to 418 are used to store the monitoring results S _MB .

Memory 411 for storing the monitoring result S _MA in the address parameters addr_A. For example, when the host device 310 accesses the data at the addresses 0x4007003x and 0x4007000c of the storage device 331, the host device 310 records the addresses 0x4007003x and 0x4007000c in the memory bank 411.

The memory bank 412 is used to store the data parameter group DA_A in the monitoring result S _MA . In one possible embodiment, the data parameter group DA_A is used to represent the data values written to the addresses 0x4007003x and 0x4007000c by the master device 310, or the data values obtained by the master device 310 from the addresses 0x4007003x and 0x4007000c.

Memory 413 for storing the monitoring result S _MA in the time parameter set TMS_A. For example, the main device 310 may access the storage device 331 in the fifth and sixth cycles of an operating frequency. In this example, the main device 310 records the cycles cycle5 and cycle6 in the memory bank 413.

Memory 414 for storing the results of the monitoring in the access parameter S _MA group RorW_A. For example, the main device 310 may write two data into the storage device 331 respectively. Therefore, the memory bank 414 records two write operations Write.

Memory banks 415~418 respectively record the address parameter group addr_B, data parameter group DA_B, time parameter group TMS_B and access parameter group RorW_B in the monitoring result S _MB . Since the characteristics of the address parameter group addr_B, data parameter group DA_B, time parameter group TMS_B, and access parameter group RorW_B are the same as those of address parameter group addr_A, data parameter group DA_A, time parameter group TMS_A, and access parameter group RorW_A, Therefore, I will not repeat it. In other embodiments, the address parameter group addr_B, the data parameter group DA_B, the time parameter group TMS_B, and the access parameter group RorW_B may be stored in the memory banks 411 to 414, respectively.

Since the main device only monitors the access status of the storage device (such as a register), the monitoring results S _MA and S _MB are only simple binary format files. External devices (such as computer equipment) analyze the monitoring results S _MA and S _MB to generate easy-to-read formats (such as waveforms) for users to refer to, so that users can quickly know whether the code flow is correct.

Unless otherwise defined, all vocabulary (including technical and scientific vocabulary) herein belong to the general understanding of persons with ordinary knowledge in the technical field of the present invention. In addition, unless clearly stated, the definition of a word in a general dictionary should be interpreted as consistent with the meaning in the article in its related technical field, and should not be interpreted as an ideal state or an overly formal voice.

Although the present invention has been disclosed as above in preferred embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the relevant technical field can make some changes and modifications without departing from the spirit and scope of the present invention. . For example, the system, device, or method described in the embodiments of the present invention can be implemented in a physical embodiment of hardware, software, or a combination of hardware and software. Therefore, the protection scope of the present invention shall be subject to those defined by the attached patent application scope.

100: Operating system 110: External device 120: Connector 130, 200, 300: Microcontroller 121, 122: Transmission interface 210, 310, 320: Master device 220, 230, 330, 340: Slave device 240, 250, 350 , 60: bus CM ₁ , CM ₂ : access command CM ₃ : control command 221, 231, 232, 331, 341: storage device 260, 270: memory 370: memory module PRC: code S _M , S _MA , S _MB : monitoring results 411~418: memory addr_A, addr_B: address parameter group DA_A, DA_B: data parameter group TMS_A, TMS_B: time parameter group RorW_A, RorW_B: access parameter group

Figure 1 is a schematic diagram of the operating system of the present invention. Figure 2 is a schematic diagram of the microcontroller of the present invention. Figure 3 is another schematic diagram of the microcontroller of the present invention. Figure 4 is an internal schematic diagram of the memory module of the present invention.

200: Microcontroller

210: main device

220, 230: slave device

240, 250: bus

CM ₁ , CM ₂ : Access commands

221, 231, 232: storage device

260, 270: Memory

PRC: Code

S _M : Monitoring result

Claims (10)

A microcontroller including: A first slave device accesses a first storage device according to a first access command; A host device executes a program code to provide the first access command; and A first bus, coupled between the first slave device and the master device, for transmitting the first access command to the first slave device; Wherein, when a first trigger event occurs, the main device monitors the access state of the first storage device to generate a monitoring result to an external device. The microcontroller as described in item 1 of the scope of patent application includes: A second slave device accesses a second storage device according to a second access command; and A second bus, coupled between the second slave device and the master device, for transmitting the second access command to the second slave device, wherein the master device executes the code to provide the The second access instruction. For the microcontroller described in item 2 of the scope of patent application, the first slave device is a universal asynchronous transceiver (UART), and the second bus is an inter-integrated circuit bus (I2C bus). ). As for the microcontroller described in the first item of the patent application, the main device is a central processing unit (CPU) or a peripheral memory direct access device (PDMA). The microcontroller as described in item 1 of the scope of patent application includes: A memory is used to store the monitoring result. For the microcontroller described in item 1 of the scope of patent application, the main device directly outputs the monitoring result to the external device. The microcontroller as described in item 1 of the scope of patent application includes: A button, when the button is pressed, it means that the first trigger event occurs. For the microcontroller described in claim 1, wherein when a second trigger event occurs, the main device stops monitoring the access state of the first storage device. For the microcontroller described in item 8 of the scope of patent application, the program code has a breakpoint, and when the main device executes to the breakpoint, it means that the second trigger event occurs. The microcontroller described in item 8 of the scope of patent application, wherein the first and second trigger events are caused by the external device.

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