CN102436385A - Online updating device for configuration files of programmable logic device - Google Patents
Online updating device for configuration files of programmable logic device Download PDFInfo
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- CN102436385A CN102436385A CN2011103619467A CN201110361946A CN102436385A CN 102436385 A CN102436385 A CN 102436385A CN 2011103619467 A CN2011103619467 A CN 2011103619467A CN 201110361946 A CN201110361946 A CN 201110361946A CN 102436385 A CN102436385 A CN 102436385A
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Abstract
The invention discloses an online updating device for configuration files of a programmable logic device. In an upper computer, a program package module extracts and updates the configuration files and converts the updated configuration files into standard test and programming language (STAPL) standard input files required by a Jam STAPL Byte-Code Player analysis program. A data transmitting module converts the STAPL standard input files into internet signals and transmits the internet signals to cables, and then a data receiving buffer module receives jbc files from the cables, verifies the files and preserves the files in a program storage. A program analysis module extracts configuration information of the programmable logic device from the jbc files in a data storage, the configuration information of the programmable logic device can be converted into joint test action group (JTAG) data stream through the Jam STAPL Byte-Code Player program in the program analysis module and transmits the JTAG data stream to a general purpose input/output (GPIO) simulation JTAG module. A GPIO of a microprocessor is used as a standard JTAG interface, configuration time sequence of a standard JTAG is simulated through a driving program, only four GPIOs of the microprocessor are used, and a hardware circuit is very simple. Compared with a traditional configuration method of the programmable logic device, cost is reduced greatly.
Description
Technical field
The invention belongs to configuration file renewal technology field, more specifically, relate to a kind of PLD configuration file online updating device.
Background technology
PLD has two kinds of main types: field programmable gate array (FPGA) and CPLD (CPLD); Its scale is big; Complex structure; Belonging to the large scale integrated circuit scope, is a kind of user according to self particular demands and the digital integrated circuit of constitutive logic function voluntarily.
The conventional arrangement method of PLD generally is to develop software by integrated, generates corresponding file destination, accomplishes objective chip, the i.e. programming of PLD through the specific download cable.Common this configuration mode all needs special configuration plug-in and the support that develops software, and carries out the general more complicated of configuration of PLD through these methods, and it is very inconvenient to operate.
Summary of the invention
The objective of the invention is to overcome the deficiency of prior art, a kind of simple, easy to operate PLD configuration file online updating device that disposes is provided.
For realizing the foregoing invention purpose, PLD configuration file online updating device of the present invention comprises:
Host computer comprises program package module and data transmission blocks in the host computer;
The PLD that the program package module is used for development environment acquiescence is produced more new configuration file is the file of .jbc form according to the assembled package that requires of standard testing and programming language (STAPL) standard;
Data transmission blocks is used for the file with program package module assembled package, and promptly the .jbc file converts network signal into through ethernet control chip and sends on the netting twine;
One microprocessor and program storage; Comprise Data Receiving buffer module, program parsing module and GPIO (General Purpose Input Output in the microprocessor; General I/O) simulation JTAG (Joint Test Action Group, joint test behavior tissue) module;
The Data Receiving buffer module is used to receive the .jbc file that transmits from host computer on the netting twine, and it is errorless to guarantee to transmit to accomplish the data check function, and it is deposited in the program storage;
The program parsing module is used to obtain the .jbc file of depositing in the program storage, and uses inner Jam STAPL Byte-Code Player analysis program the configuration information that comprises in this .jbc file to be resolved to the data stream of JTAG standard;
GPIO simulation JTAG module uses 4 GPIO pins of microprocessor to be connected to the standard jtag interface of PLD, and uses the JTAG signal wire of these 4 pins as configuration of programmable logic devices; GPIO simulation JTAG module at first receives the JTAG normal data that is come by the transmission of program parsing module and flows; Therefrom obtain corresponding JTAG level information; And according to the level information call driver; The output level of GPIO pin in the control microprocessor, the level output of micro processor leg need be satisfied the sequential requirement of JTAG, and PLD is realized the online updating of configuration file according to this level information.
Goal of the invention of the present invention is achieved in that
In host computer; The program package module extracts the more new configuration file of the PLD that is generated by the development environment acquiescence; Be that .pof is the configuration file of suffix; And be translated in the Jam STAPL Byte-Code Player analysis program STAPL standard files input that needs, i.e. .jbc file; Data transmission blocks is network signal with the .jbc file conversion and sends on the netting twine; So just, accomplished the work of host computer to generation, encapsulation and the transmission of PLD configuration file.
In PLD configuration file online updating device of the present invention; Use the microprocessor control data to receive buffer module and receive .jbc file from netting twine; And file carried out verification guaranteeing in transmission course, not having Presence information to lose, and this document is saved in the program storage; The program parsing module extracts the PLD configuration information in the .jbc file in the data-carrier store; And convert the configuration information of PLD to the JTAG data stream, and this JTAG data stream is passed to GPIO simulation JTAG module through the inner Jam STAPL Byte-Code Player program of program parsing module.
GPIO simulation JTAG module uses 4 GPIO of microprocessor to be connected to the standard jtag interface of PLD, and uses the JTAG signal wire of these 4 GPIO mouths as the PLD of configuration; GPIO simulation JTAG module at first receives the JTAG normal data that is come by the transmission of program parsing module and flows; And therefrom obtain corresponding JTAG level information; And according to the level information call driver; The output level of GPIO pin in the control microprocessor, the level output of micro processor leg need be satisfied the sequential requirement of JTAG, and PLD is realized the online updating of configuration file according to this level information.
The JTAG standard comprises 4 necessary signals, is respectively TMS, TDI, TDO and TCK; Tms signal is used to control the conversion of the state machine of JTAG for the output signal; The TDI signal is similarly the output signal; It is the interface of JTAG scan chain data input; All will be input to the data of particular register all through one one bit serial input of TDI interface; The TDO signal is the device feedback signal of returning from the JTAG scan chain, and TCK is the clock signal control signal of JTAG input, and the input/output function of TMS, TDI and TDO signal all is to be undertaken directly actuated by tck signal; The signal demand of TMS, TDI latchs and outputs to the JTAG scan chain at the negative edge of tck clock signal, and the TDO feedback signal is effective at the rising edge of tck clock signal; The key that GPIO simulation JTAG module realizes is that the output of the GPIO pin output signal of microprocessor need satisfy the sequential requirement of JTAG configuration;
The present invention has the following advantages:
1, uses the jtag interface of the GPIO of microprocessor as standard; And the configuration sequential through driver mock standard JTAG, only used the GPIO of 4 common microprocessors, hardware circuit is very simple; Collocation method with conventional programmable logic device is compared, and cost reduces a lot.
2, use Jam STAPL Player that the configuration file of the PLD of input is resolved; What configuration file used is standard testing and programming language (STAPL) language; Specialized application makes configuration file have versatility in the configuration file of describing PLD, is independent of the production firm of PLD; Can be applied to the configuration effort of multiple PLD, and just not be confined to a kind of configuration of PLD.
PLD configuration file online updating device of the present invention is core with the microprocessor; Use the common GPIO of microprocessor and the JTAG pin of PLD to be connected; Realized the renewal of PLD configuration file with software mode, hardware cost is low, and layoutprocedure is simple, easy to operate; Renewal speed is fast, can be applied to the chip of multiple PLD.
Description of drawings
Fig. 1 is a kind of embodiment theory diagram of PLD configuration file online updating device of the present invention;
Fig. 2 is the schematic diagram that Jam Player is configured PLD;
Fig. 3 is the sequential chart of GPIO simulation JTAG module.
Embodiment
Describe below in conjunction with the accompanying drawing specific embodiments of the invention, so that those skilled in the art understands the present invention better.What need point out especially is that in the following description, when perhaps the detailed description of known function and design can desalinate main contents of the present invention, these were described in here and will be left in the basket.
Embodiment
Fig. 1 is a kind of embodiment theory diagram of PLD configuration file online updating device of the present invention.
As shown in Figure 1, in the present embodiment, simple and easy Monobus interface conversion circuit comprises:
Comprise program package module 101 and data transmission blocks 102 in the host computer, the Software Development Platform of this device is a QUARTUS II development environment.
The PLD configuration file that program package module 101 produces the compiling of QUARTUS II development environment acquiescence, promptly the .pof file is the file of .jbc form according to the assembled package that requires of standard testing and programming language (STAPL) standard; Data transmission blocks 102 is with the file of program package module assembled package, and promptly the .jbc file is converted into the network level signal, through ethernet control chip it is carried out conversion process, and finally outputs on the netting twine;
Microprocessor adopts ARM9 series main flow microprocessor.Include Data Receiving buffer module 201, program parsing module 202, GPIO simulation JTAG module 203 in the ARM9 microprocessor; Receive the .jbc file that buffer module 201 receives from netting twine by ARM9 microprocessor control data, and file is carried out verification guaranteeing in transmission course, not having Presence information to lose, and this document is saved in the data-carrier store 3; Program parsing module 202 extracts the PLD configuration information that the .jbc file comprises in the data-carrier store; And convert the configuration information of PLD to the JTAG data stream through the inner Jam STAPL Byte-Code Player program of program parsing module 202; And receive the configuration information of the PLD that comprises the JTAG data stream through GPIO simulation JTAG module 203; Obtain corresponding JTAG level information in this configuration information; Through the Linux driver in the system, the pin output level of control ARM9 microprocessor is passed PLD 4 with this JTAG level signal through 4 GPIO oral instructions of ARM9 microprocessor at last; And from the pin state of ARM9 microprocessor, obtain from PLD 4 simultaneously and obtain feedback information; So just, accomplished work, realized configuration and function renewal, under the prerequisite of not using the special configuration plug-in unit PLD 4 to reception, parsing and the configuration of preparation file; Configuration file to PLD advances to upgrade, and increases work efficiency.
In the present embodiment, generate the configuration file of .pof, convert the configuration file of .jbc form into, and be sent to data transmission blocks 102 as input through program package module 101 by the compiling of the development environment Quartus II development environment of altera corp.
It is the ARM9 chip of S3C2440A that said ARM microprocessor adopts the model of Samsung company.This chip comprises equipment on the abundant sheet, and is integrated with a memory management unit (MMU), supports multiple embedded OS.
Said program storage links to each other with the ARM9 microprocessor for a slice capacity is the K9F2G08U0A chip of 256MB.
The development that in this device, needs to accomplish comprises:
1, transplants based on the built-in Linux operating system of S3C2440A processor: comprise the transplanting that Bootstrap Commissioning Program u-boot, embedded Linux system kernel, yaffs2 file system and ethernet controller drive.U-boot, linux kernel and yaffs2 file system all are stored in the program storage;
2, in order to realize the online updating of PLD configuration file, need the Jam STAPL Byte-Code Player of altera corp be transplanted in the linux system in this device;
3, because Jam STAPL Byte-Code Player operates in the built-in Linux operating system, cannot directly visit the GPIO pin register of ARM9 chip, input/output function that also can't the direct control pin.Therefore need write driver for the GPIO pin that is used for jtag interface, the character device that these pin package can be read and write for Jam Player based on Linux.
Fig. 2 is the schematic diagram that Jam Player is configured PLD.
In the environment of built-in Linux, use the jtag interface configuration of programmable logic devices, must use standard testing and programming language (Standard Test And Programming Language, STAPL) standard.STAPL is a kind of programming language of describing the programmable logic device configuration file that is specifically designed to, and standard is organized to set up by EIA/JEDEC.The configuration file that uses STAPL to describe has versatility, is independent of PLD production firm.
In the present embodiment, as shown in Figure 2, program parsing module 202 is the Jam resolver, uses Jam STAPL to be configured and comprises two parts: Jam Player and Jam configuration file.Jam Player operates in the microprocessor, reads the Jam configuration file and resolves the content of expressing in the configuration file, on jtag interface 401, produces the binary data stream that is used to dispose and reads feedback data.
In the present embodiment; Said PLD 4 is the MAX II of ALTERA company family chip EPM1270; That Jam Player uses is the Jam STAPL Byte-Code Player of ALTERA company 2.2 versions; The Jam compiler of this version is supported the code of Windows, Dos and these three kinds of platforms of UNIX, and employed Jam configuration file format is .jbc.In the present embodiment, application platform is a built-in Linux, therefore must customize accordingly and transplant according to platform.
Use the order of Jam Player configuration EPM1270 to be " PROGRAM "; Its child-operation that comprises has: DO_BLANK_CHECK, DO_VERIFY, DO_SECURE, DO_DISABLE_ISP_CLAMP, DO_BYPASS_CFM, DO_BYPASS_UFM, DO_REAL_TIME_ISP, DO_READ_USERCODE, DO_INIT_CONFIGURATION, wherein each child-operation all is made up of several corresponding orders.
Jam Player at first analyzes the content that comprises in the .jbc file; Extract the child-operation that wherein comprises according to configure order; Successively the child-operation that is comprised is converted into the stereotyped command of STAPL; And the stereotyped command of this STAPL is converted into EPM1270 disposes needed JTAG traffic flow information, then the JTAG traffic flow information is outputed on the jtag interface of EPM1270 through the IO interface function.After EPM1270 receives the JTAG data stream; Content according to instruction; Dispensing unit (CFM) and subscriber unit (UFM) to inside are programmed one by one; And feedback information turned back to through the TDO interface among the GPIO of ARM9, Jam Player judges the process of configuration through the feedback information of JTAG data stream before relatively and EPM1270 and controls, and exports current states information.When the instruction in all child-operations that comprise in the .jbc file all be performed finish after, the EPM1270 config update finishes.
Fig. 3 is the sequential chart of GPIO simulation JTAG module.
The JTAG standard comprises 4 necessary signals, is respectively TMS, TDI, TDO and TCK; Tms signal is used to control the conversion of the state machine of JTAG for the output signal; The TDI signal is similarly the output signal; It is the interface of JTAG scan chain data input; All will be input to the data of particular register and all import through TDI interface serial-by-bit; The TDO signal is the device feedback signal of returning from the JTAG scan chain, and TCK is the clock signal control signal of JTAG input, and the input/output function of TMS, TDI and TDO signal all is directly actuated through tck signal; The signal demand of TMS, TDI latchs and outputs to the JTAG scan chain at the negative edge of tck clock signal, and the TDO feedback signal is effective at the rising edge of tck clock signal;
The key that GPIO simulation JTAG module 203 realizes is that the output of the GPIO pin GPB5～8 output signals of ARM9 microprocessor need satisfy the sequential requirement of JTAG configuration;
t
JCPBe the tck clock cycle, must be greater than 55.5ns, t
JCHBe the high level time of TCK, must be greater than 20ns, t
JCLBe the low level time of TCK, must be greater than 20ns, t
JPSUBe the port Time Created of JTAG, need be greater than 8ns, t
JPHBe the retention time of jtag port, need be greater than 10ns, t
JPZXTime representation is after tck signal is effective, and the interval of TDO signal from the high resistant to effective time must not surpass 15ns, t
JPCOTime representation tck signal effectively after, the switching time of TDO signal is the highest must not to surpass 15ns, t
JPXZTime representation is after tck signal is effective; The retention time of TDO signal is the highest must not to surpass 15ns; Because the operating system of using in this device is built-in Linux, the pin that in application program, can't directly handle ARM9 is operated, through writing the input/output function of Linux driver control arm processor pin; And the function of using accurate timing is controlled the sequential of input and output; Be used to control the input and output of ARM9 processor GPIO mouth, make it reach EPM1270 and dispose desired sequential, accomplish the renewal of EPM1270 configuration file with this.
Although above the illustrative embodiment of the present invention is described; So that the technician in present technique field understands the present invention, but should be clear, the invention is not restricted to the scope of embodiment; To those skilled in the art; As long as various variations appended claim limit and the spirit and scope of the present invention confirmed in, these variations are conspicuous, all utilize innovation and creation that the present invention conceives all at the row of protection.
Claims (2)
1. a PLD configuration file online updating device is characterized in that, comprising:
Host computer comprises program package module and data transmission blocks in the host computer;
The PLD that the program package module is used for development environment acquiescence is produced more new configuration file is the file of .jbc form according to the assembled package that requires of standard testing and programming language (STAPL) standard;
Data transmission blocks is used for the file with program package module assembled package, and promptly the .jbc file converts network signal into through ethernet control chip and sends on the netting twine;
Microprocessor and program storage comprise Data Receiving buffer module, program parsing module and GPIO simulation JTAG module in the microprocessor;
The Data Receiving buffer module is used to receive the .jbc file that transmits from host computer on the netting twine, and it is errorless to guarantee to transmit to accomplish the data check function, and it is deposited in the program storage;
The program parsing module is used to obtain the .jbc file of depositing in the program storage, and uses inner JamSTAPL Byte-Code Player analysis program the configuration information that comprises in this .jbc file to be resolved to the data stream of JTAG standard;
GPIO simulation JTAG module uses 4 GPIO pins of microprocessor to be connected to the standard jtag interface of PLD, and uses the JTAG signal wire of these 4 pins as configuration of programmable logic devices; GPIO simulation JTAG module at first receives the JTAG normal data that is come by the transmission of program parsing module and flows; Therefrom obtain corresponding JTAG level information; And according to the level information call driver; The output level of GPIO pin in the control microprocessor, the level output of micro processor leg need be satisfied the sequential requirement of JTAG, and PLD is realized the online updating of configuration file according to this level information.
2. PLD configuration file online updating device according to claim 1; It is characterized in that; Described microprocessor is the ARM9 chip; And transplant built-in Linux operating system therein: comprise the transplanting that Bootstrap Commissioning Program u-boot, embedded Linux system kernel, yaffs2 file system and ethernet controller drive, wherein Bootstrap Commissioning Program U-boot, go into formula linux system kernel, the yaffs2 file system all is stored in the program storage;
Jam STAPL Byte-Code Player is transplanted in the (SuSE) Linux OS; And write driver for the GPIO pin that is used for jtag interface, the character device that these pin package can be read and write for Jam Player based on Linux.
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| CN104035757A (en) * | 2013-03-07 | 2014-09-10 | 深圳国人通信有限公司 | MIPS-based (microprocessor without interlocked piped stages-based) U-boot (universal boot loader) transplantation implementing method |
| CN105224345A (en) * | 2014-05-28 | 2016-01-06 | 株洲变流技术国家工程研究中心有限公司 | A kind of programmable logic device (PLD) remote update system and method thereof |
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| CN107621819B (en) * | 2017-08-24 | 2019-12-27 | 电子科技大学 | FPGA configuration file online updating device of three-dimensional acoustic logging instrument |
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| CN108519889A (en) * | 2018-03-22 | 2018-09-11 | 深圳华中科技大学研究院 | A kind of FPGA program remote upgrading system and methods based on JTAG standard |
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| CN109491959A (en) * | 2018-10-27 | 2019-03-19 | 北京控制与电子技术研究所 | A kind of programmable logic device configurator |
| CN109491959B (en) * | 2018-10-27 | 2023-03-21 | 北京控制与电子技术研究所 | Programmable logic device configurator |
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| CN109885327A (en) * | 2019-02-28 | 2019-06-14 | 新华三信息安全技术有限公司 | A kind of method and device upgrading CPLD |
| CN111752780A (en) * | 2020-06-12 | 2020-10-09 | 苏州浪潮智能科技有限公司 | Self-adaptive interconnection system and method for JTAG (joint test action group) components of server |
| US11953550B2 (en) | 2020-06-12 | 2024-04-09 | Inspur Suzhou Intelligent Technology Co., Ltd. | Server JTAG component adaptive interconnection system and method |
| CN113590166A (en) * | 2021-08-02 | 2021-11-02 | 腾讯数码（深圳）有限公司 | Application program updating method and device and computer readable storage medium |
| CN113590166B (en) * | 2021-08-02 | 2024-03-26 | 腾讯数码（深圳）有限公司 | Application program updating method and device and computer readable storage medium |
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