CN105137800A - PLC cooperative control device based on SOPC technology - Google Patents
PLC cooperative control device based on SOPC technology Download PDFInfo
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- CN105137800A CN105137800A CN201510578385.4A CN201510578385A CN105137800A CN 105137800 A CN105137800 A CN 105137800A CN 201510578385 A CN201510578385 A CN 201510578385A CN 105137800 A CN105137800 A CN 105137800A
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B15/00—Systems controlled by a computer
- G05B15/02—Systems controlled by a computer electric
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B2219/00—Program-control systems
- G05B2219/20—Pc systems
- G05B2219/22—Pc multi processor system
- G05B2219/2225—Communication, CPU accesses own I-O and next CPU over dual port memory
Abstract
The invention relates to a PLC cooperative control device based on an SOPC technology. The device comprises two parts, a hardware system and a software system. The hardware system comprises an upper computer and a lower computer. The upper computer is formed by a Nios II soft core processor module, a memory module and a peripheral module, wherein the Nios II soft core processor module is composed of a CPU module, a TIMER0 module, a TIMER1 module, an UART module and a JTAG module. The software system comprises an embedded uC/OS-II real-time operating system, upper computer software, lower computer software and a virtual soft core PLC. The PLC cooperative control device is high in modifiability and transportability; the uC/OS-II real-time operating system is added, the operation real-time performance of the system is ensured, customized IP cores can be compiled according to specific requirements, and the required specific functions can be added freely; in addition, the number of I/O ports can be conveniently increased or reduced, so that the system is high in expansion and maintenance performance.
Description
Technical field
The present invention relates to a kind of industry control FPGA (Field Programmable Gate Array) Embedded Soft Core PLC device, particularly relate to the device that a kind of collaborative PLC based on SOPC technology realizes industrial automatic control.
Background technology
Because conventional hardware PLC technology is to outer closure, the PLC hardware platform of each production firm is different, and the PLC language of support is not identical yet, and the agreement communicated each other is also completely different with bus.Therefore, along with the development of computer technology, people have recognized the versatility of hardware PLC, compatibility and the bad fast development that govern PLC of expansion gradually.Meanwhile, along with the technological transformation of a cigarette industry new round, a large amount of novel tobacco throwing equipment is introduced from the foreign cigarette machine equipment company of state such as German HAUNI, Italian Garbuio, and equipment manufacturer takes blockade on new techniques for the PLC program of key equipment and the means such as even to encrypt.Therefore, cigarette machine function is improved, need to seek a kind of new solution to break through the problems such as the blockade of conventional P LC internal processes and outside versatility, poor compatibility.
Past, the many hardware platforms based on ASIC design of the exploitation of logic controller system, and the programmable system on chip occurred in recent years (SOPC) solution obtains industry and payes attention to widely and develop rapidly.SOPC not only makes PCB design more simple, and design is more flexible, develops more efficient.Its feature is its programmability, namely utilizes the programmability of field programmable gate array (FPGA) device to carry out SOC (systemonchip) design.SOPCBuilder provides a guide for each element, utilizes this guide to be easy to customization elements function, and can add NiosII soft-core processor, Peripheral Interface etc. easily in a design by this guide.In order to microprocessor core, peripherals, storer and other IP kernel are connected with each other, SOPCBuilder can generate the required logic such as on-chip bus and bus arbiter automatically.SOPCBuilder achieves the exploitation of embedded system various aspects in an instrument, comprise design and the checking of software, therefore use SOPC technology convenient on FPGA, the various complex logic of fast custom to control, and logic in conventional P LC is transplanted or transferred on FPGA device realize.
Summary of the invention
The object of the present invention is to provide a kind of PLC Collaborative Control device based on SOPC technology.Conventional hardware PLC is assisted to complete Automated condtrol as virtual PLC the FPGA based on SOPC technology, the shortcoming of the single control of solution conventional P LC, customizes various function by SOPC and conventional P LC real-time communication reaches the object controlling same equipment when double-core is worked in coordination with.
In order to realize above-mentioned object, present invention employs following technical scheme:
Based on the PLC Collaborative Control device of SOPC technology, this device comprises hardware system and software systems two parts, described hardware system comprises host computer and slave computer, and described host computer operates on PC, completes PLC program and is compiled into object code and code transfer work, described slave computer uses AlteraFPGA (EP2c35F672c6) NiosII embedded software processor to be hardware platform, is communicated by RS232 agreement with between host computer, described slave computer is by NiosII soft-core processor module, memory module and peripheral module composition, wherein NiosII soft-core processor module is by CPU module, TIMER0 module, TIMER1 module, UART module and JTAG module composition, when FPGA is configured, by the soft nuclear parameter of SOPCBuilder system synthesis software set NiosII, and TIMER0 module is set, TIMER1 module, UART module and JTAG module correlation parameter, the reseting address of automatic distribution each module base address and appointment NiosII processor and abnormal interrupt address, generate corresponding NiosII system, UART module can realize the transmission of host computer and FPGA and the serial communication of PLC ladder map file by using RS232 agreement, RS232 protocol conversion is become RS485 agreement by change-over circuit by JTAG module, realized and PLC communication by CP341 card again,
Described software systems comprise embedded uC/OS-II real time operating system, upper computer software, slave computer software and virtual soft core PLC;
Described embedded uC/OS-II real time operating system, after hardware system has created, carries out a MicroC/OS-II software design procedure based on NiosII processor, and uses IDE to be configured all RTOS modules;
Described upper computer software performs on PC, and primary responsibility compiling PLC ladder diagram also transmits ladder diagram file, described slave computer software is completed by design NiosIIIDE, in download hardware design, the final generating configuration file of QuartusII is in FPGA, then can set up engineering under NiosIIIDE, editor's debugging program of lower computer, in newly-built engineering, NiosIIIDE can generate the hardware abstraction layer (hardwareabstractionlayer of a customization automatically according to the configuration of SOPCBuilder correspondence system, HAL) system library, for program provides interface drive program with communicating of bottom hardware, the real time operating system environment of a transplantable uC/OS-II is also provided simultaneously,
Described virtual soft core PLC completes the core of the explanation of PLC program code, execution mechanism, be responsible for the class PLC logical program order accepting host computer transmission, the execution of control task interpreter, because virtual soft core PLC operates in uC/OS-II Preemptive kernel real-time system, mission Interpreter circulation in PLC virtual machine obtains code command and performs corresponding operation, realizes the controlling functions of PLC program to external unit.
As preferably, described CPU module selects 32 flush bonding processor NiosII modules based on RISC technology.
As preferably, the FLASH memory that described memory module selects power failure data not lose is to the data parameters storing application program and will preserve; The SDRAM storer selecting read or write speed higher provides running space and buffer memory intermediate processing data to uC/OS-II operating system and application program.
As preferably, described peripheral module comprises a LCD character mode lcd display screen, 4 LED, two switches.LCD is used for showing the running status of PLC virtual machine, and LED and two switch is then used for realizing the function of PLC.
As preferably, described embedded uC/OS-II real time operating system is a kind of hard real-time kernel of trying to be the first based on priority.
The present invention, owing to selecting NiosII soft-core processor module to be core and utilizing SOPC technology to build, has very strong alterability and portability; The real-time of system cloud gray model is ensure that owing to the addition of uC/OS-II real time operating system, and customized IP core can be write according to specifically needing, specific function required for freely adding, increases simultaneously or reduces the quantity of I/O port easily, system is had more and can expand and maintainability; Again because FPGA has higher density, can integrated very large system, because this in turn increases the reliability of system.
Accompanying drawing explanation
Fig. 1 is structural representation of the present invention.
Fig. 2 is that the present invention works in coordination with PLC control schematic diagram.
Fig. 3 is present system structural representation.
Fig. 4 is hardware of the present invention composition schematic diagram.
Fig. 5 is software of the present invention composition schematic diagram.
Fig. 6 is the virtual soft core PLC task scheduling schematic diagram of the present invention.
Fig. 7 is that the virtual soft core PLC of the present invention runs sequential chart.
Embodiment
Below in conjunction with accompanying drawing, the specific embodiment of the present invention is made a detailed explanation.
As Fig. 1, the PLC Collaborative Control device based on SOPC technology comprises hardware system 1 and software systems 2 two parts; Described hardware system 1 comprises host computer 3 and slave computer 4; Described slave computer 4 is made up of NiosII soft-core processor module 5, memory module 6 and peripheral module 7, and wherein NiosII soft-core processor module 5 is made up of CPU module 8, TIMER0 module 9, TIMER1 module 10, UART module 11, JTAG module 12; Described software systems 2 comprise embedded uC/OS-II real time operating system 13, upper computer software 14, slave computer software 15, virtual soft core PLC16.
As Fig. 2, the described PLC Collaborative Control device based on SOPC technology is not changing under original PLC program, hardware connection prerequisite exactly, by fieldbus access PLC internal resource, and again pass self steering logic operation result back PLC by fieldbus, finally realize double-core Collaborative Control.
As Fig. 3, described host computer 3 operates on PC, completes PLC program and is compiled into the work such as object code and code transfer.
Described slave computer 4 uses AlteraFPGA (EP2c35F672c6) NiosII embedded software processor to be hardware platform, is communicated by RS232 agreement with between host computer 3.
As Fig. 4, described CPU module 8 selects 32 flush bonding processor NiosII modules 5 based on RISC technology.When FPGA is configured, by the soft nuclear parameter of SOPCBuilder system synthesis software set NiosII, the modules such as TIMER0 (timer) module 9, TIMER1 (timer) module 10, UART module 11, JTAG module 12 and UART (RS-232) are selected in conventional peripherals and interface module, and correlation parameter is set, the reseting address of automatic distribution each module base address and appointment NiosII processor and abnormal interrupt address, generate corresponding NiosII system.UART interface can realize the function such as the transmission of PC and FPGA and the serial communication of PLC ladder map file by using RS232 agreement.RS232 protocol conversion is become RS485 agreement by change-over circuit by JTAG12 interface, then is realized and PLC communication by CP341 card.A lot of resource concentrates in FPGA by the advantage based on SOPC technology, and the expansion and upgrading of system is more prone to, and only need add the module of corresponding function in FPGA.For self-defined peripheral hardware, can VHDL hardware language IP kernel be passed through, in SOPCBuilder, add this Custom component, and be connected by standard A valon bus.
The FLASH memory that described memory module 6 selects power failure data not lose is to the data parameters storing application program and will preserve; The SDRAM storer selecting read or write speed higher provides running space and buffer memory intermediate processing data to uC/OS-II operating system and application program.
Described peripheral module 7 comprises a LCD character mode lcd display screen, 4 LED, two switches.LCD is used for showing the running status of PLC virtual machine, and LED and two switch is then used for realizing the function of PLC.
As Fig. 5, described embedded uC/OS-II real time operating system is a kind of hard real-time kernel of trying to be the first based on priority.The real time operating system uC/OS-II that altera corp provides, it is as a part for NiosII system, after hardware system has created, carry out a MicroC/OS-II software design procedure based on NiosII processor, and use IDE to be configured all RTOS modules.Concrete operations can by clicking config option under MicroC/OS-II, and the option can selected for each option inspection is arranged, such as maximum task, timer function, timestamp function, message mailbox etc.
Described host computer procedure performs on PC, and primary responsibility compiling PLC ladder diagram also transmits ladder diagram file.Usually can by the communication using the agreements such as bus, TCP/IP, Serial Port Transmission to complete host computer and slave computer (PLC virtual machine) in industrial control system.The design adopts VC++6.0MFC to add a dialog box in the PLC compiling system application program of host computer, by adding MSComm control based on RS232 communications protocol, realizes the function that transmission PLC file performs to PLC virtual machine.
Described slave computer design is completed by design NiosIIIDE.Download the final generating configuration file of QuartusII in hardware design and, in FPGA, then can set up engineering under NiosIIIDE, editor's debugging program of lower computer.In newly-built engineering, NiosIIIDE can generate the hardware abstraction layer (hardwareabstractionlayer of a customization automatically according to the configuration of SOPCBuilder correspondence system, HAL) system library, for program provides interface drive program with communicating of bottom hardware, the real time operating system environment of a transplantable uC/OS-II is also provided simultaneously, the application program of writing so can be made to have real-time, and in uC/OS-II, also directly can call HALAPI function, so easily use C/C++ language design program.
Described virtual soft core PLC is the software systems that simulation actual computer carries out work, the same with actual computer, it has oneself central processing unit, order set, memory organization, input and output etc., can accept the instruction of order set, completes the tasks such as calculating or data processing.Virtual soft core PLC has been that PLC program code is explained, the core of execution mechanism.Its primary responsibility accepts the class PLC logical program order that host computer sends, the execution of control task interpreter.Because virtual soft core PLC operates in uC/OS-II Preemptive kernel real-time system, mission Interpreter circulation in PLC virtual machine obtains code command and performs corresponding operation, realizes the controlling functions of PLC program to external unit.For the requirement of industry control PLC control system real-time, virtual soft core PLC sequential programme is divided into fast logic task and slow logic task two parts, fast logic is only used for responsible short pulse signal, these signals mainly comprise and anxious to stop, resets, outsidely slow down and suspend to spouting, and logic then only processes general signal slowly.Management and the scheduling of two logic tasks are completed by uC/OS-II real-time system kernel.Wherein every 8 milliseconds of fast logical program performs once, and thus fast logical program should be short as far as possible.Be perform fast logical program when splitting slow logical program, wherein when Segmentation Number is n, the execution time of a circulation is 8n millisecond.Because both performance periods are different, and the data consistent in input into/output from cache district in execution sequence logical program process, to be ensured, therefore can be respectively fast logic and slow logic sets up independent logic query's buffer area.
As Fig. 6, the logic task scheduling of operational system carries out data communication by defining an overall array mode.Call start time and end time that timer record performs single pass, 8ms is spaced apart whenever the execution time, wake the Interruption function of uC/OS-II real-time system up, call kernel level task dispatcher, carry out fast scan logic next time, preserve slow logical data simultaneously in slow logical cache district.Time due to uC/OS-II task scheduling is depended on and the timeticks of system has nothing to do, so can ensure the real-time of task with the task in application program.
As Fig. 7, the working method of described virtual soft core PLC is substantially identical with traditional Soft-PLC, namely by opening UART serial ports, read in PLC execute file, stored in specified memory module, after user loads PLC logical target code, object code information, distributing system resource initialization relevant variable is read by Task_routine () thread function, then read corresponding configuration information by refresh_routine () thread function, periodic order scanning logic task also performs basic logic instruction and function command.UC/OS-II performs this two threads by using kernel OSTimeDlyHMSM () delay function cycle alternation, ensures the performance period of each thread.PLC dummy machine system is in each scan period, pass through hardware abstraction layer, read in the state of exterior I/O device register, then the RefreshIO () function in refresh_routine () thread is called, upgrade the state of variable range corresponding with this register in hardware abstraction layer, the logic operation result of internal system is updated to external switch equipment by the standard interface provided finally by hardware abstraction layer (HAL).
The foregoing is only preferred embodiment of the present invention, all equalizations done according to the present patent application the scope of the claims change and modify, and all should belong to the covering scope of patent of the present invention.Usable range of the present invention is not only confined to tobacco industry and controls, and can expand other functions and be applied to more complicated industrial control field.In non-precise hard_drawn tuhes field, also can use independent for the present invention as PLC.
Claims (5)
1., based on a PLC Collaborative Control device for SOPC technology, this device comprises hardware system (1) and software systems (2) two parts, it is characterized in that: described hardware system (1) comprises host computer (3) and slave computer (4), described host computer (3) operates on PC, completes PLC program and is compiled into object code and code transfer work, described slave computer (4) uses AlteraFPGA (EP2c35F672c6) NiosII embedded software processor to be hardware platform, is communicated by RS232 agreement with between host computer (3), described slave computer (4) is by NiosII soft-core processor module (5), memory module (6) and peripheral module (7) composition, wherein NiosII soft-core processor module (5) is by CPU module (8), TIMER0 module (9), TIMER1 module (10), UART module (11) and JTAG module (12) composition, when FPGA is configured, by the soft nuclear parameter of SOPCBuilder system synthesis software set NiosII, and TIMER0 module (9) is set, TIMER1 module (10), UART module (11) and JTAG module (12) correlation parameter, the reseting address of automatic distribution each module base address and appointment NiosII processor and abnormal interrupt address, generate corresponding NiosII system, UART module (11) can realize the transmission of host computer (3) with FPGA and the serial communication of PLC ladder map file by using RS232 agreement, RS232 protocol conversion is become RS485 agreement by change-over circuit by JTAG module (12), realized and PLC communication by CP341 card again,
Described software systems (2) comprise embedded uC/OS-II real time operating system (13), upper computer software (14), slave computer software (15) and virtual soft core PLC(16);
Described embedded uC/OS-II real time operating system (13), after hardware system has created, carries out a MicroC/OS-II software design procedure based on NiosII processor, and uses IDE to be configured all RTOS modules;
Described upper computer software (14) performs on PC, and primary responsibility compiling PLC ladder diagram also transmits ladder diagram file, described slave computer software (15) is completed by design NiosIIIDE, in download hardware design, the final generating configuration file of QuartusII is in FPGA, then can set up engineering under NiosIIIDE, editor's debugging program of lower computer, in newly-built engineering, NiosIIIDE can generate the hardware abstraction layer (hardwareabstractionlayer of a customization automatically according to the configuration of SOPCBuilder correspondence system, HAL) system library, for program provides interface drive program with communicating of bottom hardware, the real time operating system environment of a transplantable uC/OS-II is also provided simultaneously,
Described virtual soft core PLC(16) complete that PLC program code is explained, the core of execution mechanism, be responsible for the class PLC logical program order accepting host computer transmission, the execution of control task interpreter, because virtual soft core PLC operates in uC/OS-II Preemptive kernel real-time system, mission Interpreter circulation in PLC virtual machine obtains code command and performs corresponding operation, realizes the controlling functions of PLC program to external unit.
2. a kind of PLC Collaborative Control device based on SOPC technology according to claim 1, is characterized in that, CPU module (8) selects 32 flush bonding processor NiosII modules (5) based on RISC technology.
3. a kind of PLC Collaborative Control device based on SOPC technology according to claim 1, it is characterized in that, the FLASH memory that memory module (6) selects power failure data not lose is to the data parameters storing application program and will preserve; The SDRAM storer selecting read or write speed higher provides running space and buffer memory intermediate processing data to uC/OS-II operating system and application program.
4. a kind of PLC Collaborative Control device based on SOPC technology according to claim 1, it is characterized in that, peripheral module (7) comprises a LCD character mode lcd display screen, 4 LED, two switches, LCD is used for showing the running status of PLC virtual machine, and LED and two switch is then used for realizing the function of PLC.
5. a kind of PLC Collaborative Control device based on SOPC technology according to claim 1, is characterized in that, embedded uC/OS-II real time operating system is a kind of hard real-time kernel of trying to be the first based on priority.
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| CN105549522A (en) * | 2015-12-16 | 2016-05-04 | 中国电子信息产业集团有限公司第六研究所 | SPARC (Scalable Processor ARChitecture) CPU based PLC (Programmable Logic Controller) embedded real-time safety control operation system and operation method thereof |
| CN105843659A (en) * | 2016-03-17 | 2016-08-10 | 深圳市金玺智控技术有限公司 | Implementation method and system of embedded C compiler |
| CN107340995A (en) * | 2016-04-29 | 2017-11-10 | 中国铁道科学研究院 | A kind of traction control applied software development system |
| CN109144732A (en) * | 2018-09-05 | 2019-01-04 | 合肥英睿系统技术有限公司 | A kind of multi-core CPU implementation method and relevant apparatus based on FPGA |
| CN110850802A (en) * | 2019-11-30 | 2020-02-28 | 信联科技(南京)有限公司 | Safe intelligent programmable logic controller supporting cloud data interconnection |
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| CN112445344A (en) * | 2019-08-29 | 2021-03-05 | 中核核电运行管理有限公司 | Acquisition control device based on Ethernet interface DCC keyboard |
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| CN116663075A (en) * | 2023-07-24 | 2023-08-29 | 信联科技(南京)有限公司 | Industrial control programming platform safety communication method and system based on cryptographic algorithm |
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| CN105549522A (en) * | 2015-12-16 | 2016-05-04 | 中国电子信息产业集团有限公司第六研究所 | SPARC (Scalable Processor ARChitecture) CPU based PLC (Programmable Logic Controller) embedded real-time safety control operation system and operation method thereof |
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| CN107340995A (en) * | 2016-04-29 | 2017-11-10 | 中国铁道科学研究院 | A kind of traction control applied software development system |
| CN107340995B (en) * | 2016-04-29 | 2020-11-20 | 中国铁道科学研究院 | Traction control application software development system and optimization compiling method for platform-independent codes |
| CN110914768A (en) * | 2017-06-07 | 2020-03-24 | 布鲁克斯自动化(德国)有限公司 | Method for controlling PLC using PC program |
| CN110914768B (en) * | 2017-06-07 | 2023-06-30 | 布鲁克斯自动化(德国)有限公司 | Method for controlling PLC using PC program |
| CN109144732A (en) * | 2018-09-05 | 2019-01-04 | 合肥英睿系统技术有限公司 | A kind of multi-core CPU implementation method and relevant apparatus based on FPGA |
| CN109144732B (en) * | 2018-09-05 | 2022-02-11 | 合肥英睿系统技术有限公司 | Multi-core CPU (Central processing Unit) implementation method based on FPGA (field programmable Gate array) and related device |
| CN112445344A (en) * | 2019-08-29 | 2021-03-05 | 中核核电运行管理有限公司 | Acquisition control device based on Ethernet interface DCC keyboard |
| WO2021046932A1 (en) * | 2019-09-12 | 2021-03-18 | 北京东土科技股份有限公司 | Message drive method and device based on real-time operating system |
| CN110850802A (en) * | 2019-11-30 | 2020-02-28 | 信联科技(南京)有限公司 | Safe intelligent programmable logic controller supporting cloud data interconnection |
| CN113391920A (en) * | 2021-06-11 | 2021-09-14 | 上海创景信息科技有限公司 | Method and system for intelligently scheduling and managing multiple target CPUs |
| CN116663075A (en) * | 2023-07-24 | 2023-08-29 | 信联科技(南京)有限公司 | Industrial control programming platform safety communication method and system based on cryptographic algorithm |
| CN116663075B (en) * | 2023-07-24 | 2023-12-15 | 信联科技(南京)有限公司 | Industrial control programming platform safety communication method and system based on cryptographic algorithm |
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Application publication date: 20151209 |