CN107621819B - FPGA configuration file online updating device of three-dimensional acoustic logging instrument - Google Patents
FPGA configuration file online updating device of three-dimensional acoustic logging instrument Download PDFInfo
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Abstract
The invention discloses an FPGA configuration file online updating device of a three-dimensional acoustic logging instrument, which is characterized in that an FPGA updating configuration file generated by an integrated development environment is firstly utilized, and the FPGA updating configuration file is converted into a network signal by a data transmitting module and is transmitted to a network cable through an LAN (local area network) port, so that the work of generating, packaging and transmitting the FPGA configuration file by an upper computer is completed; then the adapter board receives the FPGA update configuration file by utilizing the microprocessor control data, checks, packages and adds check bits, and sends the FPGA configuration file to the control board through the McBSP interface; the control board judges whether the FPGA updating configuration file is the FPGA for updating the control board or the FPGA for acquiring the board, and then analyzes the FPGA updating configuration file into JTAG standard data flow to realize the online updating of the configuration file corresponding to the FPGA.
Description
Technical Field
The invention belongs to the technical field of configuration file updating, and particularly relates to an FPGA (field programmable gate array) configuration file online updating device suitable for a three-dimensional acoustic logging instrument.
Background
The logging of petroleum engineering is an operation with very high cost, the cost of logging equipment is less, namely millions of yuan, more, tens of millions of yuan, and the labor cost and land occupation renting cost of field logging are also very high. Therefore, stability is an important indicator for evaluating logging instruments. The mechanical and circuit structure of the three-dimensional acoustic logging instrument is more complex than that of the logging instrument developed in the past, and the working environment is special.
The FPGA updating mode of the traditional logging instrument is as follows: the method comprises the steps of firstly disassembling the logging instrument to take out a circuit module, then completing program updating work of a corresponding circuit through a simulator, and finally assembling all the modules. The traditional logging instrument is upgraded, a lot of time and manpower are wasted, and in the process of disassembling the instrument, the instrument can not work normally due to the damage of certain modules. For a three-dimensional acoustic logging instrument, a remote online updating mode needs to be designed, and the FPGA can be updated by a ground system control instrument.
Disclosure of Invention
The invention aims to overcome the defects of the prior art and provides an FPGA configuration file online updating device of a three-dimensional acoustic logging instrument, which realizes the online real-time updating of the FPGA by converting the FPGA updating configuration file into a network level signal and has the characteristics of simple configuration and convenient operation.
In order to achieve the above object, the present invention provides an on-line update apparatus for an FPGA configuration file of a three-dimensional acoustic logging instrument, comprising:
the ground control system comprises an FPGA integrated development environment, a data sending module and a ground control module;
the FPGA integrated development environment generates an FPGA update configuration file, the FPGA update configuration file is converted into a network level signal through an Ethernet control chip, the network level signal is transmitted to the adapter plate through the LAN interface by the data transmission module, and meanwhile, the ground control module transmits an online update command to the adapter plate through the serial port;
an adapter plate, including a data receiving buffer module, an external data memory and a microprocessor;
the data receiving and caching module receives the FPGA updating configuration file issued by the LAN interface, performs data verification on the FPGA updating configuration file to ensure the accuracy of data transmission, and stores the accurate FPGA updating configuration file into an external data storage; a command analysis module in the microprocessor receives and analyzes an online update command issued by a serial port, then controls the microprocessor to read and package an FPGA update configuration file from an external data storage according to the analyzed command, and then adds an identifier and a check bit and issues the FPGA update configuration file to a control panel through an McBSP interface;
the control board comprises a DSP and an FPGA; the DSP also comprises a data receiving and caching module, an RAM, a configuration file analyzing module, a GPIO simulation JTAG module (GPIO, General Purpose Input/Output; JTAG, Joint Test Action Group, combined Test Action organization), a GPIO interface and a downlink data sending module; the FPGA comprises a data coding module, a JTAG interface and a programmable logic unit;
the data receiving and caching module receives the packaged FPGA update configuration file issued by the McBSP interface, performs data verification on the FPGA update configuration file, and stores the verified file in the RAM of the control board; the configuration file analysis module reads a file from the RAM of the control panel and extracts configuration information of the FPGA, then judges whether the configuration information is used for updating the FPGA of the control panel or the FPGA of the acquisition panel, and analyzes the FPGA updating configuration file into JTAG standard data flow if the configuration information is used for updating the FPGA of the control panel; if the FPGA of the acquisition board is updated, the FPGA update configuration file is sent to a downlink data sending module;
the GPIO simulation JTAG module is connected to a standard JTAG interface of the FPGA by using pins of the GPIO interface, and the pins of the GPIO interface are used as JTAG signal lines for configuring the FPGA; the GPIO simulation JTAG module receives JTAG standard data flow, acquires corresponding JTAG level information from the JTAG standard data flow, calls a driving program according to the level information, controls the output level of pins of the GPIO interface in the DSP, and the JTAG interface performs related operation on the programmable logic unit according to the level information to complete the online updating of the FPGA configuration file;
the downlink data sending module sends an FPGA update configuration file for updating the FPGA of the acquisition board to the data coding module, the data coding module performs 8B/10B coding on the FPGA update configuration file, then sends the coded file to a downlink data channel, and simultaneously the data coding module sends a clock reference signal to the acquisition board through a clock signal channel for the acquisition board to receive a reference clock of data on the downlink data channel;
the system comprises a plurality of acquisition boards, a signal processing unit and a signal processing unit, wherein each acquisition board comprises a DSP and an FPGA; the DSP also comprises an acquisition control module, a data receiving and caching module, an RAM, a configuration file analysis module, a GPIO interface and a GPIO simulation JTAG module; the FPGA comprises a data receiving and judging module, a JTAG interface and a programmable logic unit;
the data receiving and judging module in each acquisition board receives the encoded FPGA updating configuration file from the downlink data channel by taking the clock signal on the clock signal channel as a reference, performs data verification on the FPGA updating configuration file, judges that the FPGA updating configuration file is used for the acquisition board, sends the FPGA updating configuration file to the data receiving and caching module of the acquisition board if the FPGA updating configuration file is used for the acquisition board, and discards the FPGA updating configuration file if the FPGA updating configuration file is not used for the acquisition board;
in the acquisition board, a data receiving and caching module stores a received FPGA updating configuration file into an RAM, a configuration file analyzing module reads the FPGA updating configuration file from the RAM and analyzes the FPGA updating configuration file into a standard JTAG data flow, a GPIO simulation JTAG module receives the JTAG standard data flow and acquires corresponding JTAG level information from the JTAG standard data flow, a driving program is called according to the level information to control the output level of pins of a GPIO interface in a DSP, and the JTAG interface carries out related operation on a programmable logic unit according to the level information to complete the online updating of the FPGA configuration file.
The invention aims to realize the following steps:
the invention relates to an FPGA configuration file online updating device of a three-dimensional acoustic logging instrument, which is characterized in that an FPGA updating configuration file generated by an integrated development environment is firstly utilized, and the FPGA updating configuration file is converted into a network signal by a data transmitting module and is transmitted to a network cable through an LAN (local area network) port, so that the work of generating, packaging and transmitting the FPGA configuration file by an upper computer is completed; then the adapter board receives the FPGA update configuration file by utilizing the microprocessor control data, checks, packages and adds check bits, and sends the FPGA configuration file to the control board through the McBSP interface; the control board judges whether the FPGA updating configuration file is the FPGA for updating the control board or the FPGA for acquiring the board, and then analyzes the FPGA updating configuration file into JTAG standard data flow to realize the online updating of the configuration file corresponding to the FPGA.
The FPGA configuration file online updating device of the three-dimensional acoustic logging instrument further has the following beneficial effects:
(1) the GPIO of the DSP is used as a standard JTAG interface, the configuration time sequence of the standard JTAG is simulated through a driver, only 4 common GPIOs of the DSP are used, a hardware circuit is very simple, and compared with the configuration method of the traditional FPGA, the cost is greatly reduced.
(2) The configuration file of the FPGA is analyzed by using a DirectC program, the DirectC is a source code provided by Actel company and is used for converting the configuration file of the FPGA of the company into a standard JTAG data stream, the DirectC program is implanted into a microprocessor, the updating function of the FPGA can be realized by means of an I/O interface of the microprocessor, the source code provided by an official party is high in reliability, the source code can be transplanted to different microprocessor platforms only by modifying a small amount of codes, and a large amount of time cost can be saved.
(3) The invention takes the DSP as a core, uses the common GPIO of the DSP to be connected with the JTAG pin of the FPGA, realizes the update of the configuration file of the FPGA component in a software mode, has low hardware cost, simple configuration process, convenient operation and high update speed, and can be applied to various FPGA chips.
Drawings
FIG. 1 is a schematic block diagram of an apparatus for updating an FPGA configuration file of a three-dimensional acoustic logging tool on line according to the present invention;
FIG. 2 is a functional block diagram of the surface control system, patch panel and control panel of FIG. 1;
FIG. 3 is a flow chart for parsing an FPGA update configuration file into JTAG standard data streams;
FIG. 4 is a functional block diagram of the acquisition board of FIG. 1;
FIG. 5 is a timing diagram of a GPIO analog JTAG module.
Detailed Description
The following description of the embodiments of the present invention is provided in order to better understand the present invention for those skilled in the art with reference to the accompanying drawings. It is to be expressly noted that in the following description, a detailed description of known functions and designs will be omitted when it may obscure the subject matter of the present invention.
For convenience of description, the related terms appearing in the detailed description are explained:
FPGA (Field-Programmable Gate Array): a field programmable gate array;
lan (local Area network): a local area network;
mcbsp (multichannel Buffered Serial port): multi-channel bufferingSerial interface；
DAT: configuring data;
GPIO simulation JTAG module: GPIO, General Purpose Input Output, General Purpose Input/Output; JTAG, Joint Test Action Group, combined Test behavior organization;
ram (random Access memory): a random access memory;
dsp (digital Signal processor): a digital signal processor;
tms (test Mode select): selecting a test mode;
TDI (test Data input): inputting test data;
TDO (test Data output): outputting test data;
TCK (test clock): the clock is tested.
FIG. 1 is a schematic block diagram of an apparatus for updating an FPGA configuration file of a three-dimensional acoustic logging tool on line according to the present invention.
As shown in fig. 1, the device for updating an FPGA configuration file of a three-dimensional acoustic logging instrument on line comprises a ground control system, a patch panel, a control panel, 13 acquisition panels, a clock signal channel and a downlink data channel.
The ground control system issues an FPGA configuration file to the adapter plate through a logging cable, the adapter plate receives the FPGA configuration file through an LAN interface and issues the FPGA configuration file to the control panel through an McBSP interface, the control panel analyzes the received FPGA configuration file and judges whether the FPGA configuration file is used for the FPGA of the control panel or the FPGA of the acquisition panel, and if the FPGA configuration file is used for the FPGA of the control panel or the FPGA of the acquisition panel, the control panel completes the updating of the FPGA configuration file according to the configuration file; if the FPGA configuration file is the latter, the FPGA configuration file is issued to the 13 acquisition boards through the downlink data channel, and the acquisition boards complete the configuration update of the FPGA according to the received FPGA configuration file.
The following describes in detail a specific working flow of the device for updating the FPGA configuration file of the three-dimensional acoustic logging instrument on line with reference to fig. 1.
In this embodiment, as shown in fig. 2, the ground control system may be implemented by an upper computer, and the ground control system specifically includes: the device comprises a software development platform, a Libero IDE development environment of Actel company, a data transmission module and a ground control module.
The Libero IDE development environment generates an FPGA update configuration file, namely a DAT file, the DAT file is converted into a network level signal through an Ethernet control chip, the network level signal is finally output to a network cable through a LAN interface by a data sending module until the network level signal is transmitted to an adapter plate, and meanwhile, a ground control module transmits an online update command to the adapter plate through a serial port;
as shown in fig. 2, the adapter plate further includes: data receiving and caching module, external data memory and microprocessor.
The data receiving and caching module receives DAT file data on a network cable through the LAN port and stores the data into the external data storage, the command analysis module in the microprocessor receives and analyzes a command transmitted from the serial port, then the microprocessor is controlled to extract the DAT file from the external data storage according to the command, data packaging is carried out, and a relevant identifier and a check bit are added and issued to the control panel through the McBSP interface.
In this embodiment, the microprocessor is an ARM9 chip available from Samsung corporation as model S3C 2440A. The chip comprises abundant on-chip equipment, is integrated with a memory management unit and supports various embedded operating systems.
The external data memory is a K9F2G08U0A chip with the capacity of 256MB and is connected with the ARM9 microprocessor.
As shown in fig. 2, the control board further includes a DSP and an FPGA;
the DSP also comprises a data receiving and caching module, an RAM, a configuration file analyzing module, a GPIO simulation JTAG module (GPIO, General Purpose Input/Output; JTAG, Joint Test action group, combined Test action organization), a GPIO interface and a downlink data sending module; the FPGA comprises a data coding module, a JTAG interface and a programmable logic unit. The configuration file parsing module is used for parsing the DAT file, and is therefore a DAT file parsing module.
The data receiving and caching module receives DAT file data through the McBSP interface, completes verification work and stores the data into the RAM, the DAT file analyzing module extracts DAT file related mark information from the RAM and judges whether the DAT file is used for updating the control panel FPGA or the acquisition panel FPGA, and if the DAT file is a configuration updating file of the control panel, the DAT file analyzing module extracts FPGA configuration information in the DAT file and converts the FPGA configuration information into a standard JTAG data stream to be transmitted to the GPIO simulation JTAG module; if the data is the acquisition board FPGA configuration update file, the DAT file is sent to the downlink data sending module by the module, the DAT file is sent to a downlink data channel by the downlink data sending module through the data coding module, and meanwhile, the data coding module sends a clock reference signal to the acquisition board through the clock signal channel for the acquisition board to receive a reference clock of data on the downlink data channel.
In this embodiment, the data encoding module is implemented by an FPGA, and the other modules are implemented by a DSP. As shown in fig. 3, the DAT file analysis module reads DAT file data in the RAM, invokes an internal DirectC program to analyze a file, extracts configuration information of the FPGA, converts the DAT file data into a standard JTAG data stream, transfers the standard JTAG data stream to the GPIO simulation JTAG module, and reads feedback information from the module to determine whether configuration update is successful; the GPIO simulation JTAG module is connected to a standard JTAG interface of the FPGA by using 4 GPIOs of the DSP, and the 4 GPIO interfaces are used as JTAG signal lines of the configured FPGA; the GPIO simulation JTAG module firstly receives a JTAG standard data flow transmitted by the program analysis module, acquires corresponding JTAG level information from the JTAG standard data flow, calls a driving program according to the level information, controls the output level of a GPIO pin in the DSP, the level output of the DSP pin needs to meet the time sequence requirement of the JTAG, and the JTAG interface processes the programmable logic unit according to the level information to complete the online updating of the FPGA configuration file.
As shown in fig. 4, in this embodiment, 13 acquisition boards are used in total, each acquisition board is hooked with a clock signal channel and a downlink data channel at the same time, and each acquisition board includes a DSP and an FPGA.
The DSP also comprises an acquisition control module, a data receiving and caching module, an RAM, a configuration file analysis module, a GPIO interface and a GPIO simulation JTAG module; the FPGA comprises a data receiving and judging module, a JTAG interface and a programmable logic unit.
The data receiving and judging module receives DAT file data from the downlink data channel by taking a clock signal on the clock signal channel as a reference, completes the work of decoding and checking, ensures the intact transmission of the data, judges whether the data is an acquisition control command or a DAT file, sends the acquisition control command to the acquisition control module, and sends the DAT file to the data receiving and caching module; the acquisition control module receives an acquisition control command and controls the acquisition board to perform related acquisition work according to the command; the data receiving and caching module stores the received DAT file into the RAM; the DAT file analysis module extracts FPGA configuration information in the DAT file from the RAM and analyzes the DTA file into a standard JTAG data flow according to the information; the GPIO simulation JTAG module firstly receives a JTAG standard data stream transmitted by the program analysis module, acquires corresponding JTAG level information from the JTAG standard data stream, calls a driving program according to the level information, controls the output level of a GPIO pin in the DSP, the level output of the DSP pin needs to meet the time sequence requirement of the JTAG, and a JTAG interface processes the programmable logic unit according to the level information to complete the online updating of the FPGA configuration file;
in this embodiment, the acquisition board and the control board are DSP chips of the model TMS320F2812 of TI, and the FPGA is a chip of the model A3P1000 of Actel.
FIG. 5 is a timing diagram of a GPIO analog JTAG module.
The JTAG standard contains 4 necessary signals, TMS, TDI, TDO, and TCK; TMS signal is output signal, which is used to control the conversion of JTAG state machine; the TDI signal is also an output signal and is an interface for inputting JTAG scan chain data, all data to be input into a specific register are serially input according to bits through the TDI interface, the TDO signal is a device feedback signal returned from the JTAG scan chain, the TCK is a clock signal control signal for JTAG input and output data flow, and the input and output functions of TMS, TDI and TDO signals are directly controlled through the TCK signal; signals of TMS and TDI need to be latched and output to a JTAG scan chain at the falling edge of a TCK clock signal, and a TDO feedback signal is effective at the rising edge of the TCK clock signal;
the GPIO pin output signal of the key DSP realized by the GPIO simulation JTAG module needs to meet the time sequence requirement of JTAG configuration;
tJCPfor TCK clock period, it must be greater than 55.5ns, tJCHFor the high level time of TCK, it must be greater than 20ns, tJCLFor the low level time of TCK, it must be greater than 20ns, tJPSUIs the port setup time of JTAG, needs to be greater than 8ns, tJPHIs the retention time of the JTAG port, and needs more than 10ns, tJPZXTime means that after the TCK signal is effective, the interval from high impedance to effective time of the TDO signal must not exceed 15ns, tJPCOTime means that the transition time of the TDO signal after the TCK signal is effective should not exceed 15ns, t at mostJPXZTime means that the retention time of the TDO signal must not exceed 15ns at most after the TCK signal is active.
Although illustrative embodiments of the present invention have been described above to facilitate the understanding of the present invention by those skilled in the art, it should be understood that the present invention is not limited to the scope of the embodiments, and various changes may be made apparent to those skilled in the art as long as they are within the spirit and scope of the present invention as defined and defined by the appended claims, and all matters of the invention which utilize the inventive concepts are protected.
Claims (4)
1. The utility model provides a three-dimensional acoustic logging instrument's FPGA configuration file online updating device which characterized in that includes:
the ground control system comprises an FPGA integrated development environment, a data sending module and a ground control module;
the FPGA integrated development environment generates an FPGA update configuration file, the FPGA update configuration file is issued to the adapter plate by the data sending module through the LAN interface, and meanwhile, the ground control module issues an online update command to the adapter plate through the serial port;
an adapter plate, including a data receiving buffer module, an external data memory and a microprocessor;
the data receiving and caching module receives the FPGA updating configuration file issued by the LAN interface, performs data verification on the FPGA updating configuration file to ensure the accuracy of data transmission, and stores the accurate FPGA updating configuration file into an external data storage; a command analysis module in the microprocessor receives and analyzes an online update command issued by a serial port, then controls the microprocessor to read and package an FPGA update configuration file from an external data storage according to the analyzed command, and then adds an identifier and a check bit and issues the FPGA update configuration file to a control panel through an McBSP interface;
the control board comprises a DSP and an FPGA; the DSP also comprises a data receiving and caching module, an RAM, a configuration file analyzing module, a GPIO simulation JTAG module, a GPIO interface and a downlink data sending module; the FPGA comprises a data coding module, a JTAG interface and a programmable logic unit;
the data receiving and caching module receives the packaged FPGA update configuration file issued by the McBSP interface, performs data verification on the FPGA update configuration file, and stores the verified file in the RAM of the control board; the configuration file analysis module reads a file from the RAM of the control panel and extracts configuration information of the FPGA, then judges whether the configuration information is used for updating the FPGA of the control panel or the FPGA of the acquisition panel, and analyzes the FPGA updating configuration file into JTAG standard data flow if the configuration information is used for updating the FPGA of the control panel; if the FPGA of the acquisition board is updated, the FPGA update configuration file is sent to a downlink data sending module;
the GPIO simulation JTAG module is connected to a standard JTAG interface of the FPGA by using pins of the GPIO interface, and the pins of the GPIO interface are used as JTAG signal lines for configuring the FPGA; the GPIO simulation JTAG module receives JTAG standard data flow, acquires corresponding JTAG level information from the JTAG standard data flow, calls a driving program according to the level information, controls the output level of pins of the GPIO interface in the DSP, and processes the programmable logic unit by the JTAG interface according to the level information to complete the online updating of the FPGA configuration file;
the downlink data sending module sends an FPGA update configuration file for updating the FPGA of the acquisition board to the data coding module, the data coding module carries out 8B/10B coding on the FPGA update configuration file, then sends the coded file to a downlink data channel, and simultaneously sends a clock reference signal to the acquisition board through a clock signal channel for the acquisition board to receive a reference clock of data on the downlink data channel;
the system comprises a plurality of acquisition boards, a signal processing unit and a signal processing unit, wherein each acquisition board comprises a DSP and an FPGA; the DSP also comprises a data receiving and caching module, an RAM, a configuration file analyzing module, a GPIO interface and a GPIO simulation JTAG module; the FPGA comprises a data receiving and judging module, a JTAG interface and a programmable logic unit;
the data receiving and judging module in each acquisition board receives the encoded FPGA updating configuration file from the downlink data channel by taking the clock signal on the clock signal channel as a reference, performs data verification on the FPGA updating configuration file, judges that the FPGA updating configuration file is used for the acquisition board, sends the FPGA updating configuration file to the data receiving and caching module of the acquisition board if the FPGA updating configuration file is used for the acquisition board, and discards the FPGA updating configuration file if the FPGA updating configuration file is not used for the acquisition board;
in the acquisition board, a data receiving and caching module stores a received FPGA updating configuration file into an RAM, a configuration file analyzing module reads the FPGA updating configuration file from the RAM and analyzes the FPGA updating configuration file into a standard JTAG data flow, a GPIO simulation JTAG module receives the JTAG standard data flow and acquires corresponding JTAG level information from the JTAG standard data flow, a driving program is called according to the level information to control the output level of pins of a GPIO interface in a DSP, and the JTAG interface processes a programmable logic unit according to the level information to complete the online updating of the FPGA configuration file.
2. The device for the on-line updating of the FPGA configuration file of the three-dimensional acoustic tool according to claim 1, wherein the FPGA updating configuration file is a DAT format file.
3. The device for updating the FPGA configuration file of the three-dimensional acoustic logging instrument in the online manner as recited in claim 1, wherein the microprocessor is an ARM9 chip of Samsung corporation with the model number S3C 2440A;
the external data memory adopts a K9F2G08U0A chip with the capacity of 256 MB;
the DSP of the collection board and the DSP of the control board adopt a chip of TI company with the model number of TMS320F2812, and the FPGA adopts a chip of Actel company with the model number of A3P 1000.
4. The FPGA configuration file online updating device of the three-dimensional acoustic logging instrument as recited in claim 1, wherein the GPIO interface is connected to 4 JTAG pins corresponding to the JTAG interface by using 4 GPIO pins, and the level output of the 4 GPIO pins must satisfy the timing sequence requirement of the 4 JTAG pins;
the 4 JTAG pins comprise 4 necessary signals which are TMS, TDI, TDO and TCK respectively; TMS signal is output signal, which is used to control the conversion of JTAG state machine; the TDI signal is also an output signal and is an interface for inputting JTAG scan chain data, all data to be input into a specific register are serially input according to bits through the TDI interface, the TDO signal is a device feedback signal returned from the JTAG scan chain, the TCK is a clock signal control signal for JTAG input and output data flow, and the input and output functions of TMS, TDI and TDO signals are directly controlled through the TCK signal; the signals TMS and TDI need to be latched and output to the JTAG scan chain at the falling edge of the TCK clock signal, while the TDO feedback signal is active at the rising edge of the TCK clock signal.
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| CN108519889B (en) * | 2018-03-22 | 2021-06-11 | 深圳华中科技大学研究院 | JTAG standard-based FPGA program remote upgrading system and method |
| CN109614126B (en) * | 2018-10-23 | 2022-07-01 | 北京全路通信信号研究设计院集团有限公司 | Embedded system online program upgrading method and device |
| CN109597777A (en) * | 2018-12-11 | 2019-04-09 | 济南浪潮高新科技投资发展有限公司 | A kind of MCBSP interface inter-link device and method based on FPGA |
| CN109840233B (en) * | 2019-01-25 | 2020-10-27 | 上海创景信息科技有限公司 | 60X bus bridging system, method and medium based on FPGA |
| CN111309353B (en) * | 2020-01-20 | 2023-05-23 | 超越科技股份有限公司 | Method and equipment for updating operation board FPGA firmware based on server control board |
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